tyler.durden/audk
1
0
Fork 0
mirror of https://github.com/acidanthera/audk.git synced 2025-07-03 20:04:23 +02:00
Code Issues Packages Projects Releases Wiki Activity

UefiCpuPkg/MtrrLib: MtrrLibInitializeMtrrMask() uses definitions in CpuId.h

Browse Source 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
This commit is contained in:
Ruiyu Ni 2016-09-02 20:23:35 +08:00
parent b8f015999e
commit 012f4054db
1 changed files with 9 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
UefiCpuPkg/Library/MtrrLib/MtrrLib.c
View File

@ -1054,22 +1054,20 @@ MtrrLibInitializeMtrrMask (
OUT UINT64 *MtrrValidAddressMask OUT UINT64 *MtrrValidAddressMask
) )
{ {
UINT32 RegEax; UINT32 MaxExtendedFunction;
UINT8 PhysicalAddressBits; CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000008) { AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL);
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
PhysicalAddressBits = (UINT8) RegEax; if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL);
*MtrrValidBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
*MtrrValidAddressMask = *MtrrValidBitsMask & 0xfffffffffffff000ULL;
} else { } else {
*MtrrValidBitsMask = MTRR_LIB_MSR_VALID_MASK; VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
*MtrrValidAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
} }
*MtrrValidBitsMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;
*MtrrValidAddressMask = *MtrrValidBitsMask & 0xfffffffffffff000ULL;
} }