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ArmPkg/ArmLib: Drain Write Buffer before DCache maintenance operations. 

Cache maintenance operations by Set/Way require that the Write Buffer
be drained before the cache is flushed.  Without that, the flush can
miss the most recent values written as they are still "pipelined".
That has unfortunate consequences, especially where code is being
copied to RAM.
The fix is to add DSB instructions before the affected operations.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15551 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin 2014-06-03 16:37:29 +00:00 committed by oliviermartin
parent 8b7f930a14
commit 01674afdad
3 changed files with 12 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
View File

@ -1,6 +1,7 @@
/** @file /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
@ -28,6 +29,7 @@ CacheRangeOperation (
UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold); UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) { if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {
ArmDrainWriteBuffer ();
CacheOperation (); CacheOperation ();
} else { } else {
// Align address (rounding down) // Align address (rounding down)

6
ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
View File

@ -1,7 +1,7 @@
/** @file /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR> Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
@ -232,6 +232,7 @@ ArmInvalidateDataCache (
VOID VOID
) )
{ {
ArmDrainWriteBuffer ();
AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay); AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
} }
@ -241,6 +242,7 @@ ArmCleanInvalidateDataCache (
VOID VOID
) )
{ {
ArmDrainWriteBuffer ();
AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay); AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
} }
@ -250,6 +252,7 @@ ArmCleanDataCache (
VOID VOID
) )
{ {
ArmDrainWriteBuffer ();
AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay); AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
} }
@ -259,5 +262,6 @@ ArmCleanDataCacheToPoU (
VOID VOID
) )
{ {
ArmDrainWriteBuffer ();
AArch64PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay); AArch64PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
} }

5
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
View File

@ -1,6 +1,7 @@
/** @file /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
@ -233,6 +234,7 @@ ArmInvalidateDataCache (
VOID VOID
) )
{ {
ArmDrainWriteBuffer ();
ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay); ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
} }
@ -242,6 +244,7 @@ ArmCleanInvalidateDataCache (
VOID VOID
) )
{ {
ArmDrainWriteBuffer ();
ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay); ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
} }
@ -251,6 +254,7 @@ ArmCleanDataCache (
VOID VOID
) )
{ {
ArmDrainWriteBuffer ();
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay); ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
} }
@ -260,5 +264,6 @@ ArmCleanDataCacheToPoU (
VOID VOID
) )
{ {
ArmDrainWriteBuffer ();
ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay); ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
} }