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UefiCpuPkg/CpuDxe: Remove MSR_IA32_MISC_ENABLE check 

The architectural MSR MSR_IA32_MISC_ENABLE is not supported by AMD processors.
Because reading CPUID.80000001H:EDK[20] is enough to check if XD feature is
supported or not, we just remove checking MSR_IA32_MISC_ENABLE(0x1A0).

Cc: Anthony PERARD <anthony.perard@citrix.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
This commit is contained in:
Jeff Fan 2017-03-15 09:47:52 +08:00
parent 78807f6050
commit 01eb3f39bb
1 changed files with 3 additions and 6 deletions
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9
UefiCpuPkg/CpuDxe/CpuPageTable.c
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@ -193,12 +193,9 @@ GetCurrentPagingContext (
AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
if ((RegEdx & BIT20) != 0) {
// XD supported
if ((AsmReadMsr64 (0x000001A0) & BIT34) == 0) {
// XD enabled
if ((AsmReadMsr64 (0xC0000080) & BIT11) != 0) {
// XD activated
PagingContext->ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED;
}
if ((AsmReadMsr64 (0xC0000080) & BIT11) != 0) {
// XD activated
PagingContext->ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED;
}
}
if ((RegEdx & BIT26) != 0) {