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ArmPlatformPkg: Retire PrePeiCore

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Retire the PrePeiCore SEC driver, which has been replaced by Sec.inf

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Ard Biesheuvel 2024-07-31 15:20:25 +02:00 committed by mergify[bot]
parent 76c5f035a1
commit 029c7a2829
14 changed files with 0 additions and 877 deletions
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1
ArmPlatformPkg/ArmPlatformPkg.dsc
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@ -118,7 +118,6 @@
ArmPlatformPkg/PlatformPei/PlatformPeim.inf
ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
ArmPlatformPkg/Sec/Sec.inf
ArmPlatformPkg/PrePi/PeiUniCore.inf

46
ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c
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@ -1,46 +0,0 @@
/** @file
Main file supporting the transition to PEI Core in Normal World for Versatile Express
Copyright (c) 2012-2013, ARM Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
#include "PrePeiCore.h"
VOID
PeiCommonExceptionEntry (
IN UINT32 Entry,
IN UINTN LR
)
{
CHAR8 Buffer[100];
UINTN CharCount;
switch (Entry) {
case EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS:
CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Synchronous Exception at 0x%X\n\r", LR);
break;
case EXCEPT_AARCH64_IRQ:
CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "IRQ Exception at 0x%X\n\r", LR);
break;
case EXCEPT_AARCH64_FIQ:
CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "FIQ Exception at 0x%X\n\r", LR);
break;
case EXCEPT_AARCH64_SERROR:
CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "SError/Abort Exception at 0x%X\n\r", LR);
break;
default:
CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Unknown Exception at 0x%X\n\r", LR);
break;
}
SerialPortWrite ((UINT8 *)Buffer, CharCount);
while (1) {
}
}

116
ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
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@ -1,116 +0,0 @@
#
# Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#include <AArch64/AArch64.h>
#include <AsmMacroIoLibV8.h>
#include <Base.h>
#include <AutoGen.h>
.text
//============================================================
//Default Exception Handlers
//============================================================
#define TO_HANDLER \
EL1_OR_EL2(x1) \
1: mrs x1, elr_el1 /* EL1 Exception Link Register */ ;\
b 3f ;\
2: mrs x1, elr_el2 /* EL2 Exception Link Register */ ;\
3: bl ASM_PFX(PeiCommonExceptionEntry) ;
//
// Default Exception handlers: There is no plan to return from any of these exceptions.
// No context saving at all.
//
VECTOR_BASE(PeiVectorTable)
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SYNC)
_DefaultSyncExceptHandler_t:
mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_IRQ)
_DefaultIrq_t:
mov x0, #EXCEPT_AARCH64_IRQ
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_FIQ)
_DefaultFiq_t:
mov x0, #EXCEPT_AARCH64_FIQ
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SERR)
_DefaultSError_t:
mov x0, #EXCEPT_AARCH64_SERROR
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_SYNC)
_DefaultSyncExceptHandler_h:
mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_IRQ)
_DefaultIrq_h:
mov x0, #EXCEPT_AARCH64_IRQ
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_FIQ)
_DefaultFiq_h:
mov x0, #EXCEPT_AARCH64_FIQ
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_SERR)
_DefaultSError_h:
mov x0, #EXCEPT_AARCH64_SERROR
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SYNC)
_DefaultSyncExceptHandler_LowerA64:
mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_IRQ)
_DefaultIrq_LowerA64:
mov x0, #EXCEPT_AARCH64_IRQ
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_FIQ)
_DefaultFiq_LowerA64:
mov x0, #EXCEPT_AARCH64_FIQ
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SERR)
_DefaultSError_LowerA64:
mov x0, #EXCEPT_AARCH64_SERROR
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SYNC)
_DefaultSyncExceptHandler_LowerA32:
mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_IRQ)
_DefaultIrq_LowerA32:
mov x0, #EXCEPT_AARCH64_IRQ
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_FIQ)
_DefaultFiq_LowerA32:
mov x0, #EXCEPT_AARCH64_FIQ
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SERR)
_DefaultSError_LowerA32:
mov x0, #EXCEPT_AARCH64_SERROR
TO_HANDLER
VECTOR_END(PeiVectorTable)
AARCH64_BTI_NOTE()

42
ArmPlatformPkg/PrePeiCore/AArch64/Helper.S
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@ -1,42 +0,0 @@
#========================================================================================
# Copyright (c) 2011-2017, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#=======================================================================================
#include <AsmMacroIoLibV8.h>
#include <AArch64/AArch64.h>
// Setup EL1 while in EL1
ASM_FUNC(SetupExceptionLevel1)
mov x5, x30 // Save LR
mov x0, #CPACR_CP_FULL_ACCESS
bl ASM_PFX(ArmWriteCpacr) // Disable copro traps to EL1
ret x5
// Setup EL2 while in EL2
ASM_FUNC(SetupExceptionLevel2)
msr sctlr_el2, xzr
mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register
// Send all interrupts to their respective Exception levels for EL2
orr x0, x0, #(1 << 3) // Enable EL2 FIQ
orr x0, x0, #(1 << 4) // Enable EL2 IRQ
orr x0, x0, #(1 << 5) // Enable EL2 SError and Abort
msr hcr_el2, x0 // Write back our settings
msr cptr_el2, xzr // Disable copro traps to EL2
// Enable Timer access for non-secure EL1 and EL0
// The cnthctl_el2 register bits are architecturally
// UNKNOWN on reset.
// Disable event stream as it is not in use at this stage
mov x0, #(CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN)
msr cnthctl_el2, x0
ret
ASM_FUNCTION_REMOVE_IF_UNREFERENCED

61
ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S
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@ -1,61 +0,0 @@
//
// Copyright (c) 2011-2014, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//
#include <AsmMacroIoLibV8.h>
ASM_FUNC(_ModuleEntryPoint)
// Do early platform specific actions
bl ASM_PFX(ArmPlatformPeiBootAction)
// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect
// and configure the system accordingly. EL2 is default if possible.
// If we started in EL3 we need to switch and run at EL2.
// If we are running at EL2 stay in EL2
// If we are starting at EL1 stay in EL1.
// If started at EL3 Sec is run and switches to EL2 before jumping to PEI.
// If started at EL1 or EL2 Sec jumps directly to PEI without making any
// changes.
// Which EL are we running at? Every EL needs some level of setup...
// We should not run this code in EL3
EL1_OR_EL2(x0)
1:bl ASM_PFX(SetupExceptionLevel1)
b ASM_PFX(MainEntryPoint)
2:bl ASM_PFX(SetupExceptionLevel2)
b ASM_PFX(MainEntryPoint)
ASM_PFX(MainEntryPoint):
// Get the top of the primary stacks (and the base of the secondary stacks)
MOV64 (x1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCorePrimaryStackSize))
// Set up the stack pointer
mov sp, x1
// Apply the init value to the entire stack
MOV64 (x8, FixedPcdGet64 (PcdCPUCoresStackBase))
MOV64 (x9, FixedPcdGet32 (PcdInitValueInTempStack) |\
FixedPcdGet32 (PcdInitValueInTempStack) << 32)
0:stp x9, x9, [x8], #16
cmp x8, x1
b.lt 0b
// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
MOV64 (x2, FixedPcdGet64(PcdFvBaseAddress))
ldr x0, [x2, #8]
// Move sec startup address into a data register
// Ensure we're jumping to FV version of the code (not boot remapped alias)
ldr x3, =ASM_PFX(CEntryPoint)
// Set the frame pointer to NULL so any backtraces terminate here
mov x29, xzr
// Jump to PrePeiCore C code
// x0 = pei_core_address
mov x0, x5
blr x3

32
ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S
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@ -1,32 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#------------------------------------------------------------------------------
#include <AsmMacroIoLibV8.h>
#/**
# This allows the caller to switch the stack and return
#
# @param StackDelta Signed amount by which to modify the stack pointer
#
# @return Nothing. Goes to the Entry Point passing in the new parameters
#
#**/
#VOID
#EFIAPI
#SecSwitchStack (
# VOID *StackDelta
# )#
#
ASM_FUNC(SecSwitchStack)
mov x1, sp
add x1, x0, x1
mov sp, x1
ret

57
ArmPlatformPkg/PrePeiCore/Arm/ArchPrePeiCore.c
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@ -1,57 +0,0 @@
/** @file
Main file supporting the transition to PEI Core in Normal World for Versatile Express
Copyright (c) 2012, ARM Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
#include "PrePeiCore.h"
VOID
PeiCommonExceptionEntry (
IN UINT32 Entry,
IN UINTN LR
)
{
CHAR8 Buffer[100];
UINTN CharCount;
switch (Entry) {
case 0:
CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Reset Exception at 0x%X\n\r", LR);
break;
case 1:
CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Undefined Exception at 0x%X\n\r", LR);
break;
case 2:
CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "SWI Exception at 0x%X\n\r", LR);
break;
case 3:
CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "PrefetchAbort Exception at 0x%X\n\r", LR);
break;
case 4:
CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "DataAbort Exception at 0x%X\n\r", LR);
break;
case 5:
CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Reserved Exception at 0x%X\n\r", LR);
break;
case 6:
CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "IRQ Exception at 0x%X\n\r", LR);
break;
case 7:
CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "FIQ Exception at 0x%X\n\r", LR);
break;
default:
CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Unknown Exception at 0x%X\n\r", LR);
break;
}
SerialPortWrite ((UINT8 *)Buffer, CharCount);
while (1) {
}
}

96
ArmPlatformPkg/PrePeiCore/Arm/Exception.S
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@ -1,96 +0,0 @@
//
// Copyright (c) 2011, ARM Limited. All rights reserved.
//
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#include <AsmMacroIoLib.h>
#include <Base.h>
#include <AutoGen.h>
#start of the code section
.text
.align 5
# IMPORT
GCC_ASM_IMPORT(PeiCommonExceptionEntry)
# EXPORT
GCC_ASM_EXPORT(PeiVectorTable)
//============================================================
//Default Exception Handlers
//============================================================
ASM_PFX(PeiVectorTable):
b _DefaultResetHandler
b _DefaultUndefined
b _DefaultSWI
b _DefaultPrefetchAbort
b _DefaultDataAbort
b _DefaultReserved
b _DefaultIrq
b _DefaultFiq
//
// Default Exception handlers: There is no plan to return from any of these exceptions.
// No context saving at all.
//
_DefaultResetHandler:
mov r1, lr
# Switch to SVC for common stack
cps #0x13
mov r0, #0
blx ASM_PFX(PeiCommonExceptionEntry)
_DefaultUndefined:
sub r1, LR, #4
# Switch to SVC for common stack
cps #0x13
mov r0, #1
blx ASM_PFX(PeiCommonExceptionEntry)
_DefaultSWI:
sub r1, LR, #4
# Switch to SVC for common stack
cps #0x13
mov r0, #2
blx ASM_PFX(PeiCommonExceptionEntry)
_DefaultPrefetchAbort:
sub r1, LR, #4
# Switch to SVC for common stack
cps #0x13
mov r0, #3
blx ASM_PFX(PeiCommonExceptionEntry)
_DefaultDataAbort:
sub r1, LR, #8
# Switch to SVC for common stack
cps #0x13
mov r0, #4
blx ASM_PFX(PeiCommonExceptionEntry)
_DefaultReserved:
mov r1, lr
# Switch to SVC for common stack
cps #0x13
mov r0, #5
blx ASM_PFX(PeiCommonExceptionEntry)
_DefaultIrq:
sub r1, LR, #4
# Switch to SVC for common stack
cps #0x13
mov r0, #6
blx ASM_PFX(PeiCommonExceptionEntry)
_DefaultFiq:
sub r1, LR, #4
# Switch to SVC for common stack
cps #0x13
mov r0, #7
blx ASM_PFX(PeiCommonExceptionEntry)

40
ArmPlatformPkg/PrePeiCore/Arm/PrePeiCoreEntryPoint.S
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@ -1,40 +0,0 @@
//
// Copyright (c) 2011-2013, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//
#include <AsmMacroIoLib.h>
ASM_FUNC(_ModuleEntryPoint)
// Do early platform specific actions
bl ASM_PFX(ArmPlatformPeiBootAction)
// Get the top of the primary stacks (and the base of the secondary stacks)
MOV32 (r1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCorePrimaryStackSize))
// Set up the stack pointer
mov sp, r1
// Apply the init value to the entire stack
MOV32 (r8, FixedPcdGet64 (PcdCPUCoresStackBase))
MOV32 (r9, FixedPcdGet32 (PcdInitValueInTempStack))
mov r10, r9
mov r11, r9
mov r12, r9
0:stm r8!, {r9-r12}
cmp r8, r1
blt 0b
// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
MOV32 (r2, FixedPcdGet32(PcdFvBaseAddress))
ldr r0, [r2, #4]
// Move sec startup address into a data register
// Ensure we're jumping to FV version of the code (not boot remapped alias)
ldr r3, =ASM_PFX(CEntryPoint)
// Jump to PrePeiCore C code
// r0 = pei_core_address
blx r3

32
ArmPlatformPkg/PrePeiCore/Arm/SwitchStack.S
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@ -1,32 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#------------------------------------------------------------------------------
#include <AsmMacroIoLib.h>
#/**
# This allows the caller to switch the stack and return
#
# @param StackDelta Signed amount by which to modify the stack pointer
#
# @return Nothing. Goes to the Entry Point passing in the new parameters
#
#**/
#VOID
#EFIAPI
#SecSwitchStack (
# VOID *StackDelta
# )#
#
ASM_FUNC(SecSwitchStack)
mov R1, R13
add R1, R0, R1
mov R13, R1
bx LR

48
ArmPlatformPkg/PrePeiCore/MainUniCore.c
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@ -1,48 +0,0 @@
/** @file
Copyright (c) 2011-2012, ARM Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "PrePeiCore.h"
VOID
EFIAPI
PrimaryMain (
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
)
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
UINTN PpiListSize;
EFI_PEI_PPI_DESCRIPTOR *PpiList;
UINTN TemporaryRamBase;
UINTN TemporaryRamSize;
CreatePpiList (&PpiListSize, &PpiList);
// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
// the base of the primary core stack
PpiListSize = ALIGN_VALUE (PpiListSize, CPU_STACK_ALIGNMENT);
TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
//
// Bind this information into the SEC hand-off state
// Note: this must be in sync with the stuff in the asm file
// Note also: HOBs (pei temp ram) MUST be above stack
//
SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);
SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);
SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)
SecCoreData.TemporaryRamSize = TemporaryRamSize;
SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
SecCoreData.PeiTemporaryRamSize = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);
SecCoreData.StackBase = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;
// Jump to PEI core entry point
(PeiCoreEntryPoint)(&SecCoreData, PpiList);
}

179
ArmPlatformPkg/PrePeiCore/PrePeiCore.c
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@ -1,179 +0,0 @@
/** @file
Main file supporting the transition to PEI Core in Normal World for Versatile Express
Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Library/BaseLib.h>
#include <Library/CacheMaintenanceLib.h>
#include <Library/DebugAgentLib.h>
#include <Library/ArmLib.h>
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
#include "PrePeiCore.h"
CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };
CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI,
&gEfiTemporaryRamSupportPpiGuid,
(VOID *)&mTemporaryRamSupportPpi
}
};
VOID
CreatePpiList (
OUT UINTN *PpiListSize,
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
)
{
EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;
UINTN PlatformPpiListSize;
UINTN ListBase;
EFI_PEI_PPI_DESCRIPTOR *LastPpi;
// Get the Platform PPIs
PlatformPpiListSize = 0;
ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);
// Copy the Common and Platform PPis in Temporary Memory
ListBase = PcdGet64 (PcdCPUCoresStackBase);
CopyMem ((VOID *)ListBase, gCommonPpiTable, sizeof (gCommonPpiTable));
CopyMem ((VOID *)(ListBase + sizeof (gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);
// Set the Terminate flag on the last PPI entry
LastPpi = (EFI_PEI_PPI_DESCRIPTOR *)ListBase + ((sizeof (gCommonPpiTable) + PlatformPpiListSize) / sizeof (EFI_PEI_PPI_DESCRIPTOR)) - 1;
LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
*PpiList = (EFI_PEI_PPI_DESCRIPTOR *)ListBase;
*PpiListSize = sizeof (gCommonPpiTable) + PlatformPpiListSize;
}
/**
Prints firmware version and build time to serial console.
**/
STATIC
VOID
PrintFirmwareVersion (
VOID
)
{
CHAR8 Buffer[100];
UINTN CharCount;
CharCount = AsciiSPrint (
Buffer,
sizeof (Buffer),
"UEFI firmware (version %s built at %a on %a)\n\r",
(CHAR16 *)PcdGetPtr (PcdFirmwareVersionString),
__TIME__,
__DATE__
);
// Because we are directly bit banging the serial port instead of going through the DebugLib, we need to make sure
// the serial port is initialized before we write to it
SerialPortInitialize ();
SerialPortWrite ((UINT8 *)Buffer, CharCount);
}
VOID
CEntryPoint (
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
)
{
if (!ArmMmuEnabled ()) {
// Data Cache enabled on Primary core when MMU is enabled.
ArmDisableDataCache ();
// Invalidate instruction cache
ArmInvalidateInstructionCache ();
// Enable Instruction Caches on all cores.
ArmEnableInstructionCache ();
InvalidateDataCacheRange (
(VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
PcdGet32 (PcdCPUCorePrimaryStackSize)
);
}
//
// Note: Doesn't have to Enable CPU interface in non-secure world,
// as Non-secure interface is already enabled in Secure world.
//
// Write VBAR - The Exception Vector table must be aligned to its requirement
// Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
// 'Align=4K' is defined into your FDF for this module.
ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
ArmWriteVBar ((UINTN)PeiVectorTable);
// Enable Floating Point
if (FixedPcdGet32 (PcdVFPEnabled)) {
ArmEnableVFP ();
}
// Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
// Invoke "ProcessLibraryConstructorList" to have all library constructors
// called.
ProcessLibraryConstructorList ();
PrintFirmwareVersion ();
// Initialize the Debug Agent for Source Level Debugging
InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
SaveAndSetDebugTimerInterrupt (TRUE);
// Initialize the platform specific controllers
ArmPlatformInitialize (ArmReadMpidr ());
// Goto primary Main.
PrimaryMain (PeiCoreEntryPoint);
// PEI Core should always load and never return
ASSERT (FALSE);
}
EFI_STATUS
EFIAPI
PrePeiCoreTemporaryRamSupport (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
IN UINTN CopySize
)
{
VOID *OldHeap;
VOID *NewHeap;
VOID *OldStack;
VOID *NewStack;
UINTN HeapSize;
HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);
OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;
NewHeap = (VOID *)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));
OldStack = (VOID *)((UINTN)TemporaryMemoryBase + HeapSize);
NewStack = (VOID *)(UINTN)PermanentMemoryBase;
//
// Migrate the temporary memory stack to permanent memory stack.
//
CopyMem (NewStack, OldStack, CopySize - HeapSize);
//
// Migrate the temporary memory heap to permanent memory heap.
//
CopyMem (NewHeap, OldHeap, HeapSize);
SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);
return EFI_SUCCESS;
}

61
ArmPlatformPkg/PrePeiCore/PrePeiCore.h
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@ -1,61 +0,0 @@
/** @file
Main file supporting the transition to PEI Core in Normal World for Versatile Express
Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __PREPEICORE_H_
#define __PREPEICORE_H_
#include <Library/ArmLib.h>
#include <Library/ArmPlatformLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <PiPei.h>
#include <Ppi/TemporaryRamSupport.h>
VOID
CreatePpiList (
OUT UINTN *PpiListSize,
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
);
EFI_STATUS
EFIAPI
PrePeiCoreTemporaryRamSupport (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
IN UINTN CopySize
);
VOID
SecSwitchStack (
INTN StackDelta
);
// Vector Table for Pei Phase
VOID
PeiVectorTable (
VOID
);
VOID
EFIAPI
PrimaryMain (
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
);
VOID
PeiCommonExceptionEntry (
IN UINT32 Entry,
IN UINTN LR
);
#endif

66
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
View File

@ -1,66 +0,0 @@
#/** @file
# Pre PeiCore - Hand-off to PEI Core in Normal World
#
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 1.30
BASE_NAME = ArmPlatformPrePeiCore
FILE_GUID = 469fc080-aec1-11df-927c-0002a5d5c51b
MODULE_TYPE = SEC
VERSION_STRING = 1.0
[Sources.common]
PrePeiCore.h
PrePeiCore.c
MainUniCore.c
[Sources.ARM]
Arm/ArchPrePeiCore.c
Arm/PrePeiCoreEntryPoint.S | GCC
Arm/SwitchStack.S | GCC
Arm/Exception.S | GCC
[Sources.AARCH64]
AArch64/ArchPrePeiCore.c
AArch64/PrePeiCoreEntryPoint.S
AArch64/SwitchStack.S
AArch64/Exception.S
AArch64/Helper.S
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
[LibraryClasses]
ArmLib
ArmPlatformLib
CacheMaintenanceLib
BaseLib
DebugLib
DebugAgentLib
IoLib
PrintLib
SerialPortLib
[Ppis]
gEfiTemporaryRamSupportPpiGuid
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
[FixedPcd]
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdFvSize
gArmTokenSpaceGuid.PcdVFPEnabled
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize
gEfiMdeModulePkgTokenSpaceGuid.PcdInitValueInTempStack