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UefiCpuPkg/CpuPageTableLib/TestCase: Refine test case for PAE paging.

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Refine test case:
1. Check PAE paging reserved bits is zero.
2. Set stack as random value.

Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
This commit is contained in:
Zhiguang Liu 2023-11-27 14:31:06 +08:00 committed by mergify[bot]
parent c83ffd2676
commit 02d6f39bd5
2 changed files with 34 additions and 4 deletions
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24
UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
View File

@ -138,6 +138,23 @@ RandomBoolean (
return ((Probability > ((UINT8)Random64 (0, 100))) ? TRUE : FALSE);
}
/**
Set 8K stack as random value.
**/
VOID
SetRandomStack (
VOID
)
{
UINT64 Buffer[SIZE_1KB];
UINTN Index;
for (Index = 0; Index < SIZE_1KB; Index++) {
Buffer[Index] = Random64 (0, MAX_UINT64);
Buffer[Index] = Buffer[Index];
}
}
/**
Check if the Page table entry is valid
@ -670,6 +687,7 @@ SingleMapEntryTest (
IsNotPresent = FALSE;
IsModified = FALSE;
SetRandomStack ();
GenerateSingleRandomMapEntry (MaxAddress, MapEntrys);
LastMapEntry = &MapEntrys->Maps[MapsIndex];
Status = PageTableParse (*PageTable, PagingMode, NULL, &MapCount);
@ -1039,7 +1057,11 @@ TestCaseforRandomTest (
mSupportedBit.Bits.Pat = 1;
mSupportedBit.Bits.Global = 1;
mSupportedBit.Bits.ProtectionKey = 0xF;
mSupportedBit.Bits.Nx = 1;
if (((CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT *)Context)->PagingMode == PagingPae) {
mSupportedBit.Bits.ProtectionKey = 0;
}
mSupportedBit.Bits.Nx = 1;
mRandomOption = ((CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT *)Context)->RandomOption;
mNumberIndex = 0;

14
UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c
View File

@ -9,6 +9,7 @@
#include "CpuPageTableLibUnitTest.h"
#include "../CpuPageTable.h"
#define IA32_PAE_RESERVED_MASK 0x7FF0000000000000ull
//
// Global Data to validate if the page table is legal
// mValidMaskNoLeaf[0] is not used
@ -95,6 +96,7 @@ InitGlobalData (
@param[in] Level the level of PagingEntry.
@param[in] MaxLeafLevel Max leaf entry level.
@param[in] LinearAddress The linear address verified.
@param[in] PagingMode The paging mode.
@retval Leaf entry.
**/
@ -103,13 +105,18 @@ IsPageTableEntryValid (
IN IA32_PAGING_ENTRY *PagingEntry,
IN UINTN Level,
IN UINTN MaxLeafLevel,
IN UINT64 Address
IN UINT64 Address,
IN PAGING_MODE PagingMode
)
{
UINT64 Index;
IA32_PAGING_ENTRY *ChildPageEntry;
UNIT_TEST_STATUS Status;
if (PagingMode == PagingPae) {
UT_ASSERT_EQUAL (PagingEntry->Uint64 & IA32_PAE_RESERVED_MASK, 0);
}
if (PagingEntry->Pce.Present == 0) {
return UNIT_TEST_PASSED;
}
@ -142,7 +149,7 @@ IsPageTableEntryValid (
ChildPageEntry = (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&PagingEntry->Pnle));
for (Index = 0; Index < 512; Index++) {
Status = IsPageTableEntryValid (&ChildPageEntry[Index], Level-1, MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3)));
Status = IsPageTableEntryValid (&ChildPageEntry[Index], Level-1, MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3)), PagingMode);
if (Status != UNIT_TEST_PASSED) {
return Status;
}
@ -190,9 +197,10 @@ IsPageTableValid (
if (PagingMode == PagingPae) {
UT_ASSERT_EQUAL (PagingEntry[Index].PdptePae.Bits.MustBeZero, 0);
UT_ASSERT_EQUAL (PagingEntry[Index].PdptePae.Bits.MustBeZero2, 0);
UT_ASSERT_EQUAL (PagingEntry[Index].PdptePae.Bits.MustBeZero3, 0);
}
Status = IsPageTableEntryValid (&PagingEntry[Index], MaxLevel, MaxLeafLevel, Index << (9 * MaxLevel + 3));
Status = IsPageTableEntryValid (&PagingEntry[Index], MaxLevel, MaxLeafLevel, Index << (9 * MaxLevel + 3), PagingMode);
if (Status != UNIT_TEST_PASSED) {
return Status;
}