mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg: Add CpuMmuLib to UefiCpuPkg
Add a new base library named CpuMmuLib and add a LoongArch64 instance with in the library. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734 Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn> Co-authored-by: Dongyan Qian <qiandongyan@loongson.cn> Co-authored-by: Xianglai Li <lixianglai@loongson.cn> Co-authored-by: Bibo Mao <maobibo@loongson.cn> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
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## @file
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# CPU Memory Manager Unit library instance.
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#
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# Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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[Defines]
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INF_VERSION = 1.29
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BASE_NAME = CpuMmuLib
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MODULE_UNI_FILE = CpuMmuLib.uni
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FILE_GUID = DA8F0232-FB14-42F0-922C-63104D2C70BE
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MODULE_TYPE = BASE
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VERSION_STRING = 1.0
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LIBRARY_CLASS = CpuMmuLib
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#
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# VALID_ARCHITECTURES = LOONGARCH64
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#
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[Sources.LoongArch64]
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LoongArch64/TlbInvalid.S | GCC
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LoongArch64/TlbExceptionHandle.S | GCC
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LoongArch64/CpuMmu.c
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LoongArch64/Page.h
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LoongArch64/TlbInvalid.h
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[Packages]
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MdePkg/MdePkg.dec
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UefiCpuPkg/UefiCpuPkg.dec
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[LibraryClasses]
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DebugLib
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MemoryAllocationLib
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[Pcd.LoongArch64]
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gUefiCpuPkgTokenSpaceGuid.PcdLoongArchExceptionVectorBaseAddress ## CONSUMES
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// /** @file
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// CPU Memory Manager Unit library instance.
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//
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// CPU Memory Manager Unit library instance.
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//
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// Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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// **/
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#string STR_MODULE_ABSTRACT #language en-US "CPU Memory Manager Unit library instance."
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#string STR_MODULE_DESCRIPTION #language en-US "CPU Memory Manager Unit library instance."
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@ -0,0 +1,784 @@
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/** @file
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CPU Memory Map Unit Handler Library common functions.
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Copyright (c) 2011-2020, ARM Limited. All rights reserved.
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Copyright (c) 2016, Linaro Limited. All rights reserved.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.<BR>
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Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/CacheMaintenanceLib.h>
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#include <Library/CpuMmuLib.h>
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#include <Library/DebugLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Protocol/DebugSupport.h>
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#include <Register/LoongArch64/Csr.h>
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#include "TlbInvalid.h"
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#include "TlbExceptionHandle.h"
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#include "Page.h"
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/**
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Check to see if mmu successfully initializes.
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@param VOID.
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@retval TRUE Initialization has been completed.
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FALSE Initialization did not complete.
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**/
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STATIC
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BOOLEAN
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MmuIsInit (
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VOID
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)
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{
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if (CsrRead (LOONGARCH_CSR_PGDL) != 0) {
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return TRUE;
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}
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return FALSE;
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}
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/**
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Check to see if mmu is enabled.
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@param VOID.
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@retval TRUE MMU has been enabled.
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FALSE MMU did not enabled.
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**/
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STATIC
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BOOLEAN
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MmuIsEnabled (
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VOID
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)
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{
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if ((CsrRead (LOONGARCH_CSR_CRMD) & BIT4) != 0) {
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return TRUE;
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}
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return FALSE;
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}
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/**
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Determine if an entry is valid pte.
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@param Entry The entry value.
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@retval TRUE The entry is a valid pte.
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@retval FALSE The entry is not a valid pte.
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**/
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STATIC
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BOOLEAN
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IsValidPte (
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IN UINTN Entry
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)
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{
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if (Entry != INVALID_PAGE) {
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return TRUE;
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} else {
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return FALSE;
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}
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}
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/**
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Determine if an entry is huge page.
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@param Entry The entry value.
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@retval TRUE The entry is a huge page.
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@retval FALSE The entry is not a valid huge page.
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**/
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STATIC
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BOOLEAN
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IsValidHugePage (
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IN UINTN Entry
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)
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{
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if ((Entry & (PAGE_HGLOBAL | PAGE_HUGE)) == (PAGE_HGLOBAL | PAGE_HUGE)) {
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return TRUE;
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} else {
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return FALSE;
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}
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}
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/**
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Set an entry to be a valid pte.
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@param Entry The entry value.
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@return The entry value.
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**/
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STATIC
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UINTN
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SetValidPte (
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IN UINTN Entry
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)
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{
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/* Set Valid and Global mapping bits */
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return Entry | PAGE_GLOBAL | PAGE_VALID;
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}
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/**
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Parse max page table level.
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@param[in] PageWalkCfg Page table configure value.
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@return 5 MAX page level is 5
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4 MAX page level is 4
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3 MAX page level is 3
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0 Invalid
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**/
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STATIC
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UINTN
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ParseMaxPageTableLevel (
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IN UINT64 PageWalkCfg
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)
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{
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UINT32 Pwctl0;
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UINT32 Pwctl1;
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Pwctl0 = PageWalkCfg & MAX_UINT32;
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Pwctl1 = (PageWalkCfg >> 32) & MAX_UINT32;
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if (((Pwctl1 >> 18) & 0x3F) != 0x0) {
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return LEVEL5;
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} else if (((Pwctl1 >> 6) & 0x3F) != 0x0) {
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return LEVEL4;
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} else if (((Pwctl0 >> 25) & 0x3F) != 0x0) {
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return LEVEL3;
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}
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return 0;
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}
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/**
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Parse page table bit width.
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Assume that the bit width of the page table that each level is the same to PTwidth.
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@param[in] PageWalkCfg Page table configure value.
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@return page table bit width
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**/
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STATIC
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UINTN
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ParsePageTableBitWidth (
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IN UINT64 PageWalkCfg
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)
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{
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//
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// PTwidth
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//
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return ((PageWalkCfg >> 5) & 0x1F);
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}
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/**
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Determine if an entry is a HUGE PTE or 4K PTE.
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@param Entry The entry value.
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@param Level The current page table level.
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@param PageWalkCfg Page table configure value.
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@retval TRUE The entry is a block pte.
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@retval FALSE The entry is not a block pte.
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**/
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STATIC
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BOOLEAN
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IsBlockEntry (
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IN UINTN Entry,
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IN UINTN Level,
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IN UINT64 PageWalkCfg
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)
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{
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if (Level == (ParseMaxPageTableLevel (PageWalkCfg) - 1)) {
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return ((Entry & PAGE_VALID) == PAGE_VALID);
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}
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return IsValidHugePage (Entry);
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}
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/**
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Determine if an entry is a table pte.
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@param Entry The entry value.
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@param Level The current page table level.
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@param PageWalkCfg Page table configure value.
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@retval TRUE The entry is a table pte.
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@retval FALSE The entry is not a table pte.
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**/
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STATIC
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BOOLEAN
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IsTableEntry (
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IN UINTN Entry,
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IN UINTN Level,
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IN UINT64 PageWalkCfg
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)
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{
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if (Level == (ParseMaxPageTableLevel (PageWalkCfg) - 1)) {
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//
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// The last level is PAGE rather than Table.
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//
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return FALSE;
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}
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//
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// Is DIR4 or DIR3 or DIR2 a Huge Page ?
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//
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return (!IsValidHugePage (Entry)) && (IsValidPte (Entry));
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}
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/**
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Replace an existing entry with new value.
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@param Entry The entry pointer.
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@param Value The new entry value.
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@param RegionStart The start of region that new value affects.
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@param IsLiveBlockMapping TRUE if this is live update, FALSE otherwise.
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**/
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STATIC
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VOID
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ReplaceTableEntry (
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IN UINTN *Entry,
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IN UINTN Value,
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IN UINTN RegionStart,
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IN BOOLEAN IsLiveBlockMapping
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)
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{
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*Entry = Value;
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if (IsLiveBlockMapping && MmuIsInit ()) {
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InvalidTlb (RegionStart);
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}
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}
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/**
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Get an ppn value from an entry.
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@param Entry The entry value.
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@return The ppn value.
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**/
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STATIC
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UINTN
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GetPpnfromPte (
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IN UINTN Entry
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)
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{
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return ((Entry & PTE_PPN_MASK) >> PTE_PPN_SHIFT);
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}
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/**
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Set an ppn value to a entry.
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@param Entry The entry value.
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@param Address The address.
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@return The new entry value.
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**/
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STATIC
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UINTN
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SetPpnToPte (
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UINTN Entry,
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UINTN Address
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)
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{
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UINTN Ppn;
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Ppn = ((Address >> LOONGARCH_MMU_PAGE_SHIFT) << PTE_PPN_SHIFT);
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ASSERT (~(Ppn & ~PTE_PPN_MASK));
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Entry &= ~PTE_PPN_MASK;
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return Entry | Ppn;
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}
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/**
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Free resources of translation table recursively.
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@param TranslationTable The pointer of table.
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@param PageWalkCfg Page table configure value.
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@param Level The current level.
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**/
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STATIC
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VOID
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FreePageTablesRecursive (
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IN UINTN *TranslationTable,
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IN UINT64 PageWalkCfg,
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IN UINTN Level
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)
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{
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UINTN Index;
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UINTN TableEntryNum;
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TableEntryNum = (1 << ParsePageTableBitWidth (PageWalkCfg));
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if (Level < (ParseMaxPageTableLevel (PageWalkCfg) - 1)) {
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for (Index = 0; Index < TableEntryNum; Index++) {
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if (IsTableEntry (TranslationTable[Index], Level, PageWalkCfg)) {
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FreePageTablesRecursive (
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(UINTN *)(GetPpnfromPte ((TranslationTable[Index])) <<
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LOONGARCH_MMU_PAGE_SHIFT),
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PageWalkCfg,
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Level + 1
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);
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}
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}
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}
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FreePages (TranslationTable, 1);
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}
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/**
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Update region mapping recursively.
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@param RegionStart The start address of the region.
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@param RegionEnd The end address of the region.
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@param AttributeSetMask The attribute mask to be set.
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@param AttributeClearMask The attribute mask to be clear.
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@param PageTable The pointer of current page table.
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@param Level The current level.
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@param PageWalkCfg Page table configure value.
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@param TableIsLive TRUE if this is live update, FALSE otherwise.
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@retval EFI_OUT_OF_RESOURCES Not enough resource.
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@retval EFI_SUCCESS The operation succesfully.
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**/
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STATIC
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EFI_STATUS
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UpdateRegionMappingRecursive (
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IN UINTN RegionStart,
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IN UINTN RegionEnd,
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IN UINTN AttributeSetMask,
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IN UINTN AttributeClearMask,
|
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IN UINTN *PageTable,
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IN UINTN Level,
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IN UINT64 PageWalkCfg,
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IN BOOLEAN TableIsLive
|
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)
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{
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EFI_STATUS Status;
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UINTN BlockShift;
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UINTN BlockMask;
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UINTN BlockEnd;
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UINTN *Entry;
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UINTN EntryValue;
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UINTN *TranslationTable;
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UINTN TableEntryNum;
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UINTN TableBitWidth;
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BOOLEAN NextTableIsLive;
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ASSERT (Level < ParseMaxPageTableLevel (PageWalkCfg));
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ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) == 0);
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TableBitWidth = ParsePageTableBitWidth (PageWalkCfg);
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BlockShift = (ParseMaxPageTableLevel (PageWalkCfg) - Level - 1) * TableBitWidth + LOONGARCH_MMU_PAGE_SHIFT;
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BlockMask = MAX_ADDRESS >> (64 - BlockShift);
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DEBUG (
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(
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DEBUG_VERBOSE,
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"%a(%d): %llx - %llx set %lx clr %lx\n",
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__func__,
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Level,
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RegionStart,
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RegionEnd,
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AttributeSetMask,
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AttributeClearMask
|
||||
)
|
||||
);
|
||||
|
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TableEntryNum = (1 << TableBitWidth);
|
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for ( ; RegionStart < RegionEnd; RegionStart = BlockEnd) {
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BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1);
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Entry = &PageTable[(RegionStart >> BlockShift) & (TableEntryNum - 1)];
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//
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// If RegionStart or BlockEnd is not aligned to the block size at this
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// level, we will have to create a table mapping in order to map less
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// than a block, and recurse to create the block or page entries at
|
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// the next level. No block mappings are allowed at all at level 2,
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// so in that case, we have to recurse unconditionally.
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//
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if ((Level < 2) ||
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(((RegionStart | BlockEnd) & BlockMask) != 0) || IsTableEntry (*Entry, Level, PageWalkCfg))
|
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{
|
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ASSERT (Level < (ParseMaxPageTableLevel (PageWalkCfg) - 1));
|
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if (!IsTableEntry (*Entry, Level, PageWalkCfg)) {
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//
|
||||
// No table entry exists yet, so we need to allocate a page table
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// for the next level.
|
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//
|
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TranslationTable = AllocatePages (1);
|
||||
if (TranslationTable == NULL) {
|
||||
return EFI_OUT_OF_RESOURCES;
|
||||
}
|
||||
|
||||
ZeroMem (TranslationTable, EFI_PAGE_SIZE);
|
||||
|
||||
if (IsBlockEntry (*Entry, Level, PageWalkCfg)) {
|
||||
//
|
||||
// We are splitting an existing block entry, so we have to populate
|
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// the new table with the attributes of the block entry it replaces.
|
||||
//
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Status = UpdateRegionMappingRecursive (
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RegionStart & ~BlockMask,
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(RegionStart | BlockMask) + 1,
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*Entry & PTE_ATTRIBUTES_MASK,
|
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PTE_ATTRIBUTES_MASK,
|
||||
TranslationTable,
|
||||
Level + 1,
|
||||
PageWalkCfg,
|
||||
FALSE
|
||||
);
|
||||
if (EFI_ERROR (Status)) {
|
||||
//
|
||||
// The range we passed to UpdateRegionMappingRecursive () is block
|
||||
// aligned, so it is guaranteed that no further pages were allocated
|
||||
// by it, and so we only have to free the page we allocated here.
|
||||
//
|
||||
FreePages (TranslationTable, 1);
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||||
return Status;
|
||||
}
|
||||
}
|
||||
|
||||
NextTableIsLive = FALSE;
|
||||
} else {
|
||||
TranslationTable = (UINTN *)(GetPpnfromPte (*Entry) << LOONGARCH_MMU_PAGE_SHIFT);
|
||||
NextTableIsLive = TableIsLive;
|
||||
}
|
||||
|
||||
//
|
||||
// Recurse to the next level
|
||||
//
|
||||
Status = UpdateRegionMappingRecursive (
|
||||
RegionStart,
|
||||
BlockEnd,
|
||||
AttributeSetMask,
|
||||
AttributeClearMask,
|
||||
TranslationTable,
|
||||
Level + 1,
|
||||
PageWalkCfg,
|
||||
NextTableIsLive
|
||||
);
|
||||
if (EFI_ERROR (Status)) {
|
||||
if (!IsTableEntry (*Entry, Level, PageWalkCfg)) {
|
||||
//
|
||||
// We are creating a new table entry, so on failure, we can free all
|
||||
// allocations we made recursively, given that the whole subhierarchy
|
||||
// has not been wired into the live page tables yet. (This is not
|
||||
// possible for existing table entries, since we cannot revert the
|
||||
// modifications we made to the subhierarchy it represents.)
|
||||
//
|
||||
FreePageTablesRecursive (TranslationTable, PageWalkCfg, Level + 1);
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
if (!IsTableEntry (*Entry, Level, PageWalkCfg)) {
|
||||
EntryValue = SetPpnToPte (0, (UINTN)TranslationTable);
|
||||
ReplaceTableEntry (
|
||||
Entry,
|
||||
EntryValue,
|
||||
RegionStart,
|
||||
TableIsLive
|
||||
);
|
||||
}
|
||||
} else {
|
||||
EntryValue = (*Entry & ~AttributeClearMask) | AttributeSetMask;
|
||||
|
||||
EntryValue = SetPpnToPte (EntryValue, RegionStart);
|
||||
EntryValue = SetValidPte (EntryValue);
|
||||
|
||||
if (Level < (ParseMaxPageTableLevel (PageWalkCfg) - 1)) {
|
||||
EntryValue |= (PAGE_HGLOBAL | PAGE_HUGE | PAGE_VALID);
|
||||
} else {
|
||||
EntryValue |= PAGE_GLOBAL | PAGE_VALID;
|
||||
}
|
||||
|
||||
ReplaceTableEntry (Entry, EntryValue, RegionStart, TableIsLive);
|
||||
}
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Update region mapping at root table.
|
||||
|
||||
@param RegionStart The start address of the region.
|
||||
@param RegionLength The length of the region.
|
||||
@param PageWalkCfg Page table configure value.
|
||||
@param AttributeSetMask The attribute mask to be set.
|
||||
@param AttributeClearMask The attribute mask to be clear.
|
||||
@param RootTable The pointer of root table.
|
||||
@param TableIsLive TRUE if this is live update, FALSE otherwise.
|
||||
|
||||
@retval EFI_INVALID_PARAMETER The RegionStart or RegionLength was not valid.
|
||||
@retval EFI_OUT_OF_RESOURCES Not enough resource.
|
||||
@retval EFI_SUCCESS The operation succesfully.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
UpdateRegionMapping (
|
||||
IN UINTN RegionStart,
|
||||
IN UINTN RegionLength,
|
||||
IN UINT64 PageWalkCfg,
|
||||
IN UINTN AttributeSetMask,
|
||||
IN UINTN AttributeClearMask,
|
||||
IN UINTN *RootTable,
|
||||
IN BOOLEAN TableIsLive
|
||||
)
|
||||
{
|
||||
if (((RegionStart | RegionLength) & EFI_PAGE_MASK) != 0) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
return UpdateRegionMappingRecursive (
|
||||
RegionStart,
|
||||
RegionStart + RegionLength,
|
||||
AttributeSetMask,
|
||||
AttributeClearMask,
|
||||
RootTable,
|
||||
0,
|
||||
PageWalkCfg,
|
||||
TableIsLive
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
Convert EFI Attributes to Loongarch Attributes.
|
||||
|
||||
@param[in] EfiAttributes Efi Attributes.
|
||||
|
||||
@retval Corresponding architecture attributes.
|
||||
**/
|
||||
UINT64
|
||||
EFIAPI
|
||||
EfiAttributeConverse (
|
||||
IN UINT64 EfiAttributes
|
||||
)
|
||||
{
|
||||
UINT64 LoongArchAttributes;
|
||||
|
||||
LoongArchAttributes = PAGE_VALID | PAGE_DIRTY | PLV_KERNEL | PAGE_GLOBAL;
|
||||
|
||||
switch (EfiAttributes & EFI_CACHE_ATTRIBUTE_MASK) {
|
||||
case EFI_MEMORY_UC:
|
||||
LoongArchAttributes |= CACHE_SUC;
|
||||
break;
|
||||
case EFI_MEMORY_WC:
|
||||
LoongArchAttributes |= CACHE_WUC;
|
||||
break;
|
||||
case EFI_MEMORY_WT:
|
||||
case EFI_MEMORY_WB:
|
||||
LoongArchAttributes |= CACHE_CC;
|
||||
break;
|
||||
case EFI_MEMORY_WP:
|
||||
LoongArchAttributes &= ~PAGE_DIRTY;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
// Write protection attributes
|
||||
switch (EfiAttributes & EFI_MEMORY_ACCESS_MASK) {
|
||||
case EFI_MEMORY_RP:
|
||||
LoongArchAttributes |= PAGE_NO_READ;
|
||||
break;
|
||||
case EFI_MEMORY_XP:
|
||||
LoongArchAttributes |= PAGE_NO_EXEC;
|
||||
break;
|
||||
case EFI_MEMORY_RO:
|
||||
LoongArchAttributes &= ~PAGE_DIRTY;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return LoongArchAttributes;
|
||||
}
|
||||
|
||||
/**
|
||||
TLB refill handler configure.
|
||||
|
||||
@param VOID.
|
||||
|
||||
@retval EFI_SUCCESS TLB refill handler configure successfully.
|
||||
EFI_UNSUPPORTED Size not aligned.
|
||||
**/
|
||||
EFI_STATUS
|
||||
TlbRefillHandlerConfigure (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN Length;
|
||||
UINTN TlbReEntry;
|
||||
UINTN TlbReEntryOffset;
|
||||
UINTN Remaining;
|
||||
|
||||
//
|
||||
// Set TLB exception handler
|
||||
//
|
||||
///
|
||||
/// TLB Re-entry address at the end of exception vector, a vector is up to 512 bytes,
|
||||
/// so the starting address is: total exception vector size + total interrupt vector size + base.
|
||||
/// The total size of TLB handler and exception vector size and interrupt vector size should not
|
||||
/// be lager than 64KB.
|
||||
///
|
||||
Length = (UINTN)HandleTlbRefillEnd - (UINTN)HandleTlbRefillStart;
|
||||
TlbReEntryOffset = (MAX_LOONGARCH_EXCEPTION + MAX_LOONGARCH_INTERRUPT) * 512;
|
||||
Remaining = TlbReEntryOffset % SIZE_4KB;
|
||||
if (Remaining != 0x0) {
|
||||
TlbReEntryOffset += (SIZE_4KB - Remaining);
|
||||
}
|
||||
|
||||
TlbReEntry = PcdGet64 (PcdLoongArchExceptionVectorBaseAddress) + TlbReEntryOffset;
|
||||
if ((TlbReEntryOffset + Length) > SIZE_64KB) {
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
//
|
||||
// Ensure that TLB refill exception base address alignment is equals to 4KB and is valid.
|
||||
//
|
||||
if (TlbReEntry & (SIZE_4KB - 1)) {
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
CopyMem ((VOID *)TlbReEntry, HandleTlbRefillStart, Length);
|
||||
InvalidateInstructionCacheRange ((VOID *)(UINTN)HandleTlbRefillStart, Length);
|
||||
|
||||
//
|
||||
// Set the address of TLB refill exception handler
|
||||
//
|
||||
SetTlbRebaseAddress ((UINTN)TlbReEntry);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Maps the memory region in the page table to the specified attributes.
|
||||
|
||||
@param[in, out] PageTable The pointer to the page table to update, or pointer to NULL
|
||||
if a new page table is to be created.
|
||||
@param[in] PageWalkCfg The page walk controller configure.
|
||||
@param[in] BaseAddress The base address of the memory region to set the Attributes.
|
||||
@param[in] Length The length of the memory region to set the Attributes.
|
||||
@param[in] Attributes The bitmask of attributes to set, which refer to UEFI SPEC
|
||||
7.2.3(EFI_BOOT_SERVICES.GetMemoryMap()).
|
||||
@param[in] AttributeMask Mask of memory attributes to take into account.
|
||||
|
||||
@retval EFI_SUCCESS The Attributes was set successfully or Length is 0.
|
||||
@retval EFI_INVALID_PARAMETER PageTable is NULL, PageWalkCfg is invalid.
|
||||
@retval EFI_UNSUPPORTED *PageTable is NULL.
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
MemoryRegionMap (
|
||||
IN OUT UINTN *PageTable OPTIONAL,
|
||||
IN UINT64 PageWalkCfg,
|
||||
IN EFI_PHYSICAL_ADDRESS BaseAddress,
|
||||
IN UINT64 Length,
|
||||
IN UINT64 Attributes,
|
||||
IN UINT64 AttributeMask
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT64 LoongArchAttributes;
|
||||
BOOLEAN Initialization;
|
||||
BOOLEAN CreateNew;
|
||||
UINTN PageTableBitWidth;
|
||||
UINTN MaxLevel;
|
||||
UINTN PgdSize;
|
||||
|
||||
if ((PageTable == NULL) || (PageWalkCfg == 0)) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
PageTableBitWidth = ParsePageTableBitWidth (PageWalkCfg);
|
||||
MaxLevel = ParseMaxPageTableLevel (PageWalkCfg);
|
||||
|
||||
if ((!PageTableBitWidth && !MaxLevel) || (PageTableBitWidth > 0x1F) || (MaxLevel > LEVEL5)) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
Initialization = FALSE;
|
||||
CreateNew = FALSE;
|
||||
|
||||
//
|
||||
// *PageTable is NULL, create a new and return.
|
||||
//
|
||||
if (*PageTable == 0) {
|
||||
CreateNew = TRUE;
|
||||
//
|
||||
// If the MMU has not been configured yet, configure it later.
|
||||
//
|
||||
if (!MmuIsInit ()) {
|
||||
Initialization = TRUE;
|
||||
}
|
||||
}
|
||||
|
||||
if (Length == 0) {
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
if (Initialization == TRUE) {
|
||||
Status = TlbRefillHandlerConfigure ();
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
}
|
||||
|
||||
if (CreateNew == TRUE) {
|
||||
//
|
||||
// Create a new page table.
|
||||
//
|
||||
PgdSize = (1 << PageTableBitWidth) * sizeof (UINTN);
|
||||
*PageTable = (UINTN)AllocatePages (EFI_SIZE_TO_PAGES (PgdSize));
|
||||
ZeroMem ((VOID *)*PageTable, PgdSize);
|
||||
|
||||
if ((VOID *)*PageTable == NULL) {
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
LoongArchAttributes = EfiAttributeConverse (Attributes);
|
||||
|
||||
//
|
||||
// Update the page table attributes.
|
||||
//
|
||||
// If the MMU has been configured and *PageTable == CSR_PGDL, the page table in use will update.
|
||||
//
|
||||
// If *PageTable != CSR_PGDL, only the page table structure in memory is update, but some TLB
|
||||
// region may be invalidated during the mapping process. So at this time the caller must ensure
|
||||
// that the execution environment must be safe. It is recommended to use the DA mode!
|
||||
//
|
||||
Status = UpdateRegionMapping (
|
||||
BaseAddress,
|
||||
Length,
|
||||
PageWalkCfg,
|
||||
LoongArchAttributes,
|
||||
PTE_ATTRIBUTES_MASK,
|
||||
(UINTN *)(*PageTable),
|
||||
(MmuIsEnabled () && !CreateNew)
|
||||
);
|
||||
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
return Status;
|
||||
}
|
|
@ -0,0 +1,33 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
**/
|
||||
|
||||
#ifndef PAGE_H_
|
||||
#define PAGE_H_
|
||||
|
||||
#define INVALID_PAGE 0
|
||||
|
||||
#define LEVEL5 5
|
||||
#define LEVEL4 4
|
||||
#define LEVEL3 3
|
||||
#define LEVEL2 2
|
||||
#define LEVEL1 1
|
||||
|
||||
#define PTE_ATTRIBUTES_MASK 0x600000000000007EULL
|
||||
|
||||
#define PTE_PPN_MASK 0xFFFFFFFFF000ULL
|
||||
#define PTE_PPN_SHIFT EFI_PAGE_SHIFT
|
||||
#define LOONGARCH_MMU_PAGE_SHIFT EFI_PAGE_SHIFT
|
||||
|
||||
//
|
||||
// For coding convenience, define the maximum valid
|
||||
// LoongArch exception.
|
||||
// Since UEFI V2.11, it will be present in DebugSupport.h.
|
||||
//
|
||||
#define MAX_LOONGARCH_EXCEPTION 64
|
||||
|
||||
#endif // PAGE_H_
|
|
@ -0,0 +1,51 @@
|
|||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# TLB refill exception handler
|
||||
#
|
||||
# Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
#include <Register/LoongArch64/Csr.h>
|
||||
|
||||
ASM_GLOBAL ASM_PFX(HandleTlbRefillStart)
|
||||
ASM_GLOBAL ASM_PFX(HandleTlbRefillEnd)
|
||||
|
||||
#
|
||||
# Refill the page table.
|
||||
# @param VOID
|
||||
# @retval VOID
|
||||
#
|
||||
ASM_PFX(HandleTlbRefillStart):
|
||||
csrwr $t0, LOONGARCH_CSR_TLBRSAVE
|
||||
csrrd $t0, LOONGARCH_CSR_PWCTL1
|
||||
srli.d $t0, $t0, 18
|
||||
andi $t0, $t0, 0x3F
|
||||
bnez $t0, Level5
|
||||
csrrd $t0, LOONGARCH_CSR_PWCTL1
|
||||
srli.d $t0, $t0, 6
|
||||
andi $t0, $t0, 0x3F
|
||||
bnez $t0, Level4
|
||||
csrrd $t0, LOONGARCH_CSR_PGD
|
||||
b Level3
|
||||
Level5:
|
||||
csrrd $t0, LOONGARCH_CSR_PGD
|
||||
lddir $t0, $t0, 4 #Put pud BaseAddress into T0
|
||||
lddir $t0, $t0, 3 #Put pud BaseAddress into T0
|
||||
b Level3
|
||||
Level4:
|
||||
csrrd $t0, LOONGARCH_CSR_PGD
|
||||
lddir $t0, $t0, 3 #Put pud BaseAddress into T0
|
||||
Level3:
|
||||
lddir $t0, $t0, 2 #Put pmd BaseAddress into T0
|
||||
lddir $t0, $t0, 1 #Put pte BaseAddress into T0
|
||||
ldpte $t0, 0
|
||||
ldpte $t0, 1
|
||||
tlbfill // refill hi, lo0, lo1
|
||||
csrrd $t0, LOONGARCH_CSR_TLBRSAVE
|
||||
ertn
|
||||
ASM_PFX(HandleTlbRefillEnd):
|
||||
|
||||
.end
|
|
@ -0,0 +1,36 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
**/
|
||||
|
||||
#ifndef TLB_EXCEPTION_HANDLE_H_
|
||||
#define TLB_EXCEPTION_HANDLE_H_
|
||||
|
||||
/**
|
||||
TLB refill handler start.
|
||||
|
||||
@param none
|
||||
|
||||
@retval none
|
||||
**/
|
||||
VOID
|
||||
HandleTlbRefillStart (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
TLB refill handler end.
|
||||
|
||||
@param none
|
||||
|
||||
@retval none
|
||||
**/
|
||||
VOID
|
||||
HandleTlbRefillEnd (
|
||||
VOID
|
||||
);
|
||||
|
||||
#endif // TLB_EXCEPTION_HANDLE_H_
|
|
@ -0,0 +1,24 @@
|
|||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Invalid TLB operation function
|
||||
#
|
||||
# Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
#include <Register/LoongArch64/Csr.h>
|
||||
|
||||
ASM_GLOBAL ASM_PFX(InvalidTlb)
|
||||
|
||||
#
|
||||
# Invalid corresponding TLB entries are based on the address given
|
||||
# @param a0 The address corresponding to the invalid page table entry
|
||||
# @retval none
|
||||
#
|
||||
ASM_PFX(InvalidTlb):
|
||||
invtlb INVTLB_ADDR_GTRUE_OR_ASID, $zero, $a0
|
||||
jirl $zero, $ra, 0
|
||||
|
||||
.end
|
|
@ -0,0 +1,24 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
**/
|
||||
|
||||
#ifndef INVALID_TLB_H_
|
||||
#define INVALID_TLB_H_
|
||||
|
||||
/**
|
||||
Invalid corresponding TLB entries are based on the address given
|
||||
|
||||
@param Address The address corresponding to the invalid page table entry
|
||||
|
||||
@retval none
|
||||
**/
|
||||
VOID
|
||||
InvalidTlb (
|
||||
UINTN Address
|
||||
);
|
||||
|
||||
#endif // INVALID_TLB_H_
|
|
@ -211,5 +211,8 @@
|
|||
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
|
||||
UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
|
||||
|
||||
[Components.LOONGARCH64]
|
||||
UefiCpuPkg/Library/CpuMmuLib/CpuMmuLib.inf
|
||||
|
||||
[BuildOptions]
|
||||
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
|
||||
|
|
Loading…
Reference in New Issue