mirror of https://github.com/acidanthera/audk.git
IntelFsp2Pkg: Update Section Name in INF files
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
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## @file
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# Component information file for the FSP notify phase PEI module.
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#
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#@copyright
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# Copyright (c) 2016 Intel Corporation. All rights reserved.
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# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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## @file
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# NULL instance of Base cache as RAM.
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#
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# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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#
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##
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[defines]
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = BaseCacheAsRamLibNull
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FILE_GUID = 630AEB10-2106-4234-9DB3-836A3663F50D
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VERSION_STRING = 1.0
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LIBRARY_CLASS = CacheAsRamLib
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[sources.common]
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[Sources.common]
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DisableCacheAsRamNull.c
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[Packages]
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## @file
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# Instance of BaseCache.
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#
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# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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#
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##
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[defines]
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = BaseCacheLib
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FILE_GUID = 8EF3A653-DA8B-4FFA-BB85-FF47406DB9F0
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VERSION_STRING = 1.0
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LIBRARY_CLASS = CacheLib
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[sources.IA32]
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[Sources.IA32]
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CacheLib.c
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CacheLibInternal.h
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