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UefiCpuPkg: Remove AMD 32-bit SMRAM save state map

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Per AMD64 Architecture Programmer's Manual Volume 2: System
Programming - 10.2.3 SMRAM State-Save Area (Rev 24593), the AMD64
architecture does not use the legacy SMM state-save area format
(Table 10-2) for 32-bit SMRAM save state map. Clean up codes for the
invalid save state map.

Signed-off-by: Phil Noh <Phil.Noh@amd.com>
This commit is contained in:
Phil Noh 2024-10-31 14:51:20 -05:00 committed by mergify[bot]
parent b7735a087a
commit 03d8907321
3 changed files with 101 additions and 157 deletions
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92
UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveState.c
View File

@ -2,7 +2,7 @@
Provides services to access SMRAM Save State Map Provides services to access SMRAM Save State Map
Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR> Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
@ -20,36 +20,43 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Macro used to simplify the lookup table entries of type CPU_MM_SAVE_STATE_LOOKUP_ENTRY // Macro used to simplify the lookup table entries of type CPU_MM_SAVE_STATE_LOOKUP_ENTRY
#define MM_CPU_OFFSET(Field) OFFSET_OF (AMD_SMRAM_SAVE_STATE_MAP, Field) #define MM_CPU_OFFSET(Field) OFFSET_OF (AMD_SMRAM_SAVE_STATE_MAP, Field)
//
// Lookup table used to retrieve the widths and offsets associated with each // Lookup table used to retrieve the widths and offsets associated with each
// supported EFI_MM_SAVE_STATE_REGISTER value // supported EFI_MM_SAVE_STATE_REGISTER value
//
// Per AMD64 Architecture Programmer's Manual Volume 2: System
// Programming - 10.2.3 SMRAM State-Save Area (Rev 24593), the AMD64
// architecture does not use the legacy SMM state-save area format
// (Table 10-2) for 32-bit SMRAM Save State Map.
//
CONST CPU_MM_SAVE_STATE_LOOKUP_ENTRY mCpuWidthOffset[] = { CONST CPU_MM_SAVE_STATE_LOOKUP_ENTRY mCpuWidthOffset[] = {
{ 0, 0, 0, 0, FALSE }, // Reserved { 0, 0, 0, 0, 0, FALSE }, // Reserved
// //
// Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol. // Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol.
// //
{ 4, 4, MM_CPU_OFFSET (x86.SMMRevId), MM_CPU_OFFSET (x64.SMMRevId), 0, FALSE}, // AMD_MM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1 { 0, 4, 0, MM_CPU_OFFSET (x64.SMMRevId), 0, FALSE }, // AMD_MM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1
// //
// CPU Save State registers defined in PI SMM CPU Protocol. // CPU Save State registers defined in PI SMM CPU Protocol.
// //
{ 4, 8, MM_CPU_OFFSET (x86.GDTBase), MM_CPU_OFFSET (x64._GDTRBaseLoDword), MM_CPU_OFFSET (x64._GDTRBaseHiDword), FALSE}, // EFI_MM_SAVE_STATE_REGISTER_GDTBASE = 4 { 0, 8, 0, MM_CPU_OFFSET (x64._GDTRBaseLoDword), MM_CPU_OFFSET (x64._GDTRBaseHiDword), FALSE }, // EFI_MM_SAVE_STATE_REGISTER_GDTBASE = 4
{ 0, 8, 0, MM_CPU_OFFSET (x64._IDTRBaseLoDword), MM_CPU_OFFSET (x64._IDTRBaseLoDword), FALSE }, // EFI_MM_SAVE_STATE_REGISTER_IDTBASE = 5 { 0, 8, 0, MM_CPU_OFFSET (x64._IDTRBaseLoDword), MM_CPU_OFFSET (x64._IDTRBaseLoDword), FALSE }, // EFI_MM_SAVE_STATE_REGISTER_IDTBASE = 5
{ 0, 8, 0, MM_CPU_OFFSET (x64._LDTRBaseLoDword), MM_CPU_OFFSET (x64._LDTRBaseLoDword), FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTBASE = 6 { 0, 8, 0, MM_CPU_OFFSET (x64._LDTRBaseLoDword), MM_CPU_OFFSET (x64._LDTRBaseLoDword), FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTBASE = 6
{ 0, 2, 0, MM_CPU_OFFSET (x64._GDTRLimit), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT = 7 { 0, 2, 0, MM_CPU_OFFSET (x64._GDTRLimit), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT = 7
{ 0, 2, 0, MM_CPU_OFFSET (x64._IDTRLimit), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT = 8 { 0, 2, 0, MM_CPU_OFFSET (x64._IDTRLimit), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT = 8
{ 0, 4, 0, MM_CPU_OFFSET (x64._LDTRLimit), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT = 9 { 0, 4, 0, MM_CPU_OFFSET (x64._LDTRLimit), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT = 9
{ 0, 0, 0, 0, 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTINFO = 10 { 0, 0, 0, 0, 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTINFO = 10
{ 4, 2, MM_CPU_OFFSET (x86._ES), MM_CPU_OFFSET (x64._ES), 0, FALSE}, // EFI_MM_SAVE_STATE_REGISTER_ES = 20 { 0, 2, 0, MM_CPU_OFFSET (x64._ES), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_ES = 20
{ 4, 2, MM_CPU_OFFSET (x86._CS), MM_CPU_OFFSET (x64._CS), 0, FALSE}, // EFI_MM_SAVE_STATE_REGISTER_CS = 21 { 0, 2, 0, MM_CPU_OFFSET (x64._CS), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_CS = 21
{ 4, 2, MM_CPU_OFFSET (x86._SS), MM_CPU_OFFSET (x64._SS), 0, FALSE}, // EFI_MM_SAVE_STATE_REGISTER_SS = 22 { 0, 2, 0, MM_CPU_OFFSET (x64._SS), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_SS = 22
{ 4, 2, MM_CPU_OFFSET (x86._DS), MM_CPU_OFFSET (x64._DS), 0, FALSE}, // EFI_MM_SAVE_STATE_REGISTER_DS = 23 { 0, 2, 0, MM_CPU_OFFSET (x64._DS), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_DS = 23
{ 4, 2, MM_CPU_OFFSET (x86._FS), MM_CPU_OFFSET (x64._FS), 0, FALSE}, // EFI_MM_SAVE_STATE_REGISTER_FS = 24 { 0, 2, 0, MM_CPU_OFFSET (x64._FS), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_FS = 24
{ 4, 2, MM_CPU_OFFSET (x86._GS), MM_CPU_OFFSET (x64._GS), 0, FALSE}, // EFI_MM_SAVE_STATE_REGISTER_GS = 25 { 0, 2, 0, MM_CPU_OFFSET (x64._GS), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_GS = 25
{ 0, 2, 0, MM_CPU_OFFSET (x64._LDTR), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL = 26 { 0, 2, 0, MM_CPU_OFFSET (x64._LDTR), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL = 26
{ 0, 2, 0, MM_CPU_OFFSET (x64._TR), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_TR_SEL = 27 { 0, 2, 0, MM_CPU_OFFSET (x64._TR), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_TR_SEL = 27
{ 4, 8, MM_CPU_OFFSET (x86._DR7), MM_CPU_OFFSET (x64._DR7), MM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_MM_SAVE_STATE_REGISTER_DR7 = 28 { 0, 8, 0, MM_CPU_OFFSET (x64._DR7), MM_CPU_OFFSET (x64._DR7) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_DR7 = 28
{ 4, 8, MM_CPU_OFFSET (x86._DR6), MM_CPU_OFFSET (x64._DR6), MM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_MM_SAVE_STATE_REGISTER_DR6 = 29 { 0, 8, 0, MM_CPU_OFFSET (x64._DR6), MM_CPU_OFFSET (x64._DR6) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_DR6 = 29
{ 0, 8, 0, MM_CPU_OFFSET (x64._R8), MM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R8 = 30 { 0, 8, 0, MM_CPU_OFFSET (x64._R8), MM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R8 = 30
{ 0, 8, 0, MM_CPU_OFFSET (x64._R9), MM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R9 = 31 { 0, 8, 0, MM_CPU_OFFSET (x64._R9), MM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R9 = 31
{ 0, 8, 0, MM_CPU_OFFSET (x64._R10), MM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R10 = 32 { 0, 8, 0, MM_CPU_OFFSET (x64._R10), MM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R10 = 32
@ -58,21 +65,21 @@ CONST CPU_MM_SAVE_STATE_LOOKUP_ENTRY mCpuWidthOffset[] = {
{ 0, 8, 0, MM_CPU_OFFSET (x64._R13), MM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R13 = 35 { 0, 8, 0, MM_CPU_OFFSET (x64._R13), MM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R13 = 35
{ 0, 8, 0, MM_CPU_OFFSET (x64._R14), MM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R14 = 36 { 0, 8, 0, MM_CPU_OFFSET (x64._R14), MM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R14 = 36
{ 0, 8, 0, MM_CPU_OFFSET (x64._R15), MM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R15 = 37 { 0, 8, 0, MM_CPU_OFFSET (x64._R15), MM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R15 = 37
{ 4, 8, MM_CPU_OFFSET (x86._EAX), MM_CPU_OFFSET (x64._RAX), MM_CPU_OFFSET (x64._RAX) + 4, TRUE}, // EFI_MM_SAVE_STATE_REGISTER_RAX = 38 { 0, 8, 0, MM_CPU_OFFSET (x64._RAX), MM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RAX = 38
{ 4, 8, MM_CPU_OFFSET (x86._EBX), MM_CPU_OFFSET (x64._RBX), MM_CPU_OFFSET (x64._RBX) + 4, TRUE}, // EFI_MM_SAVE_STATE_REGISTER_RBX = 39 { 0, 8, 0, MM_CPU_OFFSET (x64._RBX), MM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RBX = 39
{ 4, 8, MM_CPU_OFFSET (x86._ECX), MM_CPU_OFFSET (x64._RCX), MM_CPU_OFFSET (x64._RCX) + 4, TRUE}, // EFI_MM_SAVE_STATE_REGISTER_RBX = 39 { 0, 8, 0, MM_CPU_OFFSET (x64._RCX), MM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RBX = 39
{ 4, 8, MM_CPU_OFFSET (x86._EDX), MM_CPU_OFFSET (x64._RDX), MM_CPU_OFFSET (x64._RDX) + 4, TRUE}, // EFI_MM_SAVE_STATE_REGISTER_RDX = 41 { 0, 8, 0, MM_CPU_OFFSET (x64._RDX), MM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RDX = 41
{ 4, 8, MM_CPU_OFFSET (x86._ESP), MM_CPU_OFFSET (x64._RSP), MM_CPU_OFFSET (x64._RSP) + 4, TRUE}, // EFI_MM_SAVE_STATE_REGISTER_RSP = 42 { 0, 8, 0, MM_CPU_OFFSET (x64._RSP), MM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RSP = 42
{ 4, 8, MM_CPU_OFFSET (x86._EBP), MM_CPU_OFFSET (x64._RBP), MM_CPU_OFFSET (x64._RBP) + 4, TRUE}, // EFI_MM_SAVE_STATE_REGISTER_RBP = 43 { 0, 8, 0, MM_CPU_OFFSET (x64._RBP), MM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RBP = 43
{ 4, 8, MM_CPU_OFFSET (x86._ESI), MM_CPU_OFFSET (x64._RSI), MM_CPU_OFFSET (x64._RSI) + 4, TRUE}, // EFI_MM_SAVE_STATE_REGISTER_RSI = 44 { 0, 8, 0, MM_CPU_OFFSET (x64._RSI), MM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RSI = 44
{ 4, 8, MM_CPU_OFFSET (x86._EDI), MM_CPU_OFFSET (x64._RDI), MM_CPU_OFFSET (x64._RDI) + 4, TRUE}, // EFI_MM_SAVE_STATE_REGISTER_RDI = 45 { 0, 8, 0, MM_CPU_OFFSET (x64._RDI), MM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RDI = 45
{ 4, 8, MM_CPU_OFFSET (x86._EIP), MM_CPU_OFFSET (x64._RIP), MM_CPU_OFFSET (x64._RIP) + 4, TRUE}, // EFI_MM_SAVE_STATE_REGISTER_RIP = 46 { 0, 8, 0, MM_CPU_OFFSET (x64._RIP), MM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RIP = 46
{ 4, 8, MM_CPU_OFFSET (x86._EFLAGS), MM_CPU_OFFSET (x64._RFLAGS), MM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE}, // EFI_MM_SAVE_STATE_REGISTER_RFLAGS = 51 { 0, 8, 0, MM_CPU_OFFSET (x64._RFLAGS), MM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RFLAGS = 51
{ 4, 8, MM_CPU_OFFSET (x86._CR0), MM_CPU_OFFSET (x64._CR0), MM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_MM_SAVE_STATE_REGISTER_CR0 = 52 { 0, 8, 0, MM_CPU_OFFSET (x64._CR0), MM_CPU_OFFSET (x64._CR0) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_CR0 = 52
{ 4, 8, MM_CPU_OFFSET (x86._CR3), MM_CPU_OFFSET (x64._CR3), MM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_MM_SAVE_STATE_REGISTER_CR3 = 53 { 0, 8, 0, MM_CPU_OFFSET (x64._CR3), MM_CPU_OFFSET (x64._CR3) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_CR3 = 53
{ 0, 8, 0, MM_CPU_OFFSET (x64._CR4), MM_CPU_OFFSET (x64._CR4) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_CR4 = 54 { 0, 8, 0, MM_CPU_OFFSET (x64._CR4), MM_CPU_OFFSET (x64._CR4) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_CR4 = 54
{ 0, 0, 0, 0, 0 } { 0, 0, 0, 0, 0, FALSE }
}; };
/** /**
@ -235,30 +242,6 @@ MmSaveStateWriteRegister (
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
//
// Check CPU mode
//
if (MmSaveStateGetRegisterLma () == EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT) {
//
// If 32-bit mode width is zero, then the specified register can not be accessed
//
if (mCpuWidthOffset[RegisterIndex].Width32 == 0) {
return EFI_NOT_FOUND;
}
//
// If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
//
if (Width > mCpuWidthOffset[RegisterIndex].Width32) {
return EFI_INVALID_PARAMETER;
}
//
// Write SMM State register
//
ASSERT (CpuSaveState != NULL);
CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
} else {
// //
// If 64-bit mode width is zero, then the specified register can not be accessed // If 64-bit mode width is zero, then the specified register can not be accessed
// //
@ -283,7 +266,6 @@ MmSaveStateWriteRegister (
// //
CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4); CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
} }
}
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -298,12 +280,8 @@ MmSaveStateGetRegisterLma (
VOID VOID
) )
{ {
UINT32 LMAValue; //
// AMD64 processors support EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT only
LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; //
if (LMAValue) {
return EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT; return EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT;
} }
return EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT;
}

35
UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c
View File

@ -47,13 +47,10 @@ CpuFeaturesLibInitialization (
VOID VOID
) )
{ {
UINT32 LMAValue; //
// AMD64 processors support EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT only
LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; //
mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
if (LMAValue) {
mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
}
// //
// If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded // If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded
@ -96,7 +93,6 @@ SmmCpuFeaturesInitializeProcessor (
) )
{ {
AMD_SMRAM_SAVE_STATE_MAP *CpuState; AMD_SMRAM_SAVE_STATE_MAP *CpuState;
UINT32 LMAValue;
// //
// No need to configure SMBASE if SmBase relocation has been done. // No need to configure SMBASE if SmBase relocation has been done.
@ -109,14 +105,6 @@ SmmCpuFeaturesInitializeProcessor (
CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex]; CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
} }
// Re-initialize the value of mSmmSaveStateRegisterLma flag which might have been changed in PiCpuSmmDxeSmm Driver
// Entry point, to make sure correct value on AMD platform is assigned to be used by SmmCpuFeaturesLib.
LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
if (LMAValue) {
mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
}
// //
// If SMRR is supported, then program SMRR base/mask MSRs. // If SMRR is supported, then program SMRR base/mask MSRs.
// The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI. // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.
@ -193,22 +181,12 @@ SmmCpuFeaturesHookReturnFromSmm (
AmdCpuState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; AmdCpuState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState;
if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
OriginalInstructionPointer = (UINT64)AmdCpuState->x86._EIP;
AmdCpuState->x86._EIP = (UINT32)NewInstructionPointer;
//
// Clear the auto HALT restart flag so the RSM instruction returns
// program control to the instruction following the HLT instruction.
//
if ((AmdCpuState->x86.AutoHALTRestart & BIT0) != 0) {
AmdCpuState->x86.AutoHALTRestart &= ~BIT0;
}
} else {
OriginalInstructionPointer = AmdCpuState->x64._RIP; OriginalInstructionPointer = AmdCpuState->x64._RIP;
if ((AmdCpuState->x64.EFER & LMA) == 0) { if ((AmdCpuState->x64.EFER & LMA) == 0) {
AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer32; AmdCpuState->x64._RIP = NewInstructionPointer32;
} else { } else {
AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer; AmdCpuState->x64._RIP = NewInstructionPointer;
} }
// //
@ -218,7 +196,6 @@ SmmCpuFeaturesHookReturnFromSmm (
if ((AmdCpuState->x64.AutoHALTRestart & BIT0) != 0) { if ((AmdCpuState->x64.AutoHALTRestart & BIT0) != 0) {
AmdCpuState->x64.AutoHALTRestart &= ~BIT0; AmdCpuState->x64.AutoHALTRestart &= ~BIT0;
} }
}
return OriginalInstructionPointer; return OriginalInstructionPointer;
} }

19
UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.c
View File

@ -1,7 +1,7 @@
/** @file /** @file
Config SMRAM Save State for SmmBases Relocation. Config SMRAM Save State for SmmBases Relocation.
Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR> Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@ -94,22 +94,12 @@ HookReturnFromSmm (
AmdCpuState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; AmdCpuState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState;
if (GetMmSaveStateRegisterLma () == EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT) {
OriginalInstructionPointer = (UINT64)AmdCpuState->x86._EIP;
AmdCpuState->x86._EIP = (UINT32)NewInstructionPointer;
//
// Clear the auto HALT restart flag so the RSM instruction returns
// program control to the instruction following the HLT instruction.
//
if ((AmdCpuState->x86.AutoHALTRestart & BIT0) != 0) {
AmdCpuState->x86.AutoHALTRestart &= ~BIT0;
}
} else {
OriginalInstructionPointer = AmdCpuState->x64._RIP; OriginalInstructionPointer = AmdCpuState->x64._RIP;
if ((AmdCpuState->x64.EFER & LMA) == 0) { if ((AmdCpuState->x64.EFER & LMA) == 0) {
AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer32; AmdCpuState->x64._RIP = NewInstructionPointer32;
} else { } else {
AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer; AmdCpuState->x64._RIP = NewInstructionPointer;
} }
// //
@ -119,7 +109,6 @@ HookReturnFromSmm (
if ((AmdCpuState->x64.AutoHALTRestart & BIT0) != 0) { if ((AmdCpuState->x64.AutoHALTRestart & BIT0) != 0) {
AmdCpuState->x64.AutoHALTRestart &= ~BIT0; AmdCpuState->x64.AutoHALTRestart &= ~BIT0;
} }
}
return OriginalInstructionPointer; return OriginalInstructionPointer;
} }