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ArmPkg/CpuDxe: Fixed AArch64 MMU/GCD synchronization 

- Fix the length used to set the GCD Memory Space attribute
- Print a warning message if the given length of a memory space region is not 4KB-aligned

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14562 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin 2013-08-19 17:33:31 +00:00 committed by oliviermartin
parent 6a343fac2c
commit 047c0cbb1e
2 changed files with 17 additions and 8 deletions
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18
ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c
View File

@ -89,7 +89,7 @@ GetNextEntryAttribute (
// Update GCD with the last region // Update GCD with the last region
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,
*StartGcdRegion, *StartGcdRegion,
(BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel)) - 1) - *StartGcdRegion, (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion,
PageAttributeToGcdAttribute (EntryAttribute)); PageAttributeToGcdAttribute (EntryAttribute));
} }
@ -113,8 +113,8 @@ GetNextEntryAttribute (
// Update GCD with the last region // Update GCD with the last region
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,
*StartGcdRegion, *StartGcdRegion,
(BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel)) - 1) - *StartGcdRegion, (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion,
PageAttributeToGcdAttribute (EntryAttribute)); PageAttributeToGcdAttribute (*PrevEntryAttribute));
// Start of the new region // Start of the new region
*StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel)); *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel));
@ -182,11 +182,13 @@ SyncCacheConfig (
BaseAddressGcdRegion, BaseAddressGcdRegion,
&PageAttribute, &BaseAddressGcdRegion); &PageAttribute, &BaseAddressGcdRegion);
// Update GCD with the last region // Update GCD with the last region if valid
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, if (PageAttribute != TT_ATTR_INDX_INVALID) {
BaseAddressGcdRegion, SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,
EndAddressGcdRegion - BaseAddressGcdRegion, BaseAddressGcdRegion,
PageAttributeToGcdAttribute (PageAttribute)); EndAddressGcdRegion - BaseAddressGcdRegion,
PageAttributeToGcdAttribute (PageAttribute));
}
FreePool (MemorySpaceMap); FreePool (MemorySpaceMap);

7
ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
View File

@ -96,6 +96,13 @@ SetGcdMemorySpaceAttributes (
DEBUG ((DEBUG_GCD, "SetGcdMemorySpaceAttributes[0x%lX; 0x%lX] = 0x%lX\n", DEBUG ((DEBUG_GCD, "SetGcdMemorySpaceAttributes[0x%lX; 0x%lX] = 0x%lX\n",
BaseAddress, BaseAddress + Length, Attributes)); BaseAddress, BaseAddress + Length, Attributes));
// We do not support a smaller granularity than 4KB on ARM Architecture
if ((Length & EFI_PAGE_MASK) != 0) {
DEBUG ((DEBUG_WARN,
"Warning: We do not support smaller granularity than 4KB on ARM Architecture (passed length: 0x%lX).\n",
Length));
}
// //
// Get all memory descriptors covered by the memory range // Get all memory descriptors covered by the memory range
// //