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MdeModulePkg/AhciPei: Limit max transfer blocknum for 48-bit address
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1483 Due to the limited resource on the VTd DMA buffer size in the PEI phase, the driver will limit the maximum transfer block number for 48-bit addressing. According to PCDs: gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSize|0x00400000 gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSizeS3|0x00200000 The default buffer size allocated for IOMMU mapping is: * 4M bytes for non-S3 cases; * 2M bytes for S3 For ATA devices in 48-bit address mode, the maximum block number is currently set to 0xFFFF. For a device with block size equal to 512 bytes, the maximum buffer allowed for mapping within AhciPei driver will be close to 32M bytes. Thus, this commit will limit the 48-bit mode maximum block number to 0x800, which means 1M-byte maximum buffer for mapping when the block size of a device is 512 bytes. By doing so, potential failure on calls to the IOMMU 'Map' service can be avoided. Cc: Eric Dong <eric.dong@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
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@ -48,7 +48,13 @@ UINT8 mAtaTrustCommands[2] = {
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// Look up table (Lba48Bit) for maximum transfer block number
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// Look up table (Lba48Bit) for maximum transfer block number
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//
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//
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#define MAX_28BIT_TRANSFER_BLOCK_NUM 0x100
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#define MAX_28BIT_TRANSFER_BLOCK_NUM 0x100
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#define MAX_48BIT_TRANSFER_BLOCK_NUM 0xFFFF
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//
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// Due to limited resource for VTd PEI DMA buffer on platforms, the driver
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// limits the maximum transfer block number for 48-bit addressing.
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// Here, setting to 0x800 means that for device with 512-byte block size, the
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// maximum buffer for DMA mapping will be 1M bytes in size.
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//
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#define MAX_48BIT_TRANSFER_BLOCK_NUM 0x800
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UINT32 mMaxTransferBlockNumber[2] = {
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UINT32 mMaxTransferBlockNumber[2] = {
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MAX_28BIT_TRANSFER_BLOCK_NUM,
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MAX_28BIT_TRANSFER_BLOCK_NUM,
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