mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/SkylakeMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
This commit is contained in:
Jeff Fan
parent
94fe1b5f53
commit
04e7a46528
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@ -42,6 +42,7 @@
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Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);
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@endcode
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@note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
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**/
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#define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD
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@ -101,6 +102,7 @@ typedef union {
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Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);
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AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);
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@endcode
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@note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
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**/
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#define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9
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@ -119,6 +121,7 @@ typedef union {
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Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0);
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@endcode
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@note MSR_SKYLAKE_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM.
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**/
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#define MSR_SKYLAKE_SGXOWNER0 0x00000300
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@ -137,6 +140,7 @@ typedef union {
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Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1);
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@endcode
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@note MSR_SKYLAKE_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM.
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**/
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#define MSR_SKYLAKE_SGXOWNER1 0x00000301
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@ -158,6 +162,7 @@ typedef union {
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Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS);
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AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
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@endcode
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@note MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
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**/
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#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS 0x0000038E
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@ -269,6 +274,7 @@ typedef union {
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Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);
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AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
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@endcode
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@note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
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**/
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#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
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@ -381,6 +387,7 @@ typedef union {
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Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);
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AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
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@endcode
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@note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
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**/
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#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
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@ -489,6 +496,7 @@ typedef union {
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Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);
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AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);
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@endcode
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@note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.
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**/
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#define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7
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@ -549,6 +557,7 @@ typedef union {
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Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);
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@endcode
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@note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.
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**/
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#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D
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@ -596,6 +605,7 @@ typedef union {
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Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);
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@endcode
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@note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.
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**/
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#define MSR_SKYLAKE_PPERF 0x0000064E
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@ -616,6 +626,7 @@ typedef union {
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Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);
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AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);
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@endcode
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@note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.
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**/
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#define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652
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@ -659,6 +670,7 @@ typedef union {
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Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);
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@endcode
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@note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.
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**/
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#define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653
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@ -677,6 +689,7 @@ typedef union {
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Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);
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@endcode
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@note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.
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**/
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#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655
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@ -694,6 +707,7 @@ typedef union {
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Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);
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@endcode
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@note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.
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**/
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#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656
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@ -714,6 +728,7 @@ typedef union {
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Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);
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@endcode
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@note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.
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**/
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#define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658
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@ -733,6 +748,7 @@ typedef union {
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Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);
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@endcode
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@note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.
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**/
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#define MSR_SKYLAKE_ANY_CORE_C0 0x00000659
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@ -752,6 +768,7 @@ typedef union {
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Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);
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@endcode
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@note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.
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**/
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#define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A
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@ -772,6 +789,7 @@ typedef union {
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Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);
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@endcode
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@note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.
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**/
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#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B
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@ -798,6 +816,7 @@ typedef union {
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Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);
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AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);
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@endcode
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@note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.
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**/
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#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C
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@ -893,6 +912,22 @@ typedef union {
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Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);
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AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);
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@endcode
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@note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.
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@{
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**/
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#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690
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@ -930,6 +965,22 @@ typedef union {
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Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);
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AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);
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@endcode
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@note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.
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MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.
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@{
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**/
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#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0
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@ -969,6 +1020,38 @@ typedef union {
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Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);
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AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);
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@endcode
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@note MSR_SKYLAKE_LBR_INFO_0 is defined as MSR_LBR_INFO_0 in SDM.
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MSR_SKYLAKE_LBR_INFO_1 is defined as MSR_LBR_INFO_1 in SDM.
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MSR_SKYLAKE_LBR_INFO_2 is defined as MSR_LBR_INFO_2 in SDM.
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MSR_SKYLAKE_LBR_INFO_3 is defined as MSR_LBR_INFO_3 in SDM.
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MSR_SKYLAKE_LBR_INFO_4 is defined as MSR_LBR_INFO_4 in SDM.
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MSR_SKYLAKE_LBR_INFO_5 is defined as MSR_LBR_INFO_5 in SDM.
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MSR_SKYLAKE_LBR_INFO_6 is defined as MSR_LBR_INFO_6 in SDM.
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MSR_SKYLAKE_LBR_INFO_7 is defined as MSR_LBR_INFO_7 in SDM.
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MSR_SKYLAKE_LBR_INFO_8 is defined as MSR_LBR_INFO_8 in SDM.
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MSR_SKYLAKE_LBR_INFO_9 is defined as MSR_LBR_INFO_9 in SDM.
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MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM.
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MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM.
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MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM.
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MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM.
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MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM.
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MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM.
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MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM.
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MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM.
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MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM.
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MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM.
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MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM.
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MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM.
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MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM.
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MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM.
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MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM.
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MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM.
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MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM.
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MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM.
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MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM.
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MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM.
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MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM.
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MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.
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@{
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**/
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#define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0
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