OvmfPkg/IndustryStandard: add MCH_DEFAULT_SMBASE* register macros

In Intel datasheet 316966-002 (the "q35 spec"), Table 5-1 "DRAM Controller
Register Address Map (D0:F0)" leaves the byte register at config space
offset 0x9C unused.

On QEMU's Q35 board, for detecting the "SMRAM at default SMBASE" feature,
firmware is expected to write MCH_DEFAULT_SMBASE_QUERY (0xFF) to offset
MCH_DEFAULT_SMBASE_CTL (0x9C), and read back the register. If the value is
MCH_DEFAULT_SMBASE_IN_RAM (0x01), then the feature is available, and the
range mentioned below is open (accessible to code running outside of SMM).

Then, once firmware writes MCH_DEFAULT_SMBASE_LCK (0x02) to the register,
the MCH_DEFAULT_SMBASE_SIZE (128KB) range at 0x3_0000 (SMM_DEFAULT_SMBASE)
gets closed and locked down, and the register becomes read-only. The area
is reopened, and the register becomes read/write, at platform reset.

Add the above-listed macros to "Q35MchIch9.h".

(There are some other unused offsets in Table 5-1; for example we had
scavenged 0x50 for implementing the extended TSEG feature. 0x9C is the
first byte-wide register standing in isolation after 0x50.)

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Message-Id: <20200129214412.2361-4-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

OvmfPkg/Include/IndustryStandard/Q35MchIch9.h

@@ -49,6 +49,12 @@
 #define MCH_PAM5                  0x95
 #define MCH_PAM6                  0x96
 
+#define MCH_DEFAULT_SMBASE_CTL    0x9C
+#define MCH_DEFAULT_SMBASE_QUERY    0xFF
+#define MCH_DEFAULT_SMBASE_IN_RAM   0x01
+#define MCH_DEFAULT_SMBASE_LCK      0x02
+#define MCH_DEFAULT_SMBASE_SIZE     SIZE_128KB
+
 #define MCH_SMRAM                 0x9D
 #define MCH_SMRAM_D_LCK             BIT4
 #define MCH_SMRAM_G_SMRAME          BIT3