mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg: Reformat VE Memory Map code
This change is purely cosmetic, with no functional impact, and only
exists to isolate cosmetic changes from a functional fix.
Some indentation is adjusted.
Overlength lines are re-flowed.
alignment on = is adjusted as some lines exceeded 80 columns.
if statement converted to conditional assignment.
Redundant re-calculation of CacheAttributes removed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
This commit is contained in:
Evan Lloyd
Ard Biesheuvel
parent
960ec4e6fc
commit
05153ff221
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@ -24,17 +24,19 @@
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#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6
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// DDR attributes
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#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
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#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
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#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
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#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
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/**
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Return the Virtual Memory Map of your platform
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This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
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This Virtual Memory Map is used by MemoryInitPei Module to initialize
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the MMU on your platform.
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@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
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Virtual Memory mapping. This array must be ended by a zero-filled
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entry
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@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR
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describing a Physical-to-Virtual Memory
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mapping. This array must be ended by a
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zero-filled entry.
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**/
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VOID
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@ -59,12 +61,12 @@ ArmPlatformGetVirtualMemoryMap (
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HasSparseMemory = TRUE;
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ResourceAttributes =
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED;
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED;
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// Declared the additional DRAM from 2GB to 4GB
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SparseMemoryBase = 0x0880000000;
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@ -81,77 +83,66 @@ ArmPlatformGetVirtualMemoryMap (
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SparseMemorySize = 0x0;
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}
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VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
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VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)
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AllocatePages (EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR)
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* MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
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if (VirtualMemoryTable == NULL) {
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return;
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return;
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}
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if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
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CacheAttributes = DDR_ATTRIBUTES_CACHED;
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} else {
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CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
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}
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CacheAttributes = (FeaturePcdGet(PcdCacheEnable))
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? DDR_ATTRIBUTES_CACHED
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: DDR_ATTRIBUTES_UNCACHED;
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// ReMap (Either NOR Flash or DRAM)
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VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;
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if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) {
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// Map the NOR Flash as Secure Memory
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if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
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VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
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} else {
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VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_UNCACHED;
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}
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} else {
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// DRAM mapping
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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}
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// DDR
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// CPU peripherals. TRM. Manual says not all of them are implemented.
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// SMB CS0-CS1 - NOR Flash 1 & 2
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// SMB CS2 - SRAM
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// Peripheral CS2 and CS3
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
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VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
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VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// Map sparse memory region if present
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if (HasSparseMemory) {
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VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase;
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VirtualMemoryTable[Index].VirtualBase = SparseMemoryBase;
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VirtualMemoryTable[Index].Length = SparseMemorySize;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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VirtualMemoryTable[Index].VirtualBase = SparseMemoryBase;
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VirtualMemoryTable[Index].Length = SparseMemorySize;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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}
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// End of Table
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VirtualMemoryTable[++Index].PhysicalBase = 0;
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VirtualMemoryTable[Index].VirtualBase = 0;
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VirtualMemoryTable[Index].Length = 0;
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VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
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VirtualMemoryTable[Index].VirtualBase = 0;
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VirtualMemoryTable[Index].Length = 0;
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VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
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*VirtualMemoryMap = VirtualMemoryTable;
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}
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