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ArmPlatformPkg: Reformat VE Memory Map code

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This change is purely cosmetic, with no functional impact, and only
exists to isolate cosmetic changes from a functional fix.
    Some indentation is adjusted.
    Overlength lines are re-flowed.
    alignment on = is adjusted as some lines exceeded 80 columns.
    if statement converted to conditional assignment.
    Redundant re-calculation of CacheAttributes removed.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
This commit is contained in:
Evan Lloyd 2016-11-24 19:56:11 +00:00 committed by Ard Biesheuvel
parent 960ec4e6fc
commit 05153ff221
1 changed files with 45 additions and 54 deletions
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33
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
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@ -30,11 +30,13 @@
/**
Return the Virtual Memory Map of your platform
This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
This Virtual Memory Map is used by MemoryInitPei Module to initialize
the MMU on your platform.
@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
Virtual Memory mapping. This array must be ended by a zero-filled
entry
@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR
describing a Physical-to-Virtual Memory
mapping. This array must be ended by a
zero-filled entry.
**/
VOID
@ -81,33 +83,22 @@ ArmPlatformGetVirtualMemoryMap (
SparseMemorySize = 0x0;
}
VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)
AllocatePages (EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR)
* MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
if (VirtualMemoryTable == NULL) {
return;
}
if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
CacheAttributes = DDR_ATTRIBUTES_CACHED;
} else {
CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
}
CacheAttributes = (FeaturePcdGet(PcdCacheEnable))
? DDR_ATTRIBUTES_CACHED
: DDR_ATTRIBUTES_UNCACHED;
// ReMap (Either NOR Flash or DRAM)
VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;
VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;
if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) {
// Map the NOR Flash as Secure Memory
if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
} else {
VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_UNCACHED;
}
} else {
// DRAM mapping
VirtualMemoryTable[Index].Attributes = CacheAttributes;
}
// DDR
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;