mirror of https://github.com/acidanthera/audk.git
OvmfPkg/Sec: Move TDX APs related nasm code to IntelTdxAPs.nasm
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4172 This patch moves the TDX APs nasm code from SecEntry.nasm to IntelTdxAPs.nasm. IntelTdxX64 and OvmfPkgX64 use the same nasm so that it can be easier to be managed. In the following patch there will be AcceptMemory related changes in IntelTdxAPs.nasm. Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
This commit is contained in:
Min M Xu
mergify[bot]
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@ -0,0 +1,58 @@
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;------------------------------------------------------------------------------
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; @file
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; Intel TDX APs
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;
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; Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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%include "TdxCommondefs.inc"
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;
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; Note: BSP never gets here. APs will be unblocked by DXE
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;
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; R8 [31:0] NUM_VCPUS
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; [63:32] MAX_VCPUS
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; R9 [31:0] VCPU_INDEX
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;
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ParkAp:
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do_wait_loop:
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;
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; register itself in [rsp + CpuArrivalOffset]
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;
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mov rax, 1
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lock xadd dword [rsp + CpuArrivalOffset], eax
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inc eax
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.check_arrival_cnt:
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cmp eax, r8d
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je .check_command
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mov eax, dword[rsp + CpuArrivalOffset]
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jmp .check_arrival_cnt
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.check_command:
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mov eax, dword[rsp + CommandOffset]
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cmp eax, MpProtectedModeWakeupCommandNoop
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je .check_command
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cmp eax, MpProtectedModeWakeupCommandWakeup
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je .do_wakeup
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; Don't support this command, so ignore
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jmp .check_command
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.do_wakeup:
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;
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; BSP sets these variables before unblocking APs
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; RAX: WakeupVectorOffset
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; RBX: Relocated mailbox address
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; RBP: vCpuId
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;
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mov rax, 0
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mov eax, dword[rsp + WakeupVectorOffset]
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mov rbx, [rsp + WakeupArgsRelocatedMailBox]
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nop
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jmp rax
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jmp $
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@ -10,7 +10,6 @@
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;------------------------------------------------------------------------------
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#include <Base.h>
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%include "TdxCommondefs.inc"
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DEFAULT REL
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SECTION .text
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@ -49,6 +48,7 @@ ASM_PFX(_ModuleEntryPoint):
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cmp byte[eax], VM_GUEST_TYPE_TDX
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jne InitStack
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%define TDCALL_TDINFO 1
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mov rax, TDCALL_TDINFO
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tdcall
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@ -62,7 +62,9 @@ ASM_PFX(_ModuleEntryPoint):
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mov rax, r9
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and rax, 0xffff
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test rax, rax
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jne ParkAp
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jz InitStack
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mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase)
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jmp ParkAp
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InitStack:
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@ -98,54 +100,4 @@ InitStack:
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sub rsp, 0x20
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call ASM_PFX(SecCoreStartupWithStack)
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;
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; Note: BSP never gets here. APs will be unblocked by DXE
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;
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; R8 [31:0] NUM_VCPUS
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; [63:32] MAX_VCPUS
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; R9 [31:0] VCPU_INDEX
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;
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ParkAp:
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mov rbp, r9
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.do_wait_loop:
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mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase)
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;
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; register itself in [rsp + CpuArrivalOffset]
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;
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mov rax, 1
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lock xadd dword [rsp + CpuArrivalOffset], eax
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inc eax
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.check_arrival_cnt:
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cmp eax, r8d
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je .check_command
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mov eax, dword[rsp + CpuArrivalOffset]
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jmp .check_arrival_cnt
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.check_command:
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mov eax, dword[rsp + CommandOffset]
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cmp eax, MpProtectedModeWakeupCommandNoop
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je .check_command
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cmp eax, MpProtectedModeWakeupCommandWakeup
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je .do_wakeup
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; Don't support this command, so ignore
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jmp .check_command
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.do_wakeup:
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;
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; BSP sets these variables before unblocking APs
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; RAX: WakeupVectorOffset
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; RBX: Relocated mailbox address
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; RBP: vCpuId
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;
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mov rax, 0
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mov eax, dword[rsp + WakeupVectorOffset]
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mov rbx, [rsp + WakeupArgsRelocatedMailBox]
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nop
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jmp rax
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jmp $
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%include "IntelTdxAPs.nasm"
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@ -10,7 +10,6 @@
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;------------------------------------------------------------------------------
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#include <Base.h>
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%include "TdxCommondefs.inc"
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DEFAULT REL
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SECTION .text
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@ -49,6 +48,7 @@ ASM_PFX(_ModuleEntryPoint):
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cmp byte[eax], VM_GUEST_TYPE_TDX
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jne InitStack
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%define TDCALL_TDINFO 1
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mov rax, TDCALL_TDINFO
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tdcall
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@ -62,7 +62,9 @@ ASM_PFX(_ModuleEntryPoint):
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mov rax, r9
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and rax, 0xffff
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test rax, rax
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jne ParkAp
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jz InitStack
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mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase)
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jmp ParkAp
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InitStack:
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@ -98,54 +100,4 @@ InitStack:
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sub rsp, 0x20
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call ASM_PFX(SecCoreStartupWithStack)
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;
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; Note: BSP never gets here. APs will be unblocked by DXE
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;
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; R8 [31:0] NUM_VCPUS
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; [63:32] MAX_VCPUS
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; R9 [31:0] VCPU_INDEX
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;
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ParkAp:
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mov rbp, r9
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.do_wait_loop:
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mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase)
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;
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; register itself in [rsp + CpuArrivalOffset]
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;
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mov rax, 1
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lock xadd dword [rsp + CpuArrivalOffset], eax
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inc eax
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.check_arrival_cnt:
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cmp eax, r8d
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je .check_command
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mov eax, dword[rsp + CpuArrivalOffset]
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jmp .check_arrival_cnt
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.check_command:
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mov eax, dword[rsp + CommandOffset]
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cmp eax, MpProtectedModeWakeupCommandNoop
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je .check_command
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cmp eax, MpProtectedModeWakeupCommandWakeup
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je .do_wakeup
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; Don't support this command, so ignore
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jmp .check_command
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.do_wakeup:
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;
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; BSP sets these variables before unblocking APs
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; RAX: WakeupVectorOffset
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; RBX: Relocated mailbox address
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; RBP: vCpuId
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;
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mov rax, 0
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mov eax, dword[rsp + WakeupVectorOffset]
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mov rbx, [rsp + WakeupArgsRelocatedMailBox]
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nop
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jmp rax
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jmp $
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%include "../../IntelTdx/Sec/X64/IntelTdxAPs.nasm"
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