mirror of https://github.com/acidanthera/audk.git
MdeModulePkg NvmExpressDxe: Fix invalid queue size when creating IO queues
The Maximum Queue Entries Supported (MQES) field in the CAP (Controller Capabilities) register for a NVMe controller restrict the maximum individual queue size that the controller supports. The origin code does not check this value and always uses a hardcode value when creating I/O submission/completion queues for asynchronous transmission. The hardcode value might be larger than the MQES field, this will lead to an 'Invalid Queue Size' error when creating I/O submission/completion queues. The patch will add checks to make sure proper queue size is passed when creating I/O submission/completion queues. Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
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@ -683,6 +683,7 @@ NvmeCreateIoCompletionQueue (
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EFI_STATUS Status;
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NVME_ADMIN_CRIOCQ CrIoCq;
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UINT32 Index;
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UINT16 QueueSize;
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Status = EFI_SUCCESS;
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@ -701,8 +702,18 @@ NvmeCreateIoCompletionQueue (
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CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
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CommandPacket.QueueType = NVME_ADMIN_QUEUE;
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if (Index == 1) {
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QueueSize = NVME_CCQ_SIZE;
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} else {
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if (Private->Cap.Mqes > NVME_ASYNC_CCQ_SIZE) {
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QueueSize = NVME_ASYNC_CCQ_SIZE;
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} else {
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QueueSize = Private->Cap.Mqes;
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}
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}
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CrIoCq.Qid = Index;
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CrIoCq.Qsize = (Index == 1) ? NVME_CCQ_SIZE : NVME_ASYNC_CCQ_SIZE;
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CrIoCq.Qsize = QueueSize;
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CrIoCq.Pc = 1;
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CopyMem (&CommandPacket.NvmeCmd->Cdw10, &CrIoCq, sizeof (NVME_ADMIN_CRIOCQ));
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CommandPacket.NvmeCmd->Flags = CDW10_VALID | CDW11_VALID;
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@ -741,6 +752,7 @@ NvmeCreateIoSubmissionQueue (
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EFI_STATUS Status;
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NVME_ADMIN_CRIOSQ CrIoSq;
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UINT32 Index;
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UINT16 QueueSize;
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Status = EFI_SUCCESS;
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@ -759,8 +771,18 @@ NvmeCreateIoSubmissionQueue (
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CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
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CommandPacket.QueueType = NVME_ADMIN_QUEUE;
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if (Index == 1) {
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QueueSize = NVME_CSQ_SIZE;
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} else {
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if (Private->Cap.Mqes > NVME_ASYNC_CSQ_SIZE) {
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QueueSize = NVME_ASYNC_CSQ_SIZE;
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} else {
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QueueSize = Private->Cap.Mqes;
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}
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}
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CrIoSq.Qid = Index;
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CrIoSq.Qsize = (Index == 1) ? NVME_CSQ_SIZE : NVME_ASYNC_CSQ_SIZE;
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CrIoSq.Qsize = QueueSize;
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CrIoSq.Pc = 1;
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CrIoSq.Cqid = Index;
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CrIoSq.Qprio = 0;
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