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CorebootPayloadPkg/PciHostBridgeLib: Fix the wrong PCI resource limit 

The current PCI resource limit calculation in CorebootPayloadPkg
PciHostBridgeLib is wrong. Adjusted it to match the PciHostBridge
driver's expectation.

Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by : Prince Agyeman <prince.agyeman@intel.com>
This commit is contained in:
Maurice Ma 2016-10-17 10:48:04 -07:00
parent 201fbce6fb
commit 0613ccbd13
1 changed files with 2 additions and 2 deletions
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4
CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
View File

@ -91,7 +91,7 @@ AdjustRootBridgeResource (
// Align IO resource at 4K boundary // Align IO resource at 4K boundary
// //
Mask = 0xFFFULL; Mask = 0xFFFULL;
Io->Limit = (Io->Limit + Mask) & ~Mask; Io->Limit = ((Io->Limit + Mask) & ~Mask) - 1;
if (Io->Base != MAX_UINT64) { if (Io->Base != MAX_UINT64) {
Io->Base &= ~Mask; Io->Base &= ~Mask;
} }
@ -100,7 +100,7 @@ AdjustRootBridgeResource (
// Align MEM resource at 1MB boundary // Align MEM resource at 1MB boundary
// //
Mask = 0xFFFFFULL; Mask = 0xFFFFFULL;
Mem->Limit = (Mem->Limit + Mask) & ~Mask; Mem->Limit = ((Mem->Limit + Mask) & ~Mask) - 1;
if (Mem->Base != MAX_UINT64) { if (Mem->Base != MAX_UINT64) {
Mem->Base &= ~Mask; Mem->Base &= ~Mask;
} }