mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
This commit is contained in:
Leo Duran
Jeff Fan
parent
890d2bd287
commit
061ead7a2d
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@ -4,6 +4,8 @@
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This local APIC library instance supports xAPIC mode only.
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Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -15,6 +17,7 @@
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**/
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#include <Register/Cpuid.h>
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#include <Register/Amd/Cpuid.h>
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#include <Register/Msr.h>
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#include <Register/LocalApic.h>
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@ -29,6 +32,28 @@
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// Library internal functions
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//
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/**
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Determine if the standard CPU signature is "AuthenticAMD".
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@retval TRUE The CPU signature matches.
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@retval FALSE The CPU signature does not match.
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**/
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BOOLEAN
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StandardSignatureIsAuthenticAMD (
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VOID
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)
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{
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UINT32 RegEbx;
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UINT32 RegEcx;
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UINT32 RegEdx;
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AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
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return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
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RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
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RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
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}
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/**
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Determine if the CPU supports the Local APIC Base Address MSR.
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@ -967,19 +992,29 @@ GetProcessorLocationByApicId (
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)
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{
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BOOLEAN TopologyLeafSupported;
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UINTN ThreadBits;
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UINTN CoreBits;
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CPUID_VERSION_INFO_EBX VersionInfoEbx;
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CPUID_VERSION_INFO_EDX VersionInfoEdx;
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CPUID_CACHE_PARAMS_EAX CacheParamsEax;
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CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
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CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
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CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
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UINT32 MaxCpuIdIndex;
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CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
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CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
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CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
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CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
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UINT32 MaxStandardCpuIdIndex;
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UINT32 MaxExtendedCpuIdIndex;
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UINT32 SubIndex;
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UINTN LevelType;
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UINT32 MaxLogicProcessorsPerPackage;
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UINT32 MaxCoresPerPackage;
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UINT32 MaxThreadPerPackageMask;
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UINT32 ActualThreadPerPackageMask;
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UINT32 MaxCoresPerNode;
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UINT32 CorePerNodeMask;
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UINT32 ApicIdShift;
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UINTN ThreadBits;
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UINTN CoreBits;
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//
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// Check if the processor is capable of supporting more than one logical processor.
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@ -998,24 +1033,24 @@ GetProcessorLocationByApicId (
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return;
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}
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//
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// Assume three-level mapping of APIC ID: Package|Core|Thread.
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//
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ThreadBits = 0;
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CoreBits = 0;
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//
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// Assume three-level mapping of APIC ID: Package:Core:SMT.
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// Get max index of CPUID
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//
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TopologyLeafSupported = FALSE;
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//
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// Get the max index of basic CPUID
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//
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AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
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AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
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AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
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//
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// If the extended topology enumeration leaf is available, it
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// is the preferred mechanism for enumerating topology.
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//
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if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
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TopologyLeafSupported = FALSE;
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if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
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AsmCpuidEx(
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CPUID_EXTENDED_TOPOLOGY,
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0,
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@ -1065,21 +1100,79 @@ GetProcessorLocationByApicId (
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}
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if (!TopologyLeafSupported) {
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//
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// Get logical processor count
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//
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AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
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MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
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if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
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AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
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MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
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//
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// Assume single-core processor
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//
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MaxCoresPerPackage = 1;
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//
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// Check for topology extensions on AMD processor
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//
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if (StandardSignatureIsAuthenticAMD()) {
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if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
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AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
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if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
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AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,
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&AmdProcessorTopologyEcx.Uint32, NULL);
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//
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// Get cores per processor package
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//
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MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
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//
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// Account for actual thread count (e.g., SMT disabled)
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//
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AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
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MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
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ActualThreadPerPackageMask = 1;
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while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
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ActualThreadPerPackageMask <<= 1;
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}
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//
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// Adjust APIC Id to report concatenation of Package|Core|Thread.
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//
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if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
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MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
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CorePerNodeMask = 1;
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while (CorePerNodeMask < MaxCoresPerNode) {
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CorePerNodeMask <<= 1;
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}
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CorePerNodeMask -= 1;
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ApicIdShift = 0;
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do {
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ApicIdShift += 1;
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ActualThreadPerPackageMask <<= 1;
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} while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
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InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
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}
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}
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}
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}
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else {
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//
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// Must be a single-core processor.
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// Extract core count based on CACHE information
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//
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MaxCoresPerPackage = 1;
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if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
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AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
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if (CacheParamsEax.Uint32 != 0) {
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MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
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}
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}
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}
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ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
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CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
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CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
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}
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if (Thread != NULL) {
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*Thread = InitialApicId & ((1 << ThreadBits) - 1);
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@ -5,6 +5,8 @@
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which have xAPIC and x2APIC modes.
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Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -16,6 +18,7 @@
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**/
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#include <Register/Cpuid.h>
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#include <Register/Amd/Cpuid.h>
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#include <Register/Msr.h>
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#include <Register/LocalApic.h>
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@ -30,6 +33,28 @@
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// Library internal functions
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//
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/**
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Determine if the standard CPU signature is "AuthenticAMD".
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@retval TRUE The CPU signature matches.
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@retval FALSE The CPU signature does not match.
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**/
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BOOLEAN
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StandardSignatureIsAuthenticAMD (
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VOID
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)
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{
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UINT32 RegEbx;
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UINT32 RegEcx;
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UINT32 RegEdx;
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AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
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return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
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RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
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RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
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}
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/**
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Determine if the CPU supports the Local APIC Base Address MSR.
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@ -1062,19 +1087,29 @@ GetProcessorLocationByApicId (
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)
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{
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BOOLEAN TopologyLeafSupported;
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UINTN ThreadBits;
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UINTN CoreBits;
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CPUID_VERSION_INFO_EBX VersionInfoEbx;
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CPUID_VERSION_INFO_EDX VersionInfoEdx;
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CPUID_CACHE_PARAMS_EAX CacheParamsEax;
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CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
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CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
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CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
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UINT32 MaxCpuIdIndex;
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CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
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CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
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CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
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CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
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UINT32 MaxStandardCpuIdIndex;
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UINT32 MaxExtendedCpuIdIndex;
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UINT32 SubIndex;
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UINTN LevelType;
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UINT32 MaxLogicProcessorsPerPackage;
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UINT32 MaxCoresPerPackage;
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UINT32 MaxThreadPerPackageMask;
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UINT32 ActualThreadPerPackageMask;
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UINT32 MaxCoresPerNode;
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UINT32 CorePerNodeMask;
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UINT32 ApicIdShift;
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UINTN ThreadBits;
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UINTN CoreBits;
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//
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// Check if the processor is capable of supporting more than one logical processor.
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@ -1093,24 +1128,24 @@ GetProcessorLocationByApicId (
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return;
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}
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//
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// Assume three-level mapping of APIC ID: Package|Core|Thread.
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//
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ThreadBits = 0;
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CoreBits = 0;
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//
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// Assume three-level mapping of APIC ID: Package:Core:SMT.
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// Get max index of CPUID
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//
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TopologyLeafSupported = FALSE;
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//
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// Get the max index of basic CPUID
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//
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AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
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AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
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AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
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//
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// If the extended topology enumeration leaf is available, it
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// is the preferred mechanism for enumerating topology.
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//
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if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
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TopologyLeafSupported = FALSE;
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if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
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AsmCpuidEx(
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CPUID_EXTENDED_TOPOLOGY,
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0,
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@ -1160,21 +1195,79 @@ GetProcessorLocationByApicId (
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}
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if (!TopologyLeafSupported) {
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//
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// Get logical processor count
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//
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AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
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MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
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if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
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AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
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MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
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//
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// Assume single-core processor
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//
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MaxCoresPerPackage = 1;
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//
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// Check for topology extensions on AMD processor
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//
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if (StandardSignatureIsAuthenticAMD()) {
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if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
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AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
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if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
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AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,
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&AmdProcessorTopologyEcx.Uint32, NULL);
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//
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// Get cores per processor package
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//
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MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
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//
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// Account for actual thread count (e.g., SMT disabled)
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//
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AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
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MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
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ActualThreadPerPackageMask = 1;
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while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
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ActualThreadPerPackageMask <<= 1;
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}
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//
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// Adjust APIC Id to report concatenation of Package|Core|Thread.
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//
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if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
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MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
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CorePerNodeMask = 1;
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while (CorePerNodeMask < MaxCoresPerNode) {
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CorePerNodeMask <<= 1;
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}
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CorePerNodeMask -= 1;
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ApicIdShift = 0;
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do {
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ApicIdShift += 1;
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ActualThreadPerPackageMask <<= 1;
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} while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
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InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
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}
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}
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}
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}
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else {
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//
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// Must be a single-core processor.
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// Extract core count based on CACHE information
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//
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MaxCoresPerPackage = 1;
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if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
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AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
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if (CacheParamsEax.Uint32 != 0) {
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MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
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}
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}
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}
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ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
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CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
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CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
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}
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if (Thread != NULL) {
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*Thread = InitialApicId & ((1 << ThreadBits) - 1);
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