mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg/Sec: Fix typo and Remove magic value
- Replace the '0' that defined the primary core by the macro ARM_PRIMARY_CORE - Fix mispellings and coding style git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11589 6f19259b-4bc3-4df7-8a09-765794883524
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oliviermartin
parent
95650ceda8
commit
0620eec942
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@ -19,24 +19,32 @@
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/ArmLib.h>
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#include <Chipset/ArmV7.h>
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#include <Drivers/PL390Gic.h>
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#include <Library/SerialPortLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Chipset/ArmV7.h>
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#include <Drivers/PL390Gic.h>
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#define ARM_PRIMARY_CORE 0
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#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);
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extern VOID *monitor_vector_table;
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VOID ArmSetupGicNonSecure (
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IN INTN GicDistributorBase,
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IN INTN GicInterruptInterfaceBase
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VOID
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ArmSetupGicNonSecure (
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IN INTN GicDistributorBase,
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IN INTN GicInterruptInterfaceBase
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);
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// Vector Table for Sec Phase
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VOID SecVectorTable (VOID);
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VOID
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SecVectorTable (
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VOID
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);
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VOID NonSecureWaitForFirmware (
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VOID
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NonSecureWaitForFirmware (
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VOID
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);
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@ -64,7 +72,7 @@ CEntryPoint (
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UINTN CharCount;
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// Primary CPU clears out the SCU tag RAMs, secondaries wait
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if (CoreId == 0) {
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if (CoreId == ARM_PRIMARY_CORE) {
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if (FixedPcdGet32(PcdMPCoreSupport)) {
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ArmInvalidScu();
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}
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@ -104,7 +112,7 @@ CEntryPoint (
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ArmEnableVFP();
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}
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if (CoreId == 0) {
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if (CoreId == ARM_PRIMARY_CORE) {
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// Initialize peripherals that must be done at the early stage
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// Example: Some L2x0 controllers must be initialized in Secure World
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ArmPlatformInitialize ();
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@ -116,7 +124,7 @@ CEntryPoint (
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ArmPlatformInitializeSystemMemory();
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}
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// Turn Off NOR flash remapping to 0. We can will now see DRAM in low memory
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// Some platform can change their physical memory mapping
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ArmPlatformBootRemapping();
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}
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@ -134,8 +142,8 @@ CEntryPoint (
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ArmWriteVMBar((UINT32) &monitor_vector_table);
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//-------------------- Monitor Mode ---------------------
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// setup the Trustzone Chipsets
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if (CoreId == 0) {
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// Setup the Trustzone Chipsets
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if (CoreId == ARM_PRIMARY_CORE) {
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ArmPlatformTrustzoneInit();
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// Wake up the secondary cores by sending a interrupt to everyone else
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@ -153,7 +161,7 @@ CEntryPoint (
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PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
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} else {
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// The secondary cores need to wait until the Trustzone chipsets configuration is done
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// before swtching to Non Secure World
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// before switching to Non Secure World
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// Enabled GIC CPU Interface
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PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
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@ -161,8 +169,8 @@ CEntryPoint (
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// Waiting for the SGI from the primary core
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ArmCallWFI();
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//Acknowledge the interrupt and send End of Interrupt signal.
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PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
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// Acknowledge the interrupt and send End of Interrupt signal.
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PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
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}
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// Transfer the interrupt to Non-secure World
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@ -179,11 +187,11 @@ CEntryPoint (
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// security state (SCR_AW), CPSR.F modified in any security state (SCR_FW)
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ArmWriteScr(SCR_NS | SCR_FW | SCR_AW);
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} else {
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if(0 == CoreId){
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if (CoreId == ARM_PRIMARY_CORE) {
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SerialPrint ("Trust Zone Configuration is disabled\n\r");
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}
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//Trustzone is not enabled, just enable the Distributor and CPU interface
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// Trustzone is not enabled, just enable the Distributor and CPU interface
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PL390GicEnableInterruptInterface(PcdGet32(PcdGicInterruptInterfaceBase));
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// With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
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@ -194,7 +202,7 @@ CEntryPoint (
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// If ArmVe has not been built as Standalone then we need to patch the DRAM to add an infinite loop at the start address
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if (FeaturePcdGet(PcdStandalone) == FALSE) {
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if (CoreId == 0) {
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if (CoreId == ARM_PRIMARY_CORE) {
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UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFdBaseAddress);
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// Patch the DRAM to make an infinite loop at the start address
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@ -228,18 +236,22 @@ CEntryPoint (
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// When the firmware is built as not Standalone, the secondary cores need to wait the firmware
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// entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.
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VOID NonSecureWaitForFirmware() {
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VOID
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NonSecureWaitForFirmware (
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VOID
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)
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{
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VOID (*secondary_start)(VOID);
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// The secondary cores will execute the fimrware once wake from WFI.
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// The secondary cores will execute the firmware once wake from WFI.
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secondary_start = (VOID (*)())PcdGet32(PcdNormalFdBaseAddress);
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ArmCallWFI();
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//Acknowledge the interrupt and send End of Interrupt signal.
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PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
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// Acknowledge the interrupt and send End of Interrupt signal.
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PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),ARM_PRIMARY_CORE);
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//Jump to secondary core entry point.
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// Jump to secondary core entry point.
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secondary_start();
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// PEI Core should always load and never return
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