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UefiCpuPkg: Implements MmSaveStateLib for Intel
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 Implements MmSaveStateLib library interfaces to read and write save state registers for Intel processor family. Moves Intel and AMD common functionality to common area. Cc: Paul Grimes <paul.grimes@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
This commit is contained in:
Abdul Lateef Attar
mergify[bot]
parent
867851dc30
commit
065fa2dcc2
410
UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveState.c
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410
UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveState.c
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/** @file
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Provides services to access SMRAM Save State Map
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Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "MmSaveState.h"
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#include <Register/Intel/SmramSaveStateMap.h>
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#include <Register/Intel/Cpuid.h>
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#include <Library/BaseLib.h>
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#define INTEL_MM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1
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#define INTEL_MM_SAVE_STATE_REGISTER_IOMISC_INDEX 2
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#define INTEL_MM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX 3
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#define INTEL_MM_SAVE_STATE_REGISTER_MAX_INDEX 4
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///
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/// Macro used to simplify the lookup table entries of type CPU_MM_SAVE_STATE_LOOKUP_ENTRY
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///
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#define MM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)
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///
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/// Lookup table used to retrieve the widths and offsets associated with each
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/// supported EFI_MM_SAVE_STATE_REGISTER value
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///
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CONST CPU_MM_SAVE_STATE_LOOKUP_ENTRY mCpuWidthOffset[] = {
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{ 0, 0, 0, 0, 0, FALSE }, // Reserved
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//
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// Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol.
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//
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{ 4, 4, MM_CPU_OFFSET (x86.SMMRevId), MM_CPU_OFFSET (x64.SMMRevId), 0, FALSE }, // INTEL_MM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1
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{ 4, 4, MM_CPU_OFFSET (x86.IOMisc), MM_CPU_OFFSET (x64.IOMisc), 0, FALSE }, // INTEL_MM_SAVE_STATE_REGISTER_IOMISC_INDEX = 2
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{ 4, 8, MM_CPU_OFFSET (x86.IOMemAddr), MM_CPU_OFFSET (x64.IOMemAddr), MM_CPU_OFFSET (x64.IOMemAddr) + 4, FALSE }, // INTEL_MM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX = 3
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//
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// CPU Save State registers defined in PI SMM CPU Protocol.
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//
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{ 0, 8, 0, MM_CPU_OFFSET (x64.GdtBaseLoDword), MM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE }, // EFI_MM_SAVE_STATE_REGISTER_GDTBASE = 4
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{ 0, 8, 0, MM_CPU_OFFSET (x64.IdtBaseLoDword), MM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE }, // EFI_MM_SAVE_STATE_REGISTER_IDTBASE = 5
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{ 0, 8, 0, MM_CPU_OFFSET (x64.LdtBaseLoDword), MM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTBASE = 6
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{ 0, 0, 0, 0, 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT = 7
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{ 0, 0, 0, 0, 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT = 8
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{ 0, 0, 0, 0, 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT = 9
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{ 0, 0, 0, 0, 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTINFO = 10
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{ 4, 4, MM_CPU_OFFSET (x86._ES), MM_CPU_OFFSET (x64._ES), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_ES = 20
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{ 4, 4, MM_CPU_OFFSET (x86._CS), MM_CPU_OFFSET (x64._CS), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_CS = 21
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{ 4, 4, MM_CPU_OFFSET (x86._SS), MM_CPU_OFFSET (x64._SS), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_SS = 22
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{ 4, 4, MM_CPU_OFFSET (x86._DS), MM_CPU_OFFSET (x64._DS), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_DS = 23
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{ 4, 4, MM_CPU_OFFSET (x86._FS), MM_CPU_OFFSET (x64._FS), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_FS = 24
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{ 4, 4, MM_CPU_OFFSET (x86._GS), MM_CPU_OFFSET (x64._GS), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_GS = 25
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{ 0, 4, 0, MM_CPU_OFFSET (x64._LDTR), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL = 26
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{ 4, 4, MM_CPU_OFFSET (x86._TR), MM_CPU_OFFSET (x64._TR), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_TR_SEL = 27
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{ 4, 8, MM_CPU_OFFSET (x86._DR7), MM_CPU_OFFSET (x64._DR7), MM_CPU_OFFSET (x64._DR7) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_DR7 = 28
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{ 4, 8, MM_CPU_OFFSET (x86._DR6), MM_CPU_OFFSET (x64._DR6), MM_CPU_OFFSET (x64._DR6) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_DR6 = 29
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{ 0, 8, 0, MM_CPU_OFFSET (x64._R8), MM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R8 = 30
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{ 0, 8, 0, MM_CPU_OFFSET (x64._R9), MM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R9 = 31
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{ 0, 8, 0, MM_CPU_OFFSET (x64._R10), MM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R10 = 32
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{ 0, 8, 0, MM_CPU_OFFSET (x64._R11), MM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R11 = 33
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{ 0, 8, 0, MM_CPU_OFFSET (x64._R12), MM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R12 = 34
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{ 0, 8, 0, MM_CPU_OFFSET (x64._R13), MM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R13 = 35
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{ 0, 8, 0, MM_CPU_OFFSET (x64._R14), MM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R14 = 36
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{ 0, 8, 0, MM_CPU_OFFSET (x64._R15), MM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R15 = 37
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{ 4, 8, MM_CPU_OFFSET (x86._EAX), MM_CPU_OFFSET (x64._RAX), MM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RAX = 38
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{ 4, 8, MM_CPU_OFFSET (x86._EBX), MM_CPU_OFFSET (x64._RBX), MM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RBX = 39
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{ 4, 8, MM_CPU_OFFSET (x86._ECX), MM_CPU_OFFSET (x64._RCX), MM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RCX = 40
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{ 4, 8, MM_CPU_OFFSET (x86._EDX), MM_CPU_OFFSET (x64._RDX), MM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RDX = 41
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{ 4, 8, MM_CPU_OFFSET (x86._ESP), MM_CPU_OFFSET (x64._RSP), MM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RSP = 42
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{ 4, 8, MM_CPU_OFFSET (x86._EBP), MM_CPU_OFFSET (x64._RBP), MM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RBP = 43
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{ 4, 8, MM_CPU_OFFSET (x86._ESI), MM_CPU_OFFSET (x64._RSI), MM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RSI = 44
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{ 4, 8, MM_CPU_OFFSET (x86._EDI), MM_CPU_OFFSET (x64._RDI), MM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RDI = 45
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{ 4, 8, MM_CPU_OFFSET (x86._EIP), MM_CPU_OFFSET (x64._RIP), MM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RIP = 46
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{ 4, 8, MM_CPU_OFFSET (x86._EFLAGS), MM_CPU_OFFSET (x64._RFLAGS), MM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RFLAGS = 51
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{ 4, 8, MM_CPU_OFFSET (x86._CR0), MM_CPU_OFFSET (x64._CR0), MM_CPU_OFFSET (x64._CR0) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_CR0 = 52
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{ 4, 8, MM_CPU_OFFSET (x86._CR3), MM_CPU_OFFSET (x64._CR3), MM_CPU_OFFSET (x64._CR3) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_CR3 = 53
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{ 0, 4, 0, MM_CPU_OFFSET (x64._CR4), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_CR4 = 54
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};
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///
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/// Structure used to build a lookup table for the IOMisc width information
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///
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typedef struct {
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UINT8 Width;
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EFI_MM_SAVE_STATE_IO_WIDTH IoWidth;
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} CPU_MM_SAVE_STATE_IO_WIDTH;
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///
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/// Lookup table for the IOMisc width information
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///
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STATIC CONST CPU_MM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] = {
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{ 0, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 0
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{ 1, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 }, // SMM_IO_LENGTH_BYTE = 1
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{ 2, EFI_MM_SAVE_STATE_IO_WIDTH_UINT16 }, // SMM_IO_LENGTH_WORD = 2
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{ 0, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 3
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{ 4, EFI_MM_SAVE_STATE_IO_WIDTH_UINT32 }, // SMM_IO_LENGTH_DWORD = 4
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{ 0, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 5
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{ 0, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 6
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{ 0, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 } // Undefined = 7
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};
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///
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/// Lookup table for the IOMisc type information
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///
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STATIC CONST EFI_MM_SAVE_STATE_IO_TYPE mSmmCpuIoType[] = {
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EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_DX = 0
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EFI_MM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_IN_DX = 1
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EFI_MM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_OUTS = 2
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EFI_MM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_INS = 3
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(EFI_MM_SAVE_STATE_IO_TYPE)0, // Undefined = 4
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(EFI_MM_SAVE_STATE_IO_TYPE)0, // Undefined = 5
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EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_OUTS = 6
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EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_INS = 7
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EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_IMMEDIATE = 8
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EFI_MM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_OUT_IMMEDIATE = 9
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(EFI_MM_SAVE_STATE_IO_TYPE)0, // Undefined = 10
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(EFI_MM_SAVE_STATE_IO_TYPE)0, // Undefined = 11
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(EFI_MM_SAVE_STATE_IO_TYPE)0, // Undefined = 12
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(EFI_MM_SAVE_STATE_IO_TYPE)0, // Undefined = 13
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(EFI_MM_SAVE_STATE_IO_TYPE)0, // Undefined = 14
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(EFI_MM_SAVE_STATE_IO_TYPE)0 // Undefined = 15
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};
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/**
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Read an SMM Save State register on the target processor. If this function
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returns EFI_UNSUPPORTED, then the caller is responsible for reading the
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SMM Save Sate register.
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@param[in] CpuIndex The index of the CPU to read the SMM Save State. The
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value must be between 0 and the NumberOfCpus field in
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the System Management System Table (SMST).
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@param[in] Register The SMM Save State register to read.
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@param[in] Width The number of bytes to read from the CPU save state.
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@param[out] Buffer Upon return, this holds the CPU register value read
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from the save state.
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@retval EFI_SUCCESS The register was read from Save State.
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@retval EFI_INVALID_PARAMTER Buffer is NULL.
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@retval EFI_UNSUPPORTED This function does not support reading Register.
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@retval EFI_NOT_FOUND If desired Register not found.
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**/
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EFI_STATUS
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EFIAPI
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MmSaveStateReadRegister (
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IN UINTN CpuIndex,
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IN EFI_MM_SAVE_STATE_REGISTER Register,
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IN UINTN Width,
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OUT VOID *Buffer
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)
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{
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UINT32 SmmRevId;
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SMRAM_SAVE_STATE_IOMISC IoMisc;
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EFI_MM_SAVE_STATE_IO_INFO *IoInfo;
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//
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// Check for special EFI_MM_SAVE_STATE_REGISTER_LMA
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//
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if (Register == EFI_MM_SAVE_STATE_REGISTER_LMA) {
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//
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// Only byte access is supported for this register
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//
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if (Width != 1) {
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return EFI_INVALID_PARAMETER;
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}
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*(UINT8 *)Buffer = MmSaveStateGetRegisterLma ();
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return EFI_SUCCESS;
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}
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//
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// Check for special EFI_MM_SAVE_STATE_REGISTER_IO
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//
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if (Register == EFI_MM_SAVE_STATE_REGISTER_IO) {
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//
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// Get SMM Revision ID
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//
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MmSaveStateReadRegisterByIndex (CpuIndex, INTEL_MM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId);
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//
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// See if the CPU supports the IOMisc register in the save state
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//
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if (SmmRevId < SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC) {
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return EFI_NOT_FOUND;
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}
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//
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// Get the IOMisc register value
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//
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MmSaveStateReadRegisterByIndex (CpuIndex, INTEL_MM_SAVE_STATE_REGISTER_IOMISC_INDEX, sizeof (IoMisc.Uint32), &IoMisc.Uint32);
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//
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// Check for the SMI_FLAG in IOMisc
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//
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if (IoMisc.Bits.SmiFlag == 0) {
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return EFI_NOT_FOUND;
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}
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//
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// Only support IN/OUT, but not INS/OUTS/REP INS/REP OUTS.
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//
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if ((mSmmCpuIoType[IoMisc.Bits.Type] != EFI_MM_SAVE_STATE_IO_TYPE_INPUT) &&
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(mSmmCpuIoType[IoMisc.Bits.Type] != EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT))
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{
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return EFI_NOT_FOUND;
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}
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//
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// Compute index for the I/O Length and I/O Type lookup tables
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//
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if ((mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0) || (mSmmCpuIoType[IoMisc.Bits.Type] == 0)) {
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return EFI_NOT_FOUND;
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}
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//
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// Make sure the incoming buffer is large enough to hold IoInfo before accessing
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//
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if (Width < sizeof (EFI_MM_SAVE_STATE_IO_INFO)) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// Zero the IoInfo structure that will be returned in Buffer
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//
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IoInfo = (EFI_MM_SAVE_STATE_IO_INFO *)Buffer;
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ZeroMem (IoInfo, sizeof (EFI_MM_SAVE_STATE_IO_INFO));
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//
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// Use lookup tables to help fill in all the fields of the IoInfo structure
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//
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IoInfo->IoPort = (UINT16)IoMisc.Bits.Port;
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IoInfo->IoWidth = mSmmCpuIoWidth[IoMisc.Bits.Length].IoWidth;
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IoInfo->IoType = mSmmCpuIoType[IoMisc.Bits.Type];
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MmSaveStateReadRegister (CpuIndex, EFI_MM_SAVE_STATE_REGISTER_RAX, mSmmCpuIoWidth[IoMisc.Bits.Length].Width, &IoInfo->IoData);
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return EFI_SUCCESS;
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}
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//
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// Convert Register to a register lookup table index
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//
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return MmSaveStateReadRegisterByIndex (CpuIndex, MmSaveStateGetRegisterIndex (Register, INTEL_MM_SAVE_STATE_REGISTER_MAX_INDEX), Width, Buffer);
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}
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/**
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Writes an SMM Save State register on the target processor. If this function
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returns EFI_UNSUPPORTED, then the caller is responsible for writing the
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SMM Save Sate register.
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@param[in] CpuIndex The index of the CPU to write the SMM Save State. The
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value must be between 0 and the NumberOfCpus field in
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||||||
|
the System Management System Table (SMST).
|
||||||
|
@param[in] Register The SMM Save State register to write.
|
||||||
|
@param[in] Width The number of bytes to write to the CPU save state.
|
||||||
|
@param[in] Buffer Upon entry, this holds the new CPU register value.
|
||||||
|
|
||||||
|
@retval EFI_SUCCESS The register was written to Save State.
|
||||||
|
@retval EFI_INVALID_PARAMTER Buffer is NULL.
|
||||||
|
@retval EFI_UNSUPPORTED This function does not support writing Register.
|
||||||
|
@retval EFI_NOT_FOUND If desired Register not found.
|
||||||
|
**/
|
||||||
|
EFI_STATUS
|
||||||
|
EFIAPI
|
||||||
|
MmSaveStateWriteRegister (
|
||||||
|
IN UINTN CpuIndex,
|
||||||
|
IN EFI_MM_SAVE_STATE_REGISTER Register,
|
||||||
|
IN UINTN Width,
|
||||||
|
IN CONST VOID *Buffer
|
||||||
|
)
|
||||||
|
{
|
||||||
|
UINTN RegisterIndex;
|
||||||
|
SMRAM_SAVE_STATE_MAP *CpuSaveState;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Writes to EFI_MM_SAVE_STATE_REGISTER_LMA are ignored
|
||||||
|
//
|
||||||
|
if (Register == EFI_MM_SAVE_STATE_REGISTER_LMA) {
|
||||||
|
return EFI_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Writes to EFI_MM_SAVE_STATE_REGISTER_IO are not supported
|
||||||
|
//
|
||||||
|
if (Register == EFI_MM_SAVE_STATE_REGISTER_IO) {
|
||||||
|
return EFI_NOT_FOUND;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Convert Register to a register lookup table index
|
||||||
|
//
|
||||||
|
RegisterIndex = MmSaveStateGetRegisterIndex (Register, INTEL_MM_SAVE_STATE_REGISTER_MAX_INDEX);
|
||||||
|
if (RegisterIndex == 0) {
|
||||||
|
return EFI_NOT_FOUND;
|
||||||
|
}
|
||||||
|
|
||||||
|
CpuSaveState = gSmst->CpuSaveState[CpuIndex];
|
||||||
|
|
||||||
|
//
|
||||||
|
// Do not write non-writable SaveState, because it will cause exception.
|
||||||
|
//
|
||||||
|
if (!mCpuWidthOffset[RegisterIndex].Writeable) {
|
||||||
|
return EFI_UNSUPPORTED;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Check CPU mode
|
||||||
|
//
|
||||||
|
if (MmSaveStateGetRegisterLma () == EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT) {
|
||||||
|
//
|
||||||
|
// If 32-bit mode width is zero, then the specified register can not be accessed
|
||||||
|
//
|
||||||
|
if (mCpuWidthOffset[RegisterIndex].Width32 == 0) {
|
||||||
|
return EFI_NOT_FOUND;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
|
||||||
|
//
|
||||||
|
if (Width > mCpuWidthOffset[RegisterIndex].Width32) {
|
||||||
|
return EFI_INVALID_PARAMETER;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Write SMM State register
|
||||||
|
//
|
||||||
|
ASSERT (CpuSaveState != NULL);
|
||||||
|
CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
|
||||||
|
} else {
|
||||||
|
//
|
||||||
|
// If 64-bit mode width is zero, then the specified register can not be accessed
|
||||||
|
//
|
||||||
|
if (mCpuWidthOffset[RegisterIndex].Width64 == 0) {
|
||||||
|
return EFI_NOT_FOUND;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
|
||||||
|
//
|
||||||
|
if (Width > mCpuWidthOffset[RegisterIndex].Width64) {
|
||||||
|
return EFI_INVALID_PARAMETER;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Write at most 4 of the lower bytes of SMM State register
|
||||||
|
//
|
||||||
|
CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
|
||||||
|
if (Width > 4) {
|
||||||
|
//
|
||||||
|
// Write at most 4 of the upper bytes of SMM State register
|
||||||
|
//
|
||||||
|
CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return EFI_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
Returns LMA value of the Processor.
|
||||||
|
|
||||||
|
@retval UINT8 returns LMA bit value.
|
||||||
|
**/
|
||||||
|
UINT8
|
||||||
|
MmSaveStateGetRegisterLma (
|
||||||
|
VOID
|
||||||
|
)
|
||||||
|
{
|
||||||
|
UINT32 RegEax;
|
||||||
|
UINT32 RegEdx;
|
||||||
|
UINTN FamilyId;
|
||||||
|
UINTN ModelId;
|
||||||
|
UINT8 SmmSaveStateRegisterLma;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Retrieve CPU Family
|
||||||
|
//
|
||||||
|
AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);
|
||||||
|
FamilyId = (RegEax >> 8) & 0xf;
|
||||||
|
ModelId = (RegEax >> 4) & 0xf;
|
||||||
|
if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
|
||||||
|
ModelId = ModelId | ((RegEax >> 12) & 0xf0);
|
||||||
|
}
|
||||||
|
|
||||||
|
RegEdx = 0;
|
||||||
|
AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
|
||||||
|
if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
|
||||||
|
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Determine the mode of the CPU at the time an SMI occurs
|
||||||
|
// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
|
||||||
|
// Volume 3C, Section 34.4.1.1
|
||||||
|
//
|
||||||
|
SmmSaveStateRegisterLma = EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT;
|
||||||
|
if ((RegEdx & BIT29) != 0) {
|
||||||
|
SmmSaveStateRegisterLma = EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (FamilyId == 0x06) {
|
||||||
|
if ((ModelId == 0x17) || (ModelId == 0x0f) || (ModelId == 0x1c)) {
|
||||||
|
SmmSaveStateRegisterLma = EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return SmmSaveStateRegisterLma;
|
||||||
|
}
|
||||||
34
UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf
Normal file
34
UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf
Normal file
@ -0,0 +1,34 @@
|
|||||||
|
## @file
|
||||||
|
# SMM Smram save state service lib.
|
||||||
|
#
|
||||||
|
# This is SMM Smram save state service lib that provide service to read and
|
||||||
|
# save savestate area registers.
|
||||||
|
#
|
||||||
|
# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
#
|
||||||
|
##
|
||||||
|
|
||||||
|
[Defines]
|
||||||
|
INF_VERSION = 1.29
|
||||||
|
BASE_NAME = IntelMmSaveStateLib
|
||||||
|
FILE_GUID = 37E8137B-9F74-4250-8951-7A970A3C39C0
|
||||||
|
MODULE_TYPE = DXE_SMM_DRIVER
|
||||||
|
VERSION_STRING = 1.0
|
||||||
|
LIBRARY_CLASS = MmSaveStateLib
|
||||||
|
|
||||||
|
[Sources]
|
||||||
|
MmSaveState.h
|
||||||
|
MmSaveStateCommon.c
|
||||||
|
IntelMmSaveState.c
|
||||||
|
|
||||||
|
[Packages]
|
||||||
|
MdePkg/MdePkg.dec
|
||||||
|
UefiCpuPkg/UefiCpuPkg.dec
|
||||||
|
|
||||||
|
[LibraryClasses]
|
||||||
|
BaseLib
|
||||||
|
BaseMemoryLib
|
||||||
|
DebugLib
|
||||||
|
SmmServicesTableLib
|
||||||
@ -100,7 +100,7 @@
|
|||||||
MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf
|
MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf
|
||||||
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
|
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
|
||||||
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
|
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
|
||||||
MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
|
MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf
|
||||||
|
|
||||||
[LibraryClasses.common.MM_STANDALONE]
|
[LibraryClasses.common.MM_STANDALONE]
|
||||||
MmServicesTableLib|MdePkg/Library/StandaloneMmServicesTableLib/StandaloneMmServicesTableLib.inf
|
MmServicesTableLib|MdePkg/Library/StandaloneMmServicesTableLib/StandaloneMmServicesTableLib.inf
|
||||||
@ -174,6 +174,7 @@
|
|||||||
FILE_GUID = B7242C74-BD21-49EE-84B4-07162E8C080D
|
FILE_GUID = B7242C74-BD21-49EE-84B4-07162E8C080D
|
||||||
<LibraryClasses>
|
<LibraryClasses>
|
||||||
SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
|
SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
|
||||||
|
MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
|
||||||
}
|
}
|
||||||
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
|
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
|
||||||
UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
|
UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
|
||||||
@ -191,6 +192,7 @@
|
|||||||
UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultReportLib/UnitTestResultReportLibConOut.inf
|
UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultReportLib/UnitTestResultReportLibConOut.inf
|
||||||
}
|
}
|
||||||
UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
|
UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
|
||||||
|
UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf
|
||||||
UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
|
UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
|
||||||
|
|
||||||
[Components.X64]
|
[Components.X64]
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user