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ArmPkg/ArmV7Mmu: make cached translation table accesses shareable 

To align with the way normal cacheable memory is mapped, set the
shareable bit for cached accesses performed by the page table walker.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18896 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ard Biesheuvel 2015-11-18 15:59:04 +00:00 committed by abiesheuvel
parent 2ea66ed9f9
commit 07070ecc76
2 changed files with 16 additions and 3 deletions
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6
ArmPkg/Include/Chipset/ArmV7Mmu.h
View File

@ -29,10 +29,10 @@
#define TTBR_RGN_INNER_WRITE_THROUGH BIT0 #define TTBR_RGN_INNER_WRITE_THROUGH BIT0
#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6) #define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)
#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH ) #define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)
#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC ) #define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)
#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE ) #define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )
#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC ) #define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)
#define TRANSLATION_TABLE_SECTION_COUNT 4096 #define TRANSLATION_TABLE_SECTION_COUNT 4096

13
ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
View File

@ -265,6 +265,19 @@ ArmConfigureMmu (
return RETURN_UNSUPPORTED; return RETURN_UNSUPPORTED;
} }
if (TTBRAttributes & TTBR_SHAREABLE) {
//
// Unlike the S bit in the short descriptors, which implies inner shareable
// on an implementation that supports two levels, the meaning of the S bit
// in the TTBR depends on the NOS bit, which defaults to Outer Shareable.
// However, we should only set this bit after we have confirmed that the
// implementation supports multiple levels, or else the NOS bit is UNK/SBZP
//
if (((ArmReadIdMmfr0 () >> 12) & 0xf) != 0) {
TTBRAttributes |= TTBR_NOT_OUTER_SHAREABLE;
}
}
ArmCleanInvalidateDataCache (); ArmCleanInvalidateDataCache ();
ArmInvalidateInstructionCache (); ArmInvalidateInstructionCache ();