From 9c0dc0b01a79666c3ba8aa0c69ad92131aada113 Mon Sep 17 00:00:00 2001 From: Ruiyu Ni Date: Mon, 9 May 2016 11:21:25 +0800 Subject: [PATCH 01/26] MdeModulePkg/PciSioSerialDxe: Do not flush the UART The patch aligns to the IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe driver not flush the UART in Reset() and SetAttributes() function. It was found the flush causes hang on certain PCI serial devices. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Reviewed-by: Eric Jin --- .../Bus/Pci/PciSioSerialDxe/SerialIo.c | 27 +------------------ 1 file changed, 1 insertion(+), 26 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c index f1870f3a1b..cce61d7a23 100644 --- a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c +++ b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c @@ -1,7 +1,7 @@ /** @file SerialIo implementation for PCI or SIO UARTs. -Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -442,27 +442,6 @@ SerialReceiveTransmit ( return EFI_SUCCESS; } -/** - Flush the serial hardware transmit FIFO and shift register. - - @param SerialDevice The device to flush. -**/ -VOID -SerialFlushTransmitFifo ( - SERIAL_DEV *SerialDevice - ) -{ - SERIAL_PORT_LSR Lsr; - - // - // Wait for the serial port to be ready, to make sure both the transmit FIFO - // and shift register empty. - // - do { - Lsr.Data = READ_LSR (SerialDevice); - } while (Lsr.Bits.Temt == 0); -} - // // Interface Functions // @@ -503,8 +482,6 @@ SerialReset ( Tpl = gBS->RaiseTPL (TPL_NOTIFY); - SerialFlushTransmitFifo (SerialDevice); - // // Make sure DLAB is 0. // @@ -683,8 +660,6 @@ SerialSetAttributes ( Tpl = gBS->RaiseTPL (TPL_NOTIFY); - SerialFlushTransmitFifo (SerialDevice); - // // Put serial port on Divisor Latch Mode // From e55f8c73b6255b353c021ab59017a364dd527a86 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 19 Apr 2016 16:12:10 +0200 Subject: [PATCH 02/26] ArmPkg/ArmDmaLib: deal with NULL return value of UncachedAllocatePages () The allocation function UncachedAllocatePages () may return NULL, in which case our implementation of DmaAllocateBuffer () should return EFI_OUT_OF_RESOURCES rather than silently ignoring the NULL value and returning EFI_SUCCESS. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmDmaLib/ArmDmaLib.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c index 54a49a18d3..1e6b288b10 100644 --- a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c +++ b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c @@ -216,6 +216,8 @@ DmaAllocateBuffer ( OUT VOID **HostAddress ) { + VOID *Allocation; + if (HostAddress == NULL) { return EFI_INVALID_PARAMETER; } @@ -226,13 +228,19 @@ DmaAllocateBuffer ( // We used uncached memory to keep coherency // if (MemoryType == EfiBootServicesData) { - *HostAddress = UncachedAllocatePages (Pages); + Allocation = UncachedAllocatePages (Pages); } else if (MemoryType == EfiRuntimeServicesData) { - *HostAddress = UncachedAllocateRuntimePages (Pages); + Allocation = UncachedAllocateRuntimePages (Pages); } else { return EFI_INVALID_PARAMETER; } + if (Allocation == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + *HostAddress = Allocation; + return EFI_SUCCESS; } From 80e5a33da1fcbe54cbcc178f1880e80e297d5fd4 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 19 Apr 2016 16:16:37 +0200 Subject: [PATCH 03/26] ArmPkg/ArmDmaLib: consistently use 'gCacheAlignment - 1' as alignment mask We manage to use both an AND operation with 'gCacheAlignment - 1' and a modulo operation with 'gCacheAlignment' in the same compound if statement. Since gCacheAlignment is a global of which the compiler cannot guarantee that it is a power of two, simply use the AND version in both cases. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmDmaLib/ArmDmaLib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c index 1e6b288b10..66f3469eb1 100644 --- a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c +++ b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c @@ -93,7 +93,7 @@ DmaMap ( *Mapping = Map; if ((((UINTN)HostAddress & (gCacheAlignment - 1)) != 0) || - ((*NumberOfBytes % gCacheAlignment) != 0)) { + ((*NumberOfBytes & (gCacheAlignment - 1)) != 0)) { // Get the cacheability of the region Status = gDS->GetMemorySpaceDescriptor (*DeviceAddress, &GcdDescriptor); From 885d57ef091fd58916163e79ee694ddaf8fcc25e Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 19 Apr 2016 16:19:02 +0200 Subject: [PATCH 04/26] ArmPkg/ArmDmaLib: interpret GCD attributes as a bit field Comparing a GCD attribute field directly against EFI_MEMORY_UC and EFI_MEMORY_WT is incorrect, since it may have other bits set as well which are not related to the cacheability of the region. So instead, test explicitly against the flags EFI_MEMORY_WB and EFI_MEMORY_WT, which must be set if the region may be mapped with cacheable attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmDmaLib/ArmDmaLib.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c index 66f3469eb1..2144699c08 100644 --- a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c +++ b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c @@ -102,9 +102,7 @@ DmaMap ( } // If the mapped buffer is not an uncached buffer - if ( (GcdDescriptor.Attributes != EFI_MEMORY_WC) && - (GcdDescriptor.Attributes != EFI_MEMORY_UC) ) - { + if ((GcdDescriptor.Attributes & (EFI_MEMORY_WB | EFI_MEMORY_WT)) != 0) { // // If the buffer does not fill entire cache lines we must double buffer into // uncached memory. Device (PCI) address becomes uncached page. From a24f7d6680dd71616b0fcb9c5a65263fce1722be Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 19 Apr 2016 16:26:00 +0200 Subject: [PATCH 05/26] ArmPkg/ArmDmaLib: reject consistent DMA mappings of cached memory DmaMap () operations of type MapOperationBusMasterCommonBuffer should return a mapping that is coherent between the CPU and the device. For this reason, the API only allows DmaMap () to be called with this operation type if the memory to be mapped was allocated by DmaAllocateBuffer (), which in this implementation guarantees the coherency by using uncached mappings on the CPU side. This means that, if we encounter a cached mapping in DmaMap () with this operation type, the code is either broken, or someone is violating the API, but simply proceeding with a double buffer makes no sense at all, and can only cause problems. So instead, actively reject this operation type for cached memory mappings. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmDmaLib/ArmDmaLib.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c index 2144699c08..0e6fdce8ab 100644 --- a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c +++ b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c @@ -103,6 +103,18 @@ DmaMap ( // If the mapped buffer is not an uncached buffer if ((GcdDescriptor.Attributes & (EFI_MEMORY_WB | EFI_MEMORY_WT)) != 0) { + // + // Operations of type MapOperationBusMasterCommonBuffer are only allowed + // on uncached buffers. + // + if (Operation == MapOperationBusMasterCommonBuffer) { + DEBUG ((EFI_D_ERROR, + "%a: Operation type 'MapOperationBusMasterCommonBuffer' is only supported\n" + "on memory regions that were allocated using DmaAllocateBuffer ()\n", + __FUNCTION__)); + return EFI_UNSUPPORTED; + } + // // If the buffer does not fill entire cache lines we must double buffer into // uncached memory. Device (PCI) address becomes uncached page. @@ -113,7 +125,7 @@ DmaMap ( return Status; } - if ((Operation == MapOperationBusMasterRead) || (Operation == MapOperationBusMasterCommonBuffer)) { + if (Operation == MapOperationBusMasterRead) { CopyMem (Buffer, HostAddress, *NumberOfBytes); } @@ -151,6 +163,8 @@ DmaMap ( @retval EFI_SUCCESS The range was unmapped. @retval EFI_DEVICE_ERROR The data was not committed to the target system memory. + @retval EFI_INVALID_PARAMETER An inconsistency was detected between the mapping type + and the DoubleBuffer field **/ EFI_STATUS @@ -160,6 +174,7 @@ DmaUnmap ( ) { MAP_INFO_INSTANCE *Map; + EFI_STATUS Status; if (Mapping == NULL) { ASSERT (FALSE); @@ -168,8 +183,13 @@ DmaUnmap ( Map = (MAP_INFO_INSTANCE *)Mapping; + Status = EFI_SUCCESS; if (Map->DoubleBuffer) { - if ((Map->Operation == MapOperationBusMasterWrite) || (Map->Operation == MapOperationBusMasterCommonBuffer)) { + ASSERT (Map->Operation != MapOperationBusMasterCommonBuffer); + + if (Map->Operation == MapOperationBusMasterCommonBuffer) { + Status = EFI_INVALID_PARAMETER; + } else if (Map->Operation == MapOperationBusMasterWrite) { CopyMem ((VOID *)(UINTN)Map->HostAddress, (VOID *)(UINTN)Map->DeviceAddress, Map->NumberOfBytes); } @@ -186,7 +206,7 @@ DmaUnmap ( FreePool (Map); - return EFI_SUCCESS; + return Status; } /** From 32e5fb76e5692911d5176ac4dc9cedafbe7fa5c9 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 19 Apr 2016 16:37:04 +0200 Subject: [PATCH 06/26] ArmPkg/ArmDmaLib: do not remap arbitrary memory regions as uncached In the DmaMap () operation, if the region to be mapped happens to be aligned to the Cache Writeback Granule (CWG) (whose value is typically 64 or 128 bytes and 2 KB maximum), we remap the memory as uncached. Since remapping memory occurs at page granularity, while the buffer and the CWG may be much smaller, there is no telling what other memory we affect by doing this, especially since the operation is not reverted in DmaUnmap(). So remove the remapping call. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmDmaLib/ArmDmaLib.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c index 0e6fdce8ab..f5788b3756 100644 --- a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c +++ b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c @@ -138,12 +138,6 @@ DmaMap ( // Flush the Data Cache (should not have any effect if the memory region is uncached) gCpu->FlushDataCache (gCpu, *DeviceAddress, *NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate); - - if ((Operation == MapOperationBusMasterRead) || (Operation == MapOperationBusMasterCommonBuffer)) { - // In case the buffer is used for instance to send command to a PCI controller, we must ensure the memory is uncached - Status = gDS->SetMemorySpaceAttributes (*DeviceAddress & ~(BASE_4KB - 1), ALIGN_VALUE (*NumberOfBytes, BASE_4KB), EFI_MEMORY_WC); - ASSERT_EFI_ERROR (Status); - } } Map->HostAddress = (UINTN)HostAddress; From b64e44cc098ffd03ccbf1a635ae405ae98971419 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Wed, 20 Apr 2016 10:29:21 +0200 Subject: [PATCH 07/26] ArmPkg/ArmDmaLib: assert that consistent mappings are uncached DmaMap () only allows uncached mappings to be used for creating consistent mappings with operation type MapOperationBusMasterCommonBuffer. However, if the buffer passed to DmaMap () happens to be aligned to the CWG, there is no need for a bounce buffer, and we perform the cache maintenance directly without ever checking if the memory attributes of the buffer adhere to the API. So add some debug code that asserts that the operation type and the memory attributes are consistent. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Tested-by: Ryan Harkin Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmDmaLib/ArmDmaLib.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c index f5788b3756..d48d6ff6db 100644 --- a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c +++ b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c @@ -136,6 +136,23 @@ DmaMap ( } else { Map->DoubleBuffer = FALSE; + DEBUG_CODE_BEGIN (); + + // + // The operation type check above only executes if the buffer happens to be + // misaligned with respect to CWG, but even if it is aligned, we should not + // allow arbitrary buffers to be used for creating consistent mappings. + // So duplicate the check here when running in DEBUG mode, just to assert + // that we are not trying to create a consistent mapping for cached memory. + // + Status = gDS->GetMemorySpaceDescriptor (*DeviceAddress, &GcdDescriptor); + ASSERT_EFI_ERROR(Status); + + ASSERT (Operation != MapOperationBusMasterCommonBuffer || + (GcdDescriptor.Attributes & (EFI_MEMORY_WB | EFI_MEMORY_WT)) == 0); + + DEBUG_CODE_END (); + // Flush the Data Cache (should not have any effect if the memory region is uncached) gCpu->FlushDataCache (gCpu, *DeviceAddress, *NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate); } From d1ec2b2f78b752b9dfc06843f994cbfad134ea63 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Wed, 20 Apr 2016 10:07:20 +0200 Subject: [PATCH 08/26] ArmPkg/AArch64Mmu: don't let table entries inherit XN permission bits When we split a block entry into a table entry, the UXN/PXN/XN permission attributes are inherited both by the new table entry and by the new block entries at the next level down. Unlike the NS bit, which only affects the next level of lookup, the XN table bits supersede the permissions of the final translation, and setting the permissions at multiple levels is not only redundant, it also prevents us from lifting XN restrictions on a subregion of the original block entry by simply clearing the appropriate bits at the lowest level. So drop the code that sets the UXN/PXN/XN bits on the table entries. Reported-by: "Oliyil Kunnil, Vishal" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c index 48ca827184..cf9b7222b4 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c @@ -306,13 +306,6 @@ GetBlockEntryListFromAddress ( // Convert the block entry attributes into Table descriptor attributes TableAttributes = TT_TABLE_AP_NO_PERMISSION; - if (Attributes & TT_PXN_MASK) { - TableAttributes = TT_TABLE_PXN; - } - // XN maps to UXN in the EL1&0 translation regime - if (Attributes & TT_XN_MASK) { - TableAttributes = TT_TABLE_XN; - } if (Attributes & TT_NS) { TableAttributes = TT_TABLE_NS; } From 28f52b9fae9feba369ff0d773e0b0e610c0aa6f8 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Fri, 6 May 2016 18:19:06 +0100 Subject: [PATCH 09/26] Revert "EmbeddedPkg/Lan9118Dxe: use MemoryFence" Commit a4626006bbf86113 ("EmbeddedPkg/Lan9118Dxe: use MemoryFence") replaced some stalls with memory fences, on the presumption that these were erroneously being used to order memory accesses. However, this was not the case. LAN9118 devices require a timing delay between state-changing reads/writes and subsequent reads, as updates to the register file are asynchronous and the effects of state-changes are not immediately visible to subsequent reads. This delay cannot be ensured through the use of memory barriers, which only enforce observable ordering, and not timing. Thus, converting these stalls to memory fences was erroneous, and may result in stale values being read. This reverts commit a4626006bbf86113453aeb7920895e66cdd04737. Cc: Leif Lindholm Cc: Ryan Harkin Signed-off-by: Mark Rutland Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Ard Biesheuvel --- EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c | 9 +++-- .../Drivers/Lan9118Dxe/Lan9118DxeUtil.c | 40 +++++++++---------- 2 files changed, 23 insertions(+), 26 deletions(-) diff --git a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c index d0bf7beefe..50644e7b7d 100644 --- a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c +++ b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c @@ -307,7 +307,8 @@ SnpInitialize ( // Write the current configuration to the register MmioWrite32 (LAN9118_PMT_CTRL, PmConf); - MemoryFence(); + gBS->Stall (LAN9118_STALL); + gBS->Stall (LAN9118_STALL); // Configure GPIO and HW Status = ConfigureHardware (HW_CONF_USE_LEDS, Snp); @@ -430,7 +431,7 @@ SnpReset ( // Write the current configuration to the register MmioWrite32 (LAN9118_PMT_CTRL, PmConf); - MemoryFence(); + gBS->Stall (LAN9118_STALL); // Reactivate the LEDs Status = ConfigureHardware (HW_CONF_USE_LEDS, Snp); @@ -445,7 +446,7 @@ SnpReset ( HwConf |= HW_CFG_TX_FIFO_SIZE(gTxBuffer); // assign size chosen in SnpInitialize MmioWrite32 (LAN9118_HW_CFG, HwConf); // Write the conf - MemoryFence(); + gBS->Stall (LAN9118_STALL); } // Enable the receiver and transmitter and clear their contents @@ -700,7 +701,7 @@ SnpReceiveFilters ( // Write the options to the MAC_CSR // IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCSRValue); - MemoryFence(); + gBS->Stall (LAN9118_STALL); // // If we have to retrieve something, start packet reception. diff --git a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c index 3ef98ef901..bd20eebd04 100644 --- a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c +++ b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c @@ -236,7 +236,7 @@ IndirectEEPROMRead32 ( // Write to Eeprom command register MmioWrite32 (LAN9118_E2P_CMD, EepromCmd); - MemoryFence(); + gBS->Stall (LAN9118_STALL); // Wait until operation has completed while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); @@ -284,7 +284,7 @@ IndirectEEPROMWrite32 ( // Write to Eeprom command register MmioWrite32 (LAN9118_E2P_CMD, EepromCmd); - MemoryFence(); + gBS->Stall (LAN9118_STALL); // Wait until operation has completed while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); @@ -362,14 +362,13 @@ Lan9118Initialize ( if (((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) { DEBUG ((DEBUG_NET, "Waking from reduced power state.\n")); MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF); - MemoryFence(); + gBS->Stall (LAN9118_STALL); } // Check that device is active Retries = 20; while ((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_READY) == 0 && --Retries) { gBS->Stall (LAN9118_STALL); - MemoryFence(); } if (!Retries) { return EFI_TIMEOUT; @@ -379,7 +378,6 @@ Lan9118Initialize ( Retries = 20; while ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY) && --Retries){ gBS->Stall (LAN9118_STALL); - MemoryFence(); } if (!Retries) { return EFI_TIMEOUT; @@ -449,12 +447,11 @@ SoftReset ( // Write the configuration MmioWrite32 (LAN9118_HW_CFG, HwConf); - MemoryFence(); + gBS->Stall (LAN9118_STALL); // Wait for reset to complete while (MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) { - MemoryFence(); gBS->Stall (LAN9118_STALL); ResetTime += 1; @@ -503,7 +500,7 @@ PhySoftReset ( // Wait for completion while (MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PHY_RST) { - MemoryFence(); + gBS->Stall (LAN9118_STALL); } // PHY Basic Control Register reset } else if (Flags & PHY_RESET_BCR) { @@ -511,7 +508,7 @@ PhySoftReset ( // Wait for completion while (IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL) & PHYCR_RESET) { - MemoryFence(); + gBS->Stall (LAN9118_STALL); } } @@ -545,7 +542,7 @@ ConfigureHardware ( // Write the configuration MmioWrite32 (LAN9118_GPIO_CFG, GpioConf); - MemoryFence(); + gBS->Stall (LAN9118_STALL); } return EFI_SUCCESS; @@ -588,7 +585,6 @@ AutoNegotiate ( // Wait until it is up or until Time Out Retries = FixedPcdGet32 (PcdLan9118DefaultNegotiationTimeout) / LAN9118_STALL; while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_LINK_STS) == 0) { - MemoryFence(); gBS->Stall (LAN9118_STALL); Retries--; if (!Retries) { @@ -675,7 +671,7 @@ StopTx ( TxCfg = MmioRead32 (LAN9118_TX_CFG); TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP; MmioWrite32 (LAN9118_TX_CFG, TxCfg); - MemoryFence(); + gBS->Stall (LAN9118_STALL); } // Check if already stopped @@ -694,7 +690,7 @@ StopTx ( if (TxCfg & TXCFG_TX_ON) { TxCfg |= TXCFG_STOP_TX; MmioWrite32 (LAN9118_TX_CFG, TxCfg); - MemoryFence(); + gBS->Stall (LAN9118_STALL); // Wait for Tx to finish transmitting while (MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX); @@ -729,7 +725,7 @@ StopRx ( RxCfg = MmioRead32 (LAN9118_RX_CFG); RxCfg |= RXCFG_RX_DUMP; MmioWrite32 (LAN9118_RX_CFG, RxCfg); - MemoryFence(); + gBS->Stall (LAN9118_STALL); while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP); } @@ -755,28 +751,28 @@ StartTx ( TxCfg = MmioRead32 (LAN9118_TX_CFG); TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP; MmioWrite32 (LAN9118_TX_CFG, TxCfg); - MemoryFence(); + gBS->Stall (LAN9118_STALL); } // Check if tx was started from MAC and enable if not if (Flags & START_TX_MAC) { MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR); - MemoryFence(); + gBS->Stall (LAN9118_STALL); if ((MacCsr & MACCR_TX_EN) == 0) { MacCsr |= MACCR_TX_EN; IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr); - MemoryFence(); + gBS->Stall (LAN9118_STALL); } } // Check if tx was started from TX_CFG and enable if not if (Flags & START_TX_CFG) { TxCfg = MmioRead32 (LAN9118_TX_CFG); - MemoryFence(); + gBS->Stall (LAN9118_STALL); if ((TxCfg & TXCFG_TX_ON) == 0) { TxCfg |= TXCFG_TX_ON; MmioWrite32 (LAN9118_TX_CFG, TxCfg); - MemoryFence(); + gBS->Stall (LAN9118_STALL); } } @@ -806,14 +802,14 @@ StartRx ( RxCfg = MmioRead32 (LAN9118_RX_CFG); RxCfg |= RXCFG_RX_DUMP; MmioWrite32 (LAN9118_RX_CFG, RxCfg); - MemoryFence(); + gBS->Stall (LAN9118_STALL); while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP); } MacCsr |= MACCR_RX_EN; IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr); - MemoryFence(); + gBS->Stall (LAN9118_STALL); } return EFI_SUCCESS; @@ -1003,7 +999,7 @@ ChangeFifoAllocation ( HwConf &= ~(0xF0000); HwConf |= ((TxFifoOption & 0xF) << 16); MmioWrite32 (LAN9118_HW_CFG, HwConf); - MemoryFence(); + gBS->Stall (LAN9118_STALL); return EFI_SUCCESS; } From 73683a2464e2f81b7b9dfb9b84b537290235bbe1 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Fri, 6 May 2016 18:19:07 +0100 Subject: [PATCH 10/26] EmbeddedPkg/Lan9118Dxe: add LAN9118 MMIO wrappers As described in the LAN9118 datasheet, delays are necessary after some reads and writes in order to ensure subsequent reads do not see stale data. This patch adds helpers to provide these delays automatically, by performing dummy reads of the BYTE_TEST register (as recommended in the LAN9118 datasheet). This approach allows the device register file itself to provide the required delay, avoiding issues with early write acknowledgement, or re-ordering of MMIO accesses aganist other instructions (e.g. the delay loop). Cc: Leif Lindholm Cc: Ryan Harkin Signed-off-by: Mark Rutland Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Ard Biesheuvel --- EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h | 71 +++++++++++++++++++ .../Drivers/Lan9118Dxe/Lan9118DxeUtil.c | 48 +++++++++++++ .../Drivers/Lan9118Dxe/Lan9118DxeUtil.h | 17 +++++ 3 files changed, 136 insertions(+) diff --git a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h index 9e89d27459..11895849a4 100644 --- a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h +++ b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h @@ -57,6 +57,77 @@ #define LAN9118_E2P_CMD (0x000000B0 + LAN9118_BA) // EEPROM Command #define LAN9118_E2P_DATA (0x000000B4 + LAN9118_BA) // EEPROM Data +/* + * Required delays following write cycles (number of BYTE_TEST reads) + * Taken from Table 6.1 in Revision 1.5 (07-11-08) of the LAN9118 datasheet. + * Where no delay listed, 0 has been assumed. + */ +#define LAN9118_RX_DATA_WR_DELAY 0 +#define LAN9118_RX_STATUS_WR_DELAY 0 +#define LAN9118_RX_STATUS_PEEK_WR_DELAY 0 +#define LAN9118_TX_DATA_WR_DELAY 0 +#define LAN9118_TX_STATUS_WR_DELAY 0 +#define LAN9118_TX_STATUS_PEEK_WR_DELAY 0 +#define LAN9118_ID_REV_WR_DELAY 0 +#define LAN9118_IRQ_CFG_WR_DELAY 3 +#define LAN9118_INT_STS_WR_DELAY 2 +#define LAN9118_INT_EN_WR_DELAY 1 +#define LAN9118_BYTE_TEST_WR_DELAY 0 +#define LAN9118_FIFO_INT_WR_DELAY 1 +#define LAN9118_RX_CFG_WR_DELAY 1 +#define LAN9118_TX_CFG_WR_DELAY 1 +#define LAN9118_HW_CFG_WR_DELAY 1 +#define LAN9118_RX_DP_CTL_WR_DELAY 1 +#define LAN9118_RX_FIFO_INF_WR_DELAY 0 +#define LAN9118_TX_FIFO_INF_WR_DELAY 3 +#define LAN9118_PMT_CTRL_WR_DELAY 7 +#define LAN9118_GPIO_CFG_WR_DELAY 1 +#define LAN9118_GPT_CFG_WR_DELAY 1 +#define LAN9118_GPT_CNT_WR_DELAY 3 +#define LAN9118_WORD_SWAP_WR_DELAY 1 +#define LAN9118_FREE_RUN_WR_DELAY 4 +#define LAN9118_RX_DROP_WR_DELAY 0 +#define LAN9118_MAC_CSR_CMD_WR_DELAY 1 +#define LAN9118_MAC_CSR_DATA_WR_DELAY 1 +#define LAN9118_AFC_CFG_WR_DELAY 1 +#define LAN9118_E2P_CMD_WR_DELAY 1 +#define LAN9118_E2P_DATA_WR_DELAY 1 + +/* + * Required delays following read cycles (number of BYTE_TEST reads) + * Taken from Table 6.2 in Revision 1.5 (07-11-08) of the LAN9118 datasheet. + * Where no delay listed, 0 has been assumed. + */ +#define LAN9118_RX_DATA_RD_DELAY 3 +#define LAN9118_RX_STATUS_RD_DELAY 3 +#define LAN9118_RX_STATUS_PEEK_RD_DELAY 0 +#define LAN9118_TX_DATA_RD_DELAY 0 +#define LAN9118_TX_STATUS_RD_DELAY 3 +#define LAN9118_TX_STATUS_PEEK_RD_DELAY 0 +#define LAN9118_ID_REV_RD_DELAY 0 +#define LAN9118_IRQ_CFG_RD_DELAY 0 +#define LAN9118_INT_STS_RD_DELAY 0 +#define LAN9118_INT_EN_RD_DELAY 0 +#define LAN9118_BYTE_TEST_RD_DELAY 0 +#define LAN9118_FIFO_INT_RD_DELAY 0 +#define LAN9118_RX_CFG_RD_DELAY 0 +#define LAN9118_TX_CFG_RD_DELAY 0 +#define LAN9118_HW_CFG_RD_DELAY 0 +#define LAN9118_RX_DP_CTL_RD_DELAY 0 +#define LAN9118_RX_FIFO_INF_RD_DELAY 0 +#define LAN9118_TX_FIFO_INF_RD_DELAY 0 +#define LAN9118_PMT_CTRL_RD_DELAY 0 +#define LAN9118_GPIO_CFG_RD_DELAY 0 +#define LAN9118_GPT_CFG_RD_DELAY 0 +#define LAN9118_GPT_CNT_RD_DELAY 0 +#define LAN9118_WORD_SWAP_RD_DELAY 0 +#define LAN9118_FREE_RUN_RD_DELAY 0 +#define LAN9118_RX_DROP_RD_DELAY 4 +#define LAN9118_MAC_CSR_CMD_RD_DELAY 0 +#define LAN9118_MAC_CSR_DATA_RD_DELAY 0 +#define LAN9118_AFC_CFG_RD_DELAY 0 +#define LAN9118_E2P_CMD_RD_DELAY 0 +#define LAN9118_E2P_DATA_RD_DELAY 0 // Receiver Status bits #define RXSTATUS_CRC_ERROR BIT1 // Cyclic Redundancy Check Error diff --git a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c index bd20eebd04..002ea203ae 100644 --- a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c +++ b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c @@ -115,6 +115,54 @@ IndirectMACRead32 ( return MmioRead32 (LAN9118_MAC_CSR_DATA); } +/* + * LAN9118 chips have special restrictions on some back-to-back Write/Read or + * Read/Read pairs of accesses. After a read or write that changes the state of + * the device, there is a period in which stale values may be returned in + * response to a read. This period is dependent on the registers accessed. + * + * We must delay prior reads by this period. This can either be achieved by + * timer-based delays, or by performing dummy reads of the BYTE_TEST register, + * for which the recommended number of reads is described in the LAN9118 data + * sheet. This is required in addition to any memory barriers. + * + * This function performs a number of dummy reads of the BYTE_TEST register, as + * a building block for the above. + */ +VOID +WaitDummyReads ( + UINTN Count + ) +{ + while (Count--) + MmioRead32(LAN9118_BYTE_TEST); +} + +UINT32 +Lan9118RawMmioRead32( + UINTN Address, + UINTN Delay + ) +{ + UINT32 Value; + + Value = MmioRead32(Address); + WaitDummyReads(Delay); + return Value; +} + +UINT32 +Lan9118RawMmioWrite32( + UINTN Address, + UINT32 Value, + UINTN Delay + ) +{ + MmioWrite32(Address, Value); + WaitDummyReads(Delay); + return Value; +} + // Function to write to MAC indirect registers UINT32 IndirectMACWrite32 ( diff --git a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.h b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.h index 424bdc5a85..1a9a940082 100644 --- a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.h +++ b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.h @@ -38,6 +38,23 @@ GenEtherCrc32 ( IN UINT32 AddrLen ); +UINT32 +Lan9118RawMmioRead32( + UINTN Address, + UINTN Delay + ); +#define Lan9118MmioRead32(a) \ + Lan9118RawMmioRead32(a, a ## _RD_DELAY) + +UINT32 +Lan9118RawMmioWrite32( + UINTN Address, + UINT32 Value, + UINTN Delay + ); +#define Lan9118MmioWrite32(a, v) \ + Lan9118RawMmioWrite32(a, v, a ## _WR_DELAY) + /* ------------------ MAC CSR Access ------------------- */ // Read from MAC indirect registers From e68449c9992fdb4d04c14b3db45393e358a618a6 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Fri, 6 May 2016 18:19:08 +0100 Subject: [PATCH 11/26] EmbeddedPkg/Lan9118Dxe: Use LAN9118 MMIO wrappers Migrate the existing code to use the new LAN9118 MMIO wrappers, ensuring that timing requirements are respected. The newly redundant stalls will be removed in a subsequent patch. Cc: Leif Lindholm Cc: Ryan Harkin Signed-off-by: Mark Rutland Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Ard Biesheuvel --- EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c | 78 +++++------ EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h | 4 +- .../Drivers/Lan9118Dxe/Lan9118DxeUtil.c | 132 +++++++++--------- 3 files changed, 107 insertions(+), 107 deletions(-) diff --git a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c index 50644e7b7d..bef34c2e9c 100644 --- a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c +++ b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c @@ -297,7 +297,7 @@ SnpInitialize ( } // Read the PM register - PmConf = MmioRead32 (LAN9118_PMT_CTRL); + PmConf = Lan9118MmioRead32 (LAN9118_PMT_CTRL); // MPTCTRL_WOL_EN: Allow Wake-On-Lan to detect wake up frames or magic packets // MPTCTRL_ED_EN: Allow energy detection to allow lowest power consumption mode @@ -306,7 +306,7 @@ SnpInitialize ( PmConf |= (MPTCTRL_WOL_EN | MPTCTRL_ED_EN | MPTCTRL_PME_EN); // Write the current configuration to the register - MmioWrite32 (LAN9118_PMT_CTRL, PmConf); + Lan9118MmioWrite32 (LAN9118_PMT_CTRL, PmConf); gBS->Stall (LAN9118_STALL); gBS->Stall (LAN9118_STALL); @@ -359,7 +359,7 @@ SnpInitialize ( } // Now acknowledge all interrupts - MmioWrite32 (LAN9118_INT_STS, ~0); + Lan9118MmioWrite32 (LAN9118_INT_STS, ~0); // Declare the driver as initialized Snp->Mode->State = EfiSimpleNetworkInitialized; @@ -422,7 +422,7 @@ SnpReset ( } // Read the PM register - PmConf = MmioRead32 (LAN9118_PMT_CTRL); + PmConf = Lan9118MmioRead32 (LAN9118_PMT_CTRL); // MPTCTRL_WOL_EN: Allow Wake-On-Lan to detect wake up frames or magic packets // MPTCTRL_ED_EN: Allow energy detection to allow lowest power consumption mode @@ -430,7 +430,7 @@ SnpReset ( PmConf |= (MPTCTRL_WOL_EN | MPTCTRL_ED_EN | MPTCTRL_PME_EN); // Write the current configuration to the register - MmioWrite32 (LAN9118_PMT_CTRL, PmConf); + Lan9118MmioWrite32 (LAN9118_PMT_CTRL, PmConf); gBS->Stall (LAN9118_STALL); // Reactivate the LEDs @@ -441,11 +441,11 @@ SnpReset ( // Check that a buffer size was specified in SnpInitialize if (gTxBuffer != 0) { - HwConf = MmioRead32 (LAN9118_HW_CFG); // Read the HW register + HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG); // Read the HW register HwConf &= ~HW_CFG_TX_FIFO_SIZE_MASK; // Clear buffer bits first HwConf |= HW_CFG_TX_FIFO_SIZE(gTxBuffer); // assign size chosen in SnpInitialize - MmioWrite32 (LAN9118_HW_CFG, HwConf); // Write the conf + Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); // Write the conf gBS->Stall (LAN9118_STALL); } @@ -454,7 +454,7 @@ SnpReset ( StartTx (START_TX_MAC | START_TX_CFG | START_TX_CLEAR, Snp); // Now acknowledge all interrupts - MmioWrite32 (LAN9118_INT_STS, ~0); + Lan9118MmioWrite32 (LAN9118_INT_STS, ~0); return EFI_SUCCESS; } @@ -996,12 +996,12 @@ SnpGetStatus ( // consumer of SNP does not call GetStatus.) // TODO will we lose TxStatuses if this happens? Maybe in SnpTransmit we // should check for it and dump the TX Status FIFO. - FifoInt = MmioRead32 (LAN9118_FIFO_INT); + FifoInt = Lan9118MmioRead32 (LAN9118_FIFO_INT); // Clear the TX Status FIFO Overflow if ((FifoInt & INSTS_TXSO) == 0) { FifoInt |= INSTS_TXSO; - MmioWrite32 (LAN9118_FIFO_INT, FifoInt); + Lan9118MmioWrite32 (LAN9118_FIFO_INT, FifoInt); } // Read interrupt status if IrqStat is not NULL @@ -1009,30 +1009,30 @@ SnpGetStatus ( *IrqStat = 0; // Check for receive interrupt - if (MmioRead32 (LAN9118_INT_STS) & INSTS_RSFL) { // Data moved from rx FIFO + if (Lan9118MmioRead32 (LAN9118_INT_STS) & INSTS_RSFL) { // Data moved from rx FIFO *IrqStat |= EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT; - MmioWrite32 (LAN9118_INT_STS,INSTS_RSFL); + Lan9118MmioWrite32 (LAN9118_INT_STS,INSTS_RSFL); } // Check for transmit interrupt - if (MmioRead32 (LAN9118_INT_STS) & INSTS_TSFL) { + if (Lan9118MmioRead32 (LAN9118_INT_STS) & INSTS_TSFL) { *IrqStat |= EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT; - MmioWrite32 (LAN9118_INT_STS,INSTS_TSFL); + Lan9118MmioWrite32 (LAN9118_INT_STS,INSTS_TSFL); } // Check for software interrupt - if (MmioRead32 (LAN9118_INT_STS) & INSTS_SW_INT) { + if (Lan9118MmioRead32 (LAN9118_INT_STS) & INSTS_SW_INT) { *IrqStat |= EFI_SIMPLE_NETWORK_SOFTWARE_INTERRUPT; - MmioWrite32 (LAN9118_INT_STS,INSTS_SW_INT); + Lan9118MmioWrite32 (LAN9118_INT_STS,INSTS_SW_INT); } } // Check Status of transmitted packets // (We ignore TXSTATUS_NO_CA has it might happen in Full Duplex) - NumTxStatusEntries = MmioRead32(LAN9118_TX_FIFO_INF) & TXFIFOINF_TXSUSED_MASK; + NumTxStatusEntries = Lan9118MmioRead32(LAN9118_TX_FIFO_INF) & TXFIFOINF_TXSUSED_MASK; if (NumTxStatusEntries > 0) { - TxStatus = MmioRead32 (LAN9118_TX_STATUS); + TxStatus = Lan9118MmioRead32 (LAN9118_TX_STATUS); PacketTag = TxStatus >> 16; TxStatus = TxStatus & 0xFFFF; if ((TxStatus & TXSTATUS_ES) && (TxStatus != (TXSTATUS_ES | TXSTATUS_NO_CA))) { @@ -1063,7 +1063,7 @@ SnpGetStatus ( } // Check for a TX Error interrupt - Interrupts = MmioRead32 (LAN9118_INT_STS); + Interrupts = Lan9118MmioRead32 (LAN9118_INT_STS); if (Interrupts & INSTS_TXE) { DEBUG ((EFI_D_ERROR, "LAN9118: Transmitter error. Restarting...")); @@ -1221,25 +1221,25 @@ SnpTransmit ( CommandB = TX_CMD_B_PACKET_TAG (PacketTag) | TX_CMD_B_PACKET_LENGTH (BuffSize); // Write the commands first - MmioWrite32 (LAN9118_TX_DATA, CommandA); - MmioWrite32 (LAN9118_TX_DATA, CommandB); + Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandA); + Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandB); // Write the destination address - MmioWrite32 (LAN9118_TX_DATA, + Lan9118MmioWrite32 (LAN9118_TX_DATA, (DstAddr->Addr[0]) | (DstAddr->Addr[1] << 8) | (DstAddr->Addr[2] << 16) | (DstAddr->Addr[3] << 24) ); - MmioWrite32 (LAN9118_TX_DATA, + Lan9118MmioWrite32 (LAN9118_TX_DATA, (DstAddr->Addr[4]) | (DstAddr->Addr[5] << 8) | (SrcAddr->Addr[0] << 16) | // Write the Source Address (SrcAddr->Addr[1] << 24) ); - MmioWrite32 (LAN9118_TX_DATA, + Lan9118MmioWrite32 (LAN9118_TX_DATA, (SrcAddr->Addr[2]) | (SrcAddr->Addr[3] << 8) | (SrcAddr->Addr[4] << 16) | @@ -1247,18 +1247,18 @@ SnpTransmit ( ); // Write the Protocol - MmioWrite32 (LAN9118_TX_DATA, (UINT32)(HTONS (LocalProtocol))); + Lan9118MmioWrite32 (LAN9118_TX_DATA, (UINT32)(HTONS (LocalProtocol))); // Next buffer is the payload CommandA = TX_CMD_A_LAST_SEGMENT | TX_CMD_A_BUFF_SIZE (BuffSize - HdrSize) | TX_CMD_A_COMPLETION_INT | TX_CMD_A_DATA_START_OFFSET (2); // 2 bytes beginning offset // Write the commands - MmioWrite32 (LAN9118_TX_DATA, CommandA); - MmioWrite32 (LAN9118_TX_DATA, CommandB); + Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandA); + Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandB); // Write the payload for (Count = 0; Count < ((BuffSize + 3) >> 2) - 3; Count++) { - MmioWrite32 (LAN9118_TX_DATA, LocalData[Count + 3]); + Lan9118MmioWrite32 (LAN9118_TX_DATA, LocalData[Count + 3]); } } else { // Format pointer @@ -1269,12 +1269,12 @@ SnpTransmit ( CommandB = TX_CMD_B_PACKET_TAG (PacketTag) | TX_CMD_B_PACKET_LENGTH (BuffSize); // Write the commands first - MmioWrite32 (LAN9118_TX_DATA, CommandA); - MmioWrite32 (LAN9118_TX_DATA, CommandB); + Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandA); + Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandB); // Write all the data for (Count = 0; Count < ((BuffSize + 3) >> 2); Count++) { - MmioWrite32 (LAN9118_TX_DATA, LocalData[Count]); + Lan9118MmioWrite32 (LAN9118_TX_DATA, LocalData[Count]); } } @@ -1362,13 +1362,13 @@ SnpReceive ( // explain those errors has been found so far and everything seems to // work perfectly when they are just ignored. // - IntSts = MmioRead32 (LAN9118_INT_STS); + IntSts = Lan9118MmioRead32 (LAN9118_INT_STS); if ((IntSts & INSTS_RXE) && (!(IntSts & INSTS_RSFF))) { - MmioWrite32 (LAN9118_INT_STS, INSTS_RXE); + Lan9118MmioWrite32 (LAN9118_INT_STS, INSTS_RXE); } // Count dropped frames - DroppedFrames = MmioRead32 (LAN9118_RX_DROP); + DroppedFrames = Lan9118MmioRead32 (LAN9118_RX_DROP); LanDriver->Stats.RxDroppedFrames += DroppedFrames; NumPackets = RxStatusUsedSpace (0, Snp) / 4; @@ -1377,7 +1377,7 @@ SnpReceive ( } // Read Rx Status (only if not empty) - RxFifoStatus = MmioRead32 (LAN9118_RX_STATUS); + RxFifoStatus = Lan9118MmioRead32 (LAN9118_RX_STATUS); LanDriver->Stats.RxTotalFrames += 1; // First check for errors @@ -1450,13 +1450,13 @@ SnpReceive ( // Set the amount of data to be transfered out of FIFO for THIS packet // This can be used to trigger an interrupt, and status can be checked - RxCfgValue = MmioRead32 (LAN9118_RX_CFG); + RxCfgValue = Lan9118MmioRead32 (LAN9118_RX_CFG); RxCfgValue &= ~(RXCFG_RX_DMA_CNT_MASK); RxCfgValue |= RXCFG_RX_DMA_CNT (ReadLimit); // Set end alignment to 4-bytes RxCfgValue &= ~(RXCFG_RX_END_ALIGN_MASK); - MmioWrite32 (LAN9118_RX_CFG, RxCfgValue); + Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfgValue); // Update buffer size *BuffSize = PLength; // -4 bytes may be needed: Received in buffer as @@ -1471,7 +1471,7 @@ SnpReceive ( // Read Rx Packet for (Count = 0; Count < ReadLimit; Count++) { - RawData[Count] = MmioRead32 (LAN9118_RX_DATA); + RawData[Count] = Lan9118MmioRead32 (LAN9118_RX_DATA); } // Get the destination address @@ -1502,7 +1502,7 @@ SnpReceive ( } // Check for Rx errors (worst possible error) - if (MmioRead32 (LAN9118_INT_STS) & INSTS_RXE) { + if (Lan9118MmioRead32 (LAN9118_INT_STS) & INSTS_RXE) { DEBUG ((EFI_D_WARN, "Warning: Receiver Error. Restarting...\n")); // Software reset, the RXE interrupt is cleared by the reset. diff --git a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h index 11895849a4..e44e2950a5 100644 --- a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h +++ b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h @@ -158,8 +158,8 @@ #define TXSTATUS_PTAG_MASK (0xFFFF0000) // Mask for Unique ID of packets (So we know who the packets are for) // ID_REV register bits -#define IDREV_ID ((MmioRead32(LAN9118_ID_REV) & 0xFFFF0000) >> 16) -#define IDREV_REV (MmioRead32(LAN9118_ID_REV) & 0x0000FFFF) +#define IDREV_ID ((Lan9118MmioRead32(LAN9118_ID_REV) & 0xFFFF0000) >> 16) +#define IDREV_REV (Lan9118MmioRead32(LAN9118_ID_REV) & 0x0000FFFF) // Interrupt Config Register bits #define IRQCFG_IRQ_TYPE BIT0 // IRQ Buffer type diff --git a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c index 002ea203ae..61f11b6e27 100644 --- a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c +++ b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c @@ -98,7 +98,7 @@ IndirectMACRead32 ( ASSERT(Index <= 12); // Wait until CSR busy bit is cleared - while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY); + while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY); // Set CSR busy bit to ensure read will occur // Set the R/W bit to indicate we are reading @@ -106,13 +106,13 @@ IndirectMACRead32 ( MacCSR = MAC_CSR_BUSY | MAC_CSR_READ | MAC_CSR_ADDR(Index); // Write to the register - MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR); + Lan9118MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR); // Wait until CSR busy bit is cleared - while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY); + while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY); // Now read from data register to get read value - return MmioRead32 (LAN9118_MAC_CSR_DATA); + return Lan9118MmioRead32 (LAN9118_MAC_CSR_DATA); } /* @@ -134,8 +134,8 @@ WaitDummyReads ( UINTN Count ) { - while (Count--) - MmioRead32(LAN9118_BYTE_TEST); + while (Count--) + MmioRead32(LAN9118_BYTE_TEST); } UINT32 @@ -177,7 +177,7 @@ IndirectMACWrite32 ( ASSERT(Index <= 12); // Wait until CSR busy bit is cleared - while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY); + while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY); // Set CSR busy bit to ensure read will occur // Set the R/W bit to indicate we are writing @@ -185,13 +185,13 @@ IndirectMACWrite32 ( MacCSR = MAC_CSR_BUSY | MAC_CSR_WRITE | MAC_CSR_ADDR(Index); // Now write the value to the register before issuing the write command - ValueWritten = MmioWrite32 (LAN9118_MAC_CSR_DATA, Value); + ValueWritten = Lan9118MmioWrite32 (LAN9118_MAC_CSR_DATA, Value); // Write the config to the register - MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR); + Lan9118MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR); // Wait until CSR busy bit is cleared - while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY); + while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY); return ValueWritten; } @@ -283,23 +283,23 @@ IndirectEEPROMRead32 ( EepromCmd |= E2P_EPC_ADDRESS(Index); // Write to Eeprom command register - MmioWrite32 (LAN9118_E2P_CMD, EepromCmd); + Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd); gBS->Stall (LAN9118_STALL); // Wait until operation has completed - while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); + while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); // Check that operation didn't time out - if (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) { + if (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) { DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Read command on index %x\n",Index)); return 0; } // Wait until operation has completed - while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); + while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); // Finally read the value - return MmioRead32 (LAN9118_E2P_DATA); + return Lan9118MmioRead32 (LAN9118_E2P_DATA); } // Function to write to EEPROM memory @@ -315,7 +315,7 @@ IndirectEEPROMWrite32 ( ValueWritten = 0; // Read the EEPROM Command register - EepromCmd = MmioRead32 (LAN9118_E2P_CMD); + EepromCmd = Lan9118MmioRead32 (LAN9118_E2P_CMD); // Set the busy bit to ensure read will occur EepromCmd |= ((UINT32)1 << 31); @@ -328,23 +328,23 @@ IndirectEEPROMWrite32 ( EepromCmd |= (Index & 0xF); // Write the value to the data register first - ValueWritten = MmioWrite32 (LAN9118_E2P_DATA, Value); + ValueWritten = Lan9118MmioWrite32 (LAN9118_E2P_DATA, Value); // Write to Eeprom command register - MmioWrite32 (LAN9118_E2P_CMD, EepromCmd); + Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd); gBS->Stall (LAN9118_STALL); // Wait until operation has completed - while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); + while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); // Check that operation didn't time out - if (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) { + if (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) { DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Write command at memloc 0x%x, with value 0x%x\n",Index, Value)); return 0; } // Wait until operation has completed - while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); + while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); return ValueWritten; } @@ -407,15 +407,15 @@ Lan9118Initialize ( UINT64 DefaultMacAddress; // Attempt to wake-up the device if it is in a lower power state - if (((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) { + if (((Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) { DEBUG ((DEBUG_NET, "Waking from reduced power state.\n")); - MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF); + Lan9118MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF); gBS->Stall (LAN9118_STALL); } // Check that device is active Retries = 20; - while ((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_READY) == 0 && --Retries) { + while ((Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_READY) == 0 && --Retries) { gBS->Stall (LAN9118_STALL); } if (!Retries) { @@ -424,7 +424,7 @@ Lan9118Initialize ( // Check that EEPROM isn't active Retries = 20; - while ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY) && --Retries){ + while ((Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY) && --Retries){ gBS->Stall (LAN9118_STALL); } if (!Retries) { @@ -433,7 +433,7 @@ Lan9118Initialize ( // Check if a MAC address was loaded from EEPROM, and if it was, set it as the // current address. - if ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_MAC_ADDRESS_LOADED) == 0) { + if ((Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_MAC_ADDRESS_LOADED) == 0) { DEBUG ((EFI_D_ERROR, "Warning: There was an error detecting EEPROM or loading the MAC Address.\n")); // If we had an address before (set by StationAddess), continue to use it @@ -453,9 +453,9 @@ Lan9118Initialize ( } // Clear and acknowledge interrupts - MmioWrite32 (LAN9118_INT_EN, 0); - MmioWrite32 (LAN9118_IRQ_CFG, 0); - MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF); + Lan9118MmioWrite32 (LAN9118_INT_EN, 0); + Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0); + Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF); // Do self tests here? @@ -482,7 +482,7 @@ SoftReset ( StopRx (STOP_RX_CLEAR, Snp); // Clear receiver FIFO // Issue the reset - HwConf = MmioRead32 (LAN9118_HW_CFG); + HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG); HwConf |= 1; // Set the Must Be One (MBO) bit @@ -491,14 +491,14 @@ SoftReset ( } // Check that EEPROM isn't active - while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); + while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); // Write the configuration - MmioWrite32 (LAN9118_HW_CFG, HwConf); + Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); gBS->Stall (LAN9118_STALL); // Wait for reset to complete - while (MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) { + while (Lan9118MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) { gBS->Stall (LAN9118_STALL); ResetTime += 1; @@ -511,15 +511,15 @@ SoftReset ( } // Check that EEPROM isn't active - while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); + while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); // TODO we probably need to re-set the mac address here. // Clear and acknowledge all interrupts if (Flags & SOFT_RESET_CLEAR_INT) { - MmioWrite32 (LAN9118_INT_EN, 0); - MmioWrite32 (LAN9118_IRQ_CFG, 0); - MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF); + Lan9118MmioWrite32 (LAN9118_INT_EN, 0); + Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0); + Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF); } // Do self tests here? @@ -542,12 +542,12 @@ PhySoftReset ( // PMT PHY reset takes precedence over BCR if (Flags & PHY_RESET_PMT) { - PmtCtrl = MmioRead32 (LAN9118_PMT_CTRL); + PmtCtrl = Lan9118MmioRead32 (LAN9118_PMT_CTRL); PmtCtrl |= MPTCTRL_PHY_RST; - MmioWrite32 (LAN9118_PMT_CTRL,PmtCtrl); + Lan9118MmioWrite32 (LAN9118_PMT_CTRL,PmtCtrl); // Wait for completion - while (MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PHY_RST) { + while (Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PHY_RST) { gBS->Stall (LAN9118_STALL); } // PHY Basic Control Register reset @@ -562,9 +562,9 @@ PhySoftReset ( // Clear and acknowledge all interrupts if (Flags & PHY_SOFT_RESET_CLEAR_INT) { - MmioWrite32 (LAN9118_INT_EN, 0); - MmioWrite32 (LAN9118_IRQ_CFG, 0); - MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF); + Lan9118MmioWrite32 (LAN9118_INT_EN, 0); + Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0); + Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF); } return EFI_SUCCESS; @@ -582,14 +582,14 @@ ConfigureHardware ( // Check if we want to use LEDs on GPIO if (Flags & HW_CONF_USE_LEDS) { - GpioConf = MmioRead32 (LAN9118_GPIO_CFG); + GpioConf = Lan9118MmioRead32 (LAN9118_GPIO_CFG); // Enable GPIO as LEDs and Config as Push-Pull driver GpioConf |= GPIO_GPIO0_PUSH_PULL | GPIO_GPIO1_PUSH_PULL | GPIO_GPIO2_PUSH_PULL | GPIO_LED1_ENABLE | GPIO_LED2_ENABLE | GPIO_LED3_ENABLE; // Write the configuration - MmioWrite32 (LAN9118_GPIO_CFG, GpioConf); + Lan9118MmioWrite32 (LAN9118_GPIO_CFG, GpioConf); gBS->Stall (LAN9118_STALL); } @@ -716,9 +716,9 @@ StopTx ( // Check if we want to clear tx if (Flags & STOP_TX_CLEAR) { - TxCfg = MmioRead32 (LAN9118_TX_CFG); + TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG); TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP; - MmioWrite32 (LAN9118_TX_CFG, TxCfg); + Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg); gBS->Stall (LAN9118_STALL); } @@ -733,15 +733,15 @@ StopTx ( } if (Flags & STOP_TX_CFG) { - TxCfg = MmioRead32 (LAN9118_TX_CFG); + TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG); if (TxCfg & TXCFG_TX_ON) { TxCfg |= TXCFG_STOP_TX; - MmioWrite32 (LAN9118_TX_CFG, TxCfg); + Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg); gBS->Stall (LAN9118_STALL); // Wait for Tx to finish transmitting - while (MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX); + while (Lan9118MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX); } } @@ -770,12 +770,12 @@ StopRx ( // Check if we want to clear receiver FIFOs if (Flags & STOP_RX_CLEAR) { - RxCfg = MmioRead32 (LAN9118_RX_CFG); + RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG); RxCfg |= RXCFG_RX_DUMP; - MmioWrite32 (LAN9118_RX_CFG, RxCfg); + Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg); gBS->Stall (LAN9118_STALL); - while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP); + while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP); } return EFI_SUCCESS; @@ -796,9 +796,9 @@ StartTx ( // Check if we want to clear tx if (Flags & START_TX_CLEAR) { - TxCfg = MmioRead32 (LAN9118_TX_CFG); + TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG); TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP; - MmioWrite32 (LAN9118_TX_CFG, TxCfg); + Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg); gBS->Stall (LAN9118_STALL); } @@ -815,11 +815,11 @@ StartTx ( // Check if tx was started from TX_CFG and enable if not if (Flags & START_TX_CFG) { - TxCfg = MmioRead32 (LAN9118_TX_CFG); + TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG); gBS->Stall (LAN9118_STALL); if ((TxCfg & TXCFG_TX_ON) == 0) { TxCfg |= TXCFG_TX_ON; - MmioWrite32 (LAN9118_TX_CFG, TxCfg); + Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg); gBS->Stall (LAN9118_STALL); } } @@ -847,12 +847,12 @@ StartRx ( if ((MacCsr & MACCR_RX_EN) == 0) { // Check if we want to clear receiver FIFOs before starting if (Flags & START_RX_CLEAR) { - RxCfg = MmioRead32 (LAN9118_RX_CFG); + RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG); RxCfg |= RXCFG_RX_DUMP; - MmioWrite32 (LAN9118_RX_CFG, RxCfg); + Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg); gBS->Stall (LAN9118_STALL); - while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP); + while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP); } MacCsr |= MACCR_RX_EN; @@ -874,7 +874,7 @@ TxDataFreeSpace ( UINT32 FreeSpace; // Get the amount of free space from information register - TxInf = MmioRead32 (LAN9118_TX_FIFO_INF); + TxInf = Lan9118MmioRead32 (LAN9118_TX_FIFO_INF); FreeSpace = (TxInf & TXFIFOINF_TDFREE_MASK); return FreeSpace; // Value in bytes @@ -891,7 +891,7 @@ TxStatusUsedSpace ( UINT32 UsedSpace; // Get the amount of used space from information register - TxInf = MmioRead32 (LAN9118_TX_FIFO_INF); + TxInf = Lan9118MmioRead32 (LAN9118_TX_FIFO_INF); UsedSpace = (TxInf & TXFIFOINF_TXSUSED_MASK) >> 16; return UsedSpace << 2; // Value in bytes @@ -908,7 +908,7 @@ RxDataUsedSpace ( UINT32 UsedSpace; // Get the amount of used space from information register - RxInf = MmioRead32 (LAN9118_RX_FIFO_INF); + RxInf = Lan9118MmioRead32 (LAN9118_RX_FIFO_INF); UsedSpace = (RxInf & RXFIFOINF_RXDUSED_MASK); return UsedSpace; // Value in bytes (rounded up to nearest DWORD) @@ -925,7 +925,7 @@ RxStatusUsedSpace ( UINT32 UsedSpace; // Get the amount of used space from information register - RxInf = MmioRead32 (LAN9118_RX_FIFO_INF); + RxInf = Lan9118MmioRead32 (LAN9118_RX_FIFO_INF); UsedSpace = (RxInf & RXFIFOINF_RXSUSED_MASK) >> 16; return UsedSpace << 2; // Value in bytes @@ -963,7 +963,7 @@ ChangeFifoAllocation ( // If we use the FIFOs (always use this first) if (Flags & ALLOC_USE_FIFOS) { // Read the current value of allocation - HwConf = MmioRead32 (LAN9118_HW_CFG); + HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG); TxFifoOption = (HwConf >> 16) & 0xF; // Choose the correct size (always use larger than requested if possible) @@ -1046,7 +1046,7 @@ ChangeFifoAllocation ( // Clear and assign the new size option HwConf &= ~(0xF0000); HwConf |= ((TxFifoOption & 0xF) << 16); - MmioWrite32 (LAN9118_HW_CFG, HwConf); + Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); gBS->Stall (LAN9118_STALL); return EFI_SUCCESS; From 505e7fd5d07a7e2b7856050057049399fbbe1186 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Fri, 6 May 2016 18:19:09 +0100 Subject: [PATCH 12/26] EmbeddedPkg/Lan9118Dxe: remove redundant stalls Now that the LAN9118-specific MMIO accessors provide the required delays, remove the redundant stalls. Stalls in delay loops are kept, as these give time for work to happen beyond synchronisation of the device register file. Cc: Leif Lindholm Cc: Ryan Harkin Signed-off-by: Mark Rutland Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Ard Biesheuvel --- EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c | 5 ----- EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c | 16 ---------------- 2 files changed, 21 deletions(-) diff --git a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c index bef34c2e9c..8af23df394 100644 --- a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c +++ b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c @@ -307,8 +307,6 @@ SnpInitialize ( // Write the current configuration to the register Lan9118MmioWrite32 (LAN9118_PMT_CTRL, PmConf); - gBS->Stall (LAN9118_STALL); - gBS->Stall (LAN9118_STALL); // Configure GPIO and HW Status = ConfigureHardware (HW_CONF_USE_LEDS, Snp); @@ -431,7 +429,6 @@ SnpReset ( // Write the current configuration to the register Lan9118MmioWrite32 (LAN9118_PMT_CTRL, PmConf); - gBS->Stall (LAN9118_STALL); // Reactivate the LEDs Status = ConfigureHardware (HW_CONF_USE_LEDS, Snp); @@ -446,7 +443,6 @@ SnpReset ( HwConf |= HW_CFG_TX_FIFO_SIZE(gTxBuffer); // assign size chosen in SnpInitialize Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); // Write the conf - gBS->Stall (LAN9118_STALL); } // Enable the receiver and transmitter and clear their contents @@ -701,7 +697,6 @@ SnpReceiveFilters ( // Write the options to the MAC_CSR // IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCSRValue); - gBS->Stall (LAN9118_STALL); // // If we have to retrieve something, start packet reception. diff --git a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c index 61f11b6e27..50c004d728 100644 --- a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c +++ b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c @@ -284,7 +284,6 @@ IndirectEEPROMRead32 ( // Write to Eeprom command register Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd); - gBS->Stall (LAN9118_STALL); // Wait until operation has completed while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); @@ -332,7 +331,6 @@ IndirectEEPROMWrite32 ( // Write to Eeprom command register Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd); - gBS->Stall (LAN9118_STALL); // Wait until operation has completed while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY); @@ -410,7 +408,6 @@ Lan9118Initialize ( if (((Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) { DEBUG ((DEBUG_NET, "Waking from reduced power state.\n")); Lan9118MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF); - gBS->Stall (LAN9118_STALL); } // Check that device is active @@ -495,7 +492,6 @@ SoftReset ( // Write the configuration Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); - gBS->Stall (LAN9118_STALL); // Wait for reset to complete while (Lan9118MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) { @@ -590,7 +586,6 @@ ConfigureHardware ( // Write the configuration Lan9118MmioWrite32 (LAN9118_GPIO_CFG, GpioConf); - gBS->Stall (LAN9118_STALL); } return EFI_SUCCESS; @@ -719,7 +714,6 @@ StopTx ( TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG); TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP; Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg); - gBS->Stall (LAN9118_STALL); } // Check if already stopped @@ -738,7 +732,6 @@ StopTx ( if (TxCfg & TXCFG_TX_ON) { TxCfg |= TXCFG_STOP_TX; Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg); - gBS->Stall (LAN9118_STALL); // Wait for Tx to finish transmitting while (Lan9118MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX); @@ -773,7 +766,6 @@ StopRx ( RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG); RxCfg |= RXCFG_RX_DUMP; Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg); - gBS->Stall (LAN9118_STALL); while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP); } @@ -799,28 +791,23 @@ StartTx ( TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG); TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP; Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg); - gBS->Stall (LAN9118_STALL); } // Check if tx was started from MAC and enable if not if (Flags & START_TX_MAC) { MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR); - gBS->Stall (LAN9118_STALL); if ((MacCsr & MACCR_TX_EN) == 0) { MacCsr |= MACCR_TX_EN; IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr); - gBS->Stall (LAN9118_STALL); } } // Check if tx was started from TX_CFG and enable if not if (Flags & START_TX_CFG) { TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG); - gBS->Stall (LAN9118_STALL); if ((TxCfg & TXCFG_TX_ON) == 0) { TxCfg |= TXCFG_TX_ON; Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg); - gBS->Stall (LAN9118_STALL); } } @@ -850,14 +837,12 @@ StartRx ( RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG); RxCfg |= RXCFG_RX_DUMP; Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg); - gBS->Stall (LAN9118_STALL); while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP); } MacCsr |= MACCR_RX_EN; IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr); - gBS->Stall (LAN9118_STALL); } return EFI_SUCCESS; @@ -1047,7 +1032,6 @@ ChangeFifoAllocation ( HwConf &= ~(0xF0000); HwConf |= ((TxFifoOption & 0xF) << 16); Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); - gBS->Stall (LAN9118_STALL); return EFI_SUCCESS; } From 12460e227fa62d5b6c863f2167abcf5a6ca5a10b Mon Sep 17 00:00:00 2001 From: "Leahy, Leroy P" Date: Mon, 9 May 2016 10:56:40 -0700 Subject: [PATCH 13/26] CorebootModulePkg: Add BaseSerialPortLib16550 Copy MdeModulePkg/Library/BaseSerialPortLib16550 revision 89ecd4cf8078aa946083cdcbf9af81ff29f8d9f5. Change-Id: Ie2fd0123bdd7aaba4335afdb1cb017f3690455c6 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy Reviewed-by: Prince Agyeman --- .../BaseSerialPortLib16550.c | 1094 +++++++++++++++++ .../BaseSerialPortLib16550.inf | 48 + .../BaseSerialPortLib16550.uni | 22 + 3 files changed, 1164 insertions(+) create mode 100644 CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c create mode 100644 CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf create mode 100644 CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni diff --git a/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c new file mode 100644 index 0000000000..25ca822eb7 --- /dev/null +++ b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c @@ -0,0 +1,1094 @@ +/** @file + 16550 UART Serial Port library functions + + (C) Copyright 2014 Hewlett-Packard Development Company, L.P.
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +// +// PCI Defintions. +// +#define PCI_BRIDGE_32_BIT_IO_SPACE 0x01 + +// +// 16550 UART register offsets and bitfields +// +#define R_UART_RXBUF 0 +#define R_UART_TXBUF 0 +#define R_UART_BAUD_LOW 0 +#define R_UART_BAUD_HIGH 1 +#define R_UART_FCR 2 +#define B_UART_FCR_FIFOE BIT0 +#define B_UART_FCR_FIFO64 BIT5 +#define R_UART_LCR 3 +#define B_UART_LCR_DLAB BIT7 +#define R_UART_MCR 4 +#define B_UART_MCR_DTRC BIT0 +#define B_UART_MCR_RTS BIT1 +#define R_UART_LSR 5 +#define B_UART_LSR_RXRDY BIT0 +#define B_UART_LSR_TXRDY BIT5 +#define B_UART_LSR_TEMT BIT6 +#define R_UART_MSR 6 +#define B_UART_MSR_CTS BIT4 +#define B_UART_MSR_DSR BIT5 +#define B_UART_MSR_RI BIT6 +#define B_UART_MSR_DCD BIT7 + +// +// 4-byte structure for each PCI node in PcdSerialPciDeviceInfo +// +typedef struct { + UINT8 Device; + UINT8 Function; + UINT16 PowerManagementStatusAndControlRegister; +} PCI_UART_DEVICE_INFO; + +/** + Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from + MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The + parameter Offset is added to the base address of the 16550 registers that is specified + by PcdSerialRegisterBase. + + @param Base The base address register of UART device. + @param Offset The offset of the 16550 register to read. + + @return The value read from the 16550 register. + +**/ +UINT8 +SerialPortReadRegister ( + UINTN Base, + UINTN Offset + ) +{ + if (PcdGetBool (PcdSerialUseMmio)) { + return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride)); + } else { + return IoRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride)); + } +} + +/** + Write an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is written to + MMIO space. If PcdSerialUseMmio is FALSE, then the value is written to I/O space. The + parameter Offset is added to the base address of the 16550 registers that is specified + by PcdSerialRegisterBase. + + @param Base The base address register of UART device. + @param Offset The offset of the 16550 register to write. + @param Value The value to write to the 16550 register specified by Offset. + + @return The value written to the 16550 register. + +**/ +UINT8 +SerialPortWriteRegister ( + UINTN Base, + UINTN Offset, + UINT8 Value + ) +{ + if (PcdGetBool (PcdSerialUseMmio)) { + return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value); + } else { + return IoWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value); + } +} + +/** + Update the value of an 16-bit PCI configuration register in a PCI device. If the + PCI Configuration register specified by PciAddress is already programmed with a + non-zero value, then return the current value. Otherwise update the PCI configuration + register specified by PciAddress with the value specified by Value and return the + value programmed into the PCI configuration register. All values must be masked + using the bitmask specified by Mask. + + @param PciAddress PCI Library address of the PCI Configuration register to update. + @param Value The value to program into the PCI Configuration Register. + @param Mask Bitmask of the bits to check and update in the PCI configuration register. + +**/ +UINT16 +SerialPortLibUpdatePciRegister16 ( + UINTN PciAddress, + UINT16 Value, + UINT16 Mask + ) +{ + UINT16 CurrentValue; + + CurrentValue = PciRead16 (PciAddress) & Mask; + if (CurrentValue != 0) { + return CurrentValue; + } + return PciWrite16 (PciAddress, Value & Mask); +} + +/** + Update the value of an 32-bit PCI configuration register in a PCI device. If the + PCI Configuration register specified by PciAddress is already programmed with a + non-zero value, then return the current value. Otherwise update the PCI configuration + register specified by PciAddress with the value specified by Value and return the + value programmed into the PCI configuration register. All values must be masked + using the bitmask specified by Mask. + + @param PciAddress PCI Library address of the PCI Configuration register to update. + @param Value The value to program into the PCI Configuration Register. + @param Mask Bitmask of the bits to check and update in the PCI configuration register. + + @return The Secondary bus number that is actually programed into the PCI to PCI Bridge device. + +**/ +UINT32 +SerialPortLibUpdatePciRegister32 ( + UINTN PciAddress, + UINT32 Value, + UINT32 Mask + ) +{ + UINT32 CurrentValue; + + CurrentValue = PciRead32 (PciAddress) & Mask; + if (CurrentValue != 0) { + return CurrentValue; + } + return PciWrite32 (PciAddress, Value & Mask); +} + +/** + Retrieve the I/O or MMIO base address register for the PCI UART device. + + This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in PCI UART + Device if they are not already enabled. + + @return The base address register of the UART device. + +**/ +UINTN +GetSerialRegisterBase ( + VOID + ) +{ + UINTN PciLibAddress; + UINTN BusNumber; + UINTN SubordinateBusNumber; + UINT32 ParentIoBase; + UINT32 ParentIoLimit; + UINT16 ParentMemoryBase; + UINT16 ParentMemoryLimit; + UINT32 IoBase; + UINT32 IoLimit; + UINT16 MemoryBase; + UINT16 MemoryLimit; + UINTN SerialRegisterBase; + UINTN BarIndex; + UINT32 RegisterBaseMask; + PCI_UART_DEVICE_INFO *DeviceInfo; + + // + // Get PCI Device Info + // + DeviceInfo = (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInfo); + + // + // If PCI Device Info is empty, then assume fixed address UART and return PcdSerialRegisterBase + // + if (DeviceInfo->Device == 0xff) { + return (UINTN)PcdGet64 (PcdSerialRegisterBase); + } + + // + // Assume PCI Bus 0 I/O window is 0-64KB and MMIO windows is 0-4GB + // + ParentMemoryBase = 0 >> 16; + ParentMemoryLimit = 0xfff00000 >> 16; + ParentIoBase = 0 >> 12; + ParentIoLimit = 0xf000 >> 12; + + // + // Enable I/O and MMIO in PCI Bridge + // Assume Root Bus Numer is Zero. + // + for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) { + // + // Compute PCI Lib Address to PCI to PCI Bridge + // + PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0); + + // + // Retrieve and verify the bus numbers in the PCI to PCI Bridge + // + BusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET); + SubordinateBusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET); + if (BusNumber == 0 || BusNumber > SubordinateBusNumber) { + return 0; + } + + // + // Retrieve and verify the I/O or MMIO decode window in the PCI to PCI Bridge + // + if (PcdGetBool (PcdSerialUseMmio)) { + MemoryLimit = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit)) & 0xfff0; + MemoryBase = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase)) & 0xfff0; + + // + // If PCI Bridge MMIO window is disabled, then return 0 + // + if (MemoryLimit < MemoryBase) { + return 0; + } + + // + // If PCI Bridge MMIO window is not in the address range decoded by the parent PCI Bridge, then return 0 + // + if (MemoryBase < ParentMemoryBase || MemoryBase > ParentMemoryLimit || MemoryLimit > ParentMemoryLimit) { + return 0; + } + ParentMemoryBase = MemoryBase; + ParentMemoryLimit = MemoryLimit; + } else { + IoLimit = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimit)); + if ((IoLimit & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) { + IoLimit = IoLimit >> 4; + } else { + IoLimit = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimitUpper16)) << 4) | (IoLimit >> 4); + } + IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase)); + if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) { + IoBase = IoBase >> 4; + } else { + IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase >> 4); + } + + // + // If PCI Bridge I/O window is disabled, then return 0 + // + if (IoLimit < IoBase) { + return 0; + } + + // + // If PCI Bridge I/O window is not in the address range decoded by the parent PCI Bridge, then return 0 + // + if (IoBase < ParentIoBase || IoBase > ParentIoLimit || IoLimit > ParentIoLimit) { + return 0; + } + ParentIoBase = IoBase; + ParentIoLimit = IoLimit; + } + } + + // + // Compute PCI Lib Address to PCI UART + // + PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0); + + // + // Find the first IO or MMIO BAR + // + RegisterBaseMask = 0xFFFFFFF0; + for (BarIndex = 0; BarIndex < PCI_MAX_BAR; BarIndex ++) { + SerialRegisterBase = PciRead32 (PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4); + if (PcdGetBool (PcdSerialUseMmio) && ((SerialRegisterBase & BIT0) == 0)) { + // + // MMIO BAR is found + // + RegisterBaseMask = 0xFFFFFFF0; + break; + } + + if ((!PcdGetBool (PcdSerialUseMmio)) && ((SerialRegisterBase & BIT0) != 0)) { + // + // IO BAR is found + // + RegisterBaseMask = 0xFFFFFFF8; + break; + } + } + + // + // MMIO or IO BAR is not found. + // + if (BarIndex == PCI_MAX_BAR) { + return 0; + } + + // + // Program UART BAR + // + SerialRegisterBase = SerialPortLibUpdatePciRegister32 ( + PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4, + (UINT32)PcdGet64 (PcdSerialRegisterBase), + RegisterBaseMask + ); + + // + // Verify that the UART BAR is in the address range decoded by the parent PCI Bridge + // + if (PcdGetBool (PcdSerialUseMmio)) { + if (((SerialRegisterBase >> 16) & 0xfff0) < ParentMemoryBase || ((SerialRegisterBase >> 16) & 0xfff0) > ParentMemoryLimit) { + return 0; + } + } else { + if ((SerialRegisterBase >> 12) < ParentIoBase || (SerialRegisterBase >> 12) > ParentIoLimit) { + return 0; + } + } + + // + // Enable I/O and MMIO in PCI UART Device if they are not already enabled + // + PciOr16 ( + PciLibAddress + PCI_COMMAND_OFFSET, + PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI_COMMAND_IO_SPACE + ); + + // + // Force D0 state if a Power Management and Status Register is specified + // + if (DeviceInfo->PowerManagementStatusAndControlRegister != 0x00) { + if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) { + PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1)); + // + // If PCI UART was not in D0, then make sure FIFOs are enabled, but do not reset FIFOs + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64))); + } + } + + // + // Get PCI Device Info + // + DeviceInfo = (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInfo); + + // + // Enable I/O or MMIO in PCI Bridge + // Assume Root Bus Numer is Zero. + // + for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) { + // + // Compute PCI Lib Address to PCI to PCI Bridge + // + PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0); + + // + // Enable the I/O or MMIO decode windows in the PCI to PCI Bridge + // + PciOr16 ( + PciLibAddress + PCI_COMMAND_OFFSET, + PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI_COMMAND_IO_SPACE + ); + + // + // Force D0 state if a Power Management and Status Register is specified + // + if (DeviceInfo->PowerManagementStatusAndControlRegister != 0x00) { + if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) { + PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1)); + } + } + + BusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET); + } + + return SerialRegisterBase; +} + +/** + Return whether the hardware flow control signal allows writing. + + @param SerialRegisterBase The base address register of UART device. + + @retval TRUE The serial port is writable. + @retval FALSE The serial port is not writable. +**/ +BOOLEAN +SerialPortWritable ( + UINTN SerialRegisterBase + ) +{ + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) { + if (PcdGetBool (PcdSerialDetectCable)) { + // + // Wait for both DSR and CTS to be set + // DSR is set if a cable is connected. + // CTS is set if it is ok to transmit data + // + // DSR CTS Description Action + // === === ======================================== ======== + // 0 0 No cable connected. Wait + // 0 1 No cable connected. Wait + // 1 0 Cable connected, but not clear to send. Wait + // 1 1 Cable connected, and clear to send. Transmit + // + return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) == (B_UART_MSR_DSR | B_UART_MSR_CTS)); + } else { + // + // Wait for both DSR and CTS to be set OR for DSR to be clear. + // DSR is set if a cable is connected. + // CTS is set if it is ok to transmit data + // + // DSR CTS Description Action + // === === ======================================== ======== + // 0 0 No cable connected. Transmit + // 0 1 No cable connected. Transmit + // 1 0 Cable connected, but not clear to send. Wait + // 1 1 Cable connected, and clar to send. Transmit + // + return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) != (B_UART_MSR_DSR)); + } + } + + return TRUE; +} + +/** + Initialize the serial device hardware. + + If no initialization is required, then return RETURN_SUCCESS. + If the serial device was successfully initialized, then return RETURN_SUCCESS. + If the serial device could not be initialized, then return RETURN_DEVICE_ERROR. + + @retval RETURN_SUCCESS The serial device was initialized. + @retval RETURN_DEVICE_ERROR The serial device could not be initialized. + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + RETURN_STATUS Status; + UINTN SerialRegisterBase; + UINT32 Divisor; + UINT32 CurrentDivisor; + BOOLEAN Initialized; + + // + // Perform platform specific initialization required to enable use of the 16550 device + // at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase. + // + Status = PlatformHookSerialPortInitialize (); + if (RETURN_ERROR (Status)) { + return Status; + } + + // + // Calculate divisor for baud generator + // Ref_Clk_Rate / Baud_Rate / 16 + // + Divisor = PcdGet32 (PcdSerialClockRate) / (PcdGet32 (PcdSerialBaudRate) * 16); + if ((PcdGet32 (PcdSerialClockRate) % (PcdGet32 (PcdSerialBaudRate) * 16)) >= PcdGet32 (PcdSerialBaudRate) * 8) { + Divisor++; + } + + // + // Get the base address of the serial port in either I/O or MMIO space + // + SerialRegisterBase = GetSerialRegisterBase (); + if (SerialRegisterBase ==0) { + return RETURN_DEVICE_ERROR; + } + + // + // See if the serial port is already initialized + // + Initialized = TRUE; + if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & 0x3F) != (PcdGet8 (PcdSerialLineControl) & 0x3F)) { + Initialized = FALSE; + } + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) | B_UART_LCR_DLAB)); + CurrentDivisor = SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_HIGH) << 8; + CurrentDivisor |= (UINT32) SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_LOW); + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & ~B_UART_LCR_DLAB)); + if (CurrentDivisor != Divisor) { + Initialized = FALSE; + } + if (Initialized) { + return RETURN_SUCCESS; + } + + // + // Wait for the serial port to be ready. + // Verify that both the transmit FIFO and the shift register are empty. + // + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)); + + // + // Configure baud rate + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB); + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8)); + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff)); + + // + // Clear DLAB and configure Data Bits, Parity, and Stop Bits. + // Strip reserved bits from PcdSerialLineControl + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(PcdGet8 (PcdSerialLineControl) & 0x3F)); + + // + // Enable and reset FIFOs + // Strip reserved bits from PcdSerialFifoControl + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00); + SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64))); + + // + // Put Modem Control Register(MCR) into its reset state of 0x00. + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00); + + return RETURN_SUCCESS; +} + +/** + Write data from buffer to serial device. + + Writes NumberOfBytes data bytes from Buffer to the serial device. + The number of bytes actually written to the serial device is returned. + If the return value is less than NumberOfBytes, then the write operation failed. + + If Buffer is NULL, then ASSERT(). + + If NumberOfBytes is zero, then return 0. + + @param Buffer Pointer to the data buffer to be written. + @param NumberOfBytes Number of bytes to written to the serial device. + + @retval 0 NumberOfBytes is 0. + @retval >0 The number of bytes written to the serial device. + If this value is less than NumberOfBytes, then the write operation failed. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINTN SerialRegisterBase; + UINTN Result; + UINTN Index; + UINTN FifoSize; + + if (Buffer == NULL) { + return 0; + } + + SerialRegisterBase = GetSerialRegisterBase (); + if (SerialRegisterBase ==0) { + return 0; + } + + if (NumberOfBytes == 0) { + // + // Flush the hardware + // + + // + // Wait for both the transmit FIFO and shift register empty. + // + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)); + + // + // Wait for the hardware flow control signal + // + while (!SerialPortWritable (SerialRegisterBase)); + return 0; + } + + // + // Compute the maximum size of the Tx FIFO + // + FifoSize = 1; + if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFOE) != 0) { + if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFO64) == 0) { + FifoSize = 16; + } else { + FifoSize = PcdGet32 (PcdSerialExtendedTxFifoSize); + } + } + + Result = NumberOfBytes; + while (NumberOfBytes != 0) { + // + // Wait for the serial port to be ready, to make sure both the transmit FIFO + // and shift register empty. + // + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_TEMT) == 0); + + // + // Fill then entire Tx FIFO + // + for (Index = 0; Index < FifoSize && NumberOfBytes != 0; Index++, NumberOfBytes--, Buffer++) { + // + // Wait for the hardware flow control signal + // + while (!SerialPortWritable (SerialRegisterBase)); + + // + // Write byte to the transmit buffer. + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_TXBUF, *Buffer); + } + } + return Result; +} + +/** + Reads data from a serial device into a buffer. + + @param Buffer Pointer to the data buffer to store the data read from the serial device. + @param NumberOfBytes Number of bytes to read from the serial device. + + @retval 0 NumberOfBytes is 0. + @retval >0 The number of bytes read from the serial device. + If this value is less than NumberOfBytes, then the read operation failed. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINTN SerialRegisterBase; + UINTN Result; + UINT8 Mcr; + + if (NULL == Buffer) { + return 0; + } + + SerialRegisterBase = GetSerialRegisterBase (); + if (SerialRegisterBase ==0) { + return 0; + } + + Mcr = (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS); + + for (Result = 0; NumberOfBytes-- != 0; Result++, Buffer++) { + // + // Wait for the serial port to have some data. + // + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) == 0) { + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) { + // + // Set RTS to let the peer send some data + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Mcr | B_UART_MCR_RTS)); + } + } + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) { + // + // Clear RTS to prevent peer from sending data + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr); + } + + // + // Read byte from the receive buffer. + // + *Buffer = SerialPortReadRegister (SerialRegisterBase, R_UART_RXBUF); + } + + return Result; +} + + +/** + Polls a serial device to see if there is any data waiting to be read. + + Polls aserial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is returned. + If there is no data waiting to be read from the serial device, then FALSE is returned. + + @retval TRUE Data is waiting to be read from the serial device. + @retval FALSE There is no data waiting to be read from the serial device. + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + UINTN SerialRegisterBase; + + SerialRegisterBase = GetSerialRegisterBase (); + if (SerialRegisterBase ==0) { + return FALSE; + } + + // + // Read the serial port status + // + if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) != 0) { + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) { + // + // Clear RTS to prevent peer from sending data + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS)); + } + return TRUE; + } + + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) { + // + // Set RTS to let the peer send some data + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) | B_UART_MCR_RTS)); + } + + return FALSE; +} + +/** + Sets the control bits on a serial device. + + @param Control Sets the bits of Control that are settable. + + @retval RETURN_SUCCESS The new control bits were set on the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ) +{ + UINTN SerialRegisterBase; + UINT8 Mcr; + + // + // First determine the parameter is invalid. + // + if ((Control & (~(EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_READY | + EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE))) != 0) { + return RETURN_UNSUPPORTED; + } + + SerialRegisterBase = GetSerialRegisterBase (); + if (SerialRegisterBase ==0) { + return RETURN_UNSUPPORTED; + } + + // + // Read the Modem Control Register. + // + Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR); + Mcr &= (~(B_UART_MCR_DTRC | B_UART_MCR_RTS)); + + if ((Control & EFI_SERIAL_DATA_TERMINAL_READY) == EFI_SERIAL_DATA_TERMINAL_READY) { + Mcr |= B_UART_MCR_DTRC; + } + + if ((Control & EFI_SERIAL_REQUEST_TO_SEND) == EFI_SERIAL_REQUEST_TO_SEND) { + Mcr |= B_UART_MCR_RTS; + } + + // + // Write the Modem Control Register. + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr); + + return RETURN_SUCCESS; +} + +/** + Retrieve the status of the control bits on a serial device. + + @param Control A pointer to return the current control signals from the serial device. + + @retval RETURN_SUCCESS The control bits were read from the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ) +{ + UINTN SerialRegisterBase; + UINT8 Msr; + UINT8 Mcr; + UINT8 Lsr; + + SerialRegisterBase = GetSerialRegisterBase (); + if (SerialRegisterBase ==0) { + return RETURN_UNSUPPORTED; + } + + *Control = 0; + + // + // Read the Modem Status Register. + // + Msr = SerialPortReadRegister (SerialRegisterBase, R_UART_MSR); + + if ((Msr & B_UART_MSR_CTS) == B_UART_MSR_CTS) { + *Control |= EFI_SERIAL_CLEAR_TO_SEND; + } + + if ((Msr & B_UART_MSR_DSR) == B_UART_MSR_DSR) { + *Control |= EFI_SERIAL_DATA_SET_READY; + } + + if ((Msr & B_UART_MSR_RI) == B_UART_MSR_RI) { + *Control |= EFI_SERIAL_RING_INDICATE; + } + + if ((Msr & B_UART_MSR_DCD) == B_UART_MSR_DCD) { + *Control |= EFI_SERIAL_CARRIER_DETECT; + } + + // + // Read the Modem Control Register. + // + Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR); + + if ((Mcr & B_UART_MCR_DTRC) == B_UART_MCR_DTRC) { + *Control |= EFI_SERIAL_DATA_TERMINAL_READY; + } + + if ((Mcr & B_UART_MCR_RTS) == B_UART_MCR_RTS) { + *Control |= EFI_SERIAL_REQUEST_TO_SEND; + } + + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) { + *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE; + } + + // + // Read the Line Status Register. + // + Lsr = SerialPortReadRegister (SerialRegisterBase, R_UART_LSR); + + if ((Lsr & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) == (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) { + *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY; + } + + if ((Lsr & B_UART_LSR_RXRDY) == 0) { + *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY; + } + + return RETURN_SUCCESS; +} + +/** + Sets the baud rate, receive FIFO depth, transmit/receice time out, parity, + data bits, and stop bits on a serial device. + + @param BaudRate The requested baud rate. A BaudRate value of 0 will use the + device's default interface speed. + On output, the value actually set. + @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the + serial interface. A ReceiveFifoDepth value of 0 will use + the device's default FIFO depth. + On output, the value actually set. + @param Timeout The requested time out for a single character in microseconds. + This timeout applies to both the transmit and receive side of the + interface. A Timeout value of 0 will use the device's default time + out value. + On output, the value actually set. + @param Parity The type of parity to use on this serial device. A Parity value of + DefaultParity will use the device's default parity value. + On output, the value actually set. + @param DataBits The number of data bits to use on the serial device. A DataBits + vaule of 0 will use the device's default data bit setting. + On output, the value actually set. + @param StopBits The number of stop bits to use on this serial device. A StopBits + value of DefaultStopBits will use the device's default number of + stop bits. + On output, the value actually set. + + @retval RETURN_SUCCESS The new attributes were set on the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + UINTN SerialRegisterBase; + UINT32 SerialBaudRate; + UINTN Divisor; + UINT8 Lcr; + UINT8 LcrData; + UINT8 LcrParity; + UINT8 LcrStop; + + SerialRegisterBase = GetSerialRegisterBase (); + if (SerialRegisterBase ==0) { + return RETURN_UNSUPPORTED; + } + + // + // Check for default settings and fill in actual values. + // + if (*BaudRate == 0) { + *BaudRate = PcdGet32 (PcdSerialBaudRate); + } + SerialBaudRate = (UINT32) *BaudRate; + + if (*DataBits == 0) { + LcrData = (UINT8) (PcdGet8 (PcdSerialLineControl) & 0x3); + *DataBits = LcrData + 5; + } else { + if ((*DataBits < 5) || (*DataBits > 8)) { + return RETURN_INVALID_PARAMETER; + } + // + // Map 5..8 to 0..3 + // + LcrData = (UINT8) (*DataBits - (UINT8) 5); + } + + if (*Parity == DefaultParity) { + LcrParity = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 3) & 0x7); + switch (LcrParity) { + case 0: + *Parity = NoParity; + break; + + case 3: + *Parity = EvenParity; + break; + + case 1: + *Parity = OddParity; + break; + + case 7: + *Parity = SpaceParity; + break; + + case 5: + *Parity = MarkParity; + break; + + default: + break; + } + } else { + switch (*Parity) { + case NoParity: + LcrParity = 0; + break; + + case EvenParity: + LcrParity = 3; + break; + + case OddParity: + LcrParity = 1; + break; + + case SpaceParity: + LcrParity = 7; + break; + + case MarkParity: + LcrParity = 5; + break; + + default: + return RETURN_INVALID_PARAMETER; + } + } + + if (*StopBits == DefaultStopBits) { + LcrStop = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 2) & 0x1); + switch (LcrStop) { + case 0: + *StopBits = OneStopBit; + break; + + case 1: + if (*DataBits == 5) { + *StopBits = OneFiveStopBits; + } else { + *StopBits = TwoStopBits; + } + break; + + default: + break; + } + } else { + switch (*StopBits) { + case OneStopBit: + LcrStop = 0; + break; + + case OneFiveStopBits: + case TwoStopBits: + LcrStop = 1; + break; + + default: + return RETURN_INVALID_PARAMETER; + } + } + + // + // Calculate divisor for baud generator + // Ref_Clk_Rate / Baud_Rate / 16 + // + Divisor = PcdGet32 (PcdSerialClockRate) / (SerialBaudRate * 16); + if ((PcdGet32 (PcdSerialClockRate) % (SerialBaudRate * 16)) >= SerialBaudRate * 8) { + Divisor++; + } + + // + // Configure baud rate + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB); + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8)); + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff)); + + // + // Clear DLAB and configure Data Bits, Parity, and Stop Bits. + // Strip reserved bits from line control value + // + Lcr = (UINT8) ((LcrParity << 3) | (LcrStop << 2) | LcrData); + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8) (Lcr & 0x3F)); + + return RETURN_SUCCESS; +} + diff --git a/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf new file mode 100644 index 0000000000..e8b340cf91 --- /dev/null +++ b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf @@ -0,0 +1,48 @@ +## @file +# SerialPortLib instance for 16550 UART. +# +# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = BaseSerialPortLib16550 + MODULE_UNI_FILE = BaseSerialPortLib16550.uni + FILE_GUID = 9E7C00CF-355A-4d4e-BF60-0428CFF95540 + MODULE_TYPE = BASE + VERSION_STRING = 1.1 + LIBRARY_CLASS = SerialPortLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + PcdLib + IoLib + PlatformHookLib + PciLib + +[Sources] + BaseSerialPortLib16550.c + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable ## SOMETIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## CONSUMES diff --git a/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni new file mode 100644 index 0000000000..0b8d7f9131 --- /dev/null +++ b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni @@ -0,0 +1,22 @@ +// /** @file +// SerialPortLib instance for 16550 UART. +// +// SerialPortLib instance for 16550 UART. +// +// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "SerialPortLib instance for 16550 UART" + +#string STR_MODULE_DESCRIPTION #language en-US "SerialPortLib instance for 16550 UART." + From b08993bd13578b081f7c416efe932be6b73194b2 Mon Sep 17 00:00:00 2001 From: "Leahy, Leroy P" Date: Mon, 9 May 2016 10:56:55 -0700 Subject: [PATCH 14/26] CorebootModulePkg/BaseSerialPortLib16550: Remove white-space Remove trailing white space. Change-Id: I73c3a3e1e55eec20b09443de1966573c97fa74f8 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy Reviewed-by: Prince Agyeman --- .../BaseSerialPortLib16550.c | 126 +++++++++--------- .../BaseSerialPortLib16550.inf | 2 +- 2 files changed, 64 insertions(+), 64 deletions(-) diff --git a/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c index 25ca822eb7..45056363c3 100644 --- a/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c +++ b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c @@ -62,11 +62,11 @@ typedef struct { } PCI_UART_DEVICE_INFO; /** - Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from + Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The - parameter Offset is added to the base address of the 16550 registers that is specified - by PcdSerialRegisterBase. - + parameter Offset is added to the base address of the 16550 registers that is specified + by PcdSerialRegisterBase. + @param Base The base address register of UART device. @param Offset The offset of the 16550 register to read. @@ -89,9 +89,9 @@ SerialPortReadRegister ( /** Write an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is written to MMIO space. If PcdSerialUseMmio is FALSE, then the value is written to I/O space. The - parameter Offset is added to the base address of the 16550 registers that is specified - by PcdSerialRegisterBase. - + parameter Offset is added to the base address of the 16550 registers that is specified + by PcdSerialRegisterBase. + @param Base The base address register of UART device. @param Offset The offset of the 16550 register to write. @param Value The value to write to the 16550 register specified by Offset. @@ -114,11 +114,11 @@ SerialPortWriteRegister ( } /** - Update the value of an 16-bit PCI configuration register in a PCI device. If the - PCI Configuration register specified by PciAddress is already programmed with a - non-zero value, then return the current value. Otherwise update the PCI configuration + Update the value of an 16-bit PCI configuration register in a PCI device. If the + PCI Configuration register specified by PciAddress is already programmed with a + non-zero value, then return the current value. Otherwise update the PCI configuration register specified by PciAddress with the value specified by Value and return the - value programmed into the PCI configuration register. All values must be masked + value programmed into the PCI configuration register. All values must be masked using the bitmask specified by Mask. @param PciAddress PCI Library address of the PCI Configuration register to update. @@ -134,7 +134,7 @@ SerialPortLibUpdatePciRegister16 ( ) { UINT16 CurrentValue; - + CurrentValue = PciRead16 (PciAddress) & Mask; if (CurrentValue != 0) { return CurrentValue; @@ -143,11 +143,11 @@ SerialPortLibUpdatePciRegister16 ( } /** - Update the value of an 32-bit PCI configuration register in a PCI device. If the - PCI Configuration register specified by PciAddress is already programmed with a - non-zero value, then return the current value. Otherwise update the PCI configuration + Update the value of an 32-bit PCI configuration register in a PCI device. If the + PCI Configuration register specified by PciAddress is already programmed with a + non-zero value, then return the current value. Otherwise update the PCI configuration register specified by PciAddress with the value specified by Value and return the - value programmed into the PCI configuration register. All values must be masked + value programmed into the PCI configuration register. All values must be masked using the bitmask specified by Mask. @param PciAddress PCI Library address of the PCI Configuration register to update. @@ -165,7 +165,7 @@ SerialPortLibUpdatePciRegister32 ( ) { UINT32 CurrentValue; - + CurrentValue = PciRead32 (PciAddress) & Mask; if (CurrentValue != 0) { return CurrentValue; @@ -174,11 +174,11 @@ SerialPortLibUpdatePciRegister32 ( } /** - Retrieve the I/O or MMIO base address register for the PCI UART device. - - This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in PCI UART - Device if they are not already enabled. - + Retrieve the I/O or MMIO base address register for the PCI UART device. + + This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in PCI UART + Device if they are not already enabled. + @return The base address register of the UART device. **/ @@ -207,10 +207,10 @@ GetSerialRegisterBase ( // Get PCI Device Info // DeviceInfo = (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInfo); - + // // If PCI Device Info is empty, then assume fixed address UART and return PcdSerialRegisterBase - // + // if (DeviceInfo->Device == 0xff) { return (UINTN)PcdGet64 (PcdSerialRegisterBase); } @@ -222,17 +222,17 @@ GetSerialRegisterBase ( ParentMemoryLimit = 0xfff00000 >> 16; ParentIoBase = 0 >> 12; ParentIoLimit = 0xf000 >> 12; - + // // Enable I/O and MMIO in PCI Bridge - // Assume Root Bus Numer is Zero. + // Assume Root Bus Numer is Zero. // for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) { // // Compute PCI Lib Address to PCI to PCI Bridge // PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0); - + // // Retrieve and verify the bus numbers in the PCI to PCI Bridge // @@ -255,10 +255,10 @@ GetSerialRegisterBase ( if (MemoryLimit < MemoryBase) { return 0; } - + // // If PCI Bridge MMIO window is not in the address range decoded by the parent PCI Bridge, then return 0 - // + // if (MemoryBase < ParentMemoryBase || MemoryBase > ParentMemoryLimit || MemoryLimit > ParentMemoryLimit) { return 0; } @@ -277,17 +277,17 @@ GetSerialRegisterBase ( } else { IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase >> 4); } - + // // If PCI Bridge I/O window is disabled, then return 0 // if (IoLimit < IoBase) { return 0; } - + // // If PCI Bridge I/O window is not in the address range decoded by the parent PCI Bridge, then return 0 - // + // if (IoBase < ParentIoBase || IoBase > ParentIoLimit || IoLimit > ParentIoLimit) { return 0; } @@ -300,7 +300,7 @@ GetSerialRegisterBase ( // Compute PCI Lib Address to PCI UART // PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0); - + // // Find the first IO or MMIO BAR // @@ -333,16 +333,16 @@ GetSerialRegisterBase ( // // Program UART BAR - // + // SerialRegisterBase = SerialPortLibUpdatePciRegister32 ( PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4, - (UINT32)PcdGet64 (PcdSerialRegisterBase), + (UINT32)PcdGet64 (PcdSerialRegisterBase), RegisterBaseMask ); // // Verify that the UART BAR is in the address range decoded by the parent PCI Bridge - // + // if (PcdGetBool (PcdSerialUseMmio)) { if (((SerialRegisterBase >> 16) & 0xfff0) < ParentMemoryBase || ((SerialRegisterBase >> 16) & 0xfff0) > ParentMemoryLimit) { return 0; @@ -352,7 +352,7 @@ GetSerialRegisterBase ( return 0; } } - + // // Enable I/O and MMIO in PCI UART Device if they are not already enabled // @@ -373,7 +373,7 @@ GetSerialRegisterBase ( SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64))); } } - + // // Get PCI Device Info // @@ -381,22 +381,22 @@ GetSerialRegisterBase ( // // Enable I/O or MMIO in PCI Bridge - // Assume Root Bus Numer is Zero. + // Assume Root Bus Numer is Zero. // for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) { // // Compute PCI Lib Address to PCI to PCI Bridge // PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0); - + // // Enable the I/O or MMIO decode windows in the PCI to PCI Bridge // PciOr16 ( - PciLibAddress + PCI_COMMAND_OFFSET, + PciLibAddress + PCI_COMMAND_OFFSET, PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI_COMMAND_IO_SPACE ); - + // // Force D0 state if a Power Management and Status Register is specified // @@ -405,10 +405,10 @@ GetSerialRegisterBase ( PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1)); } } - + BusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET); } - + return SerialRegisterBase; } @@ -442,7 +442,7 @@ SerialPortWritable ( return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) == (B_UART_MSR_DSR | B_UART_MSR_CTS)); } else { // - // Wait for both DSR and CTS to be set OR for DSR to be clear. + // Wait for both DSR and CTS to be set OR for DSR to be clear. // DSR is set if a cable is connected. // CTS is set if it is ok to transmit data // @@ -462,11 +462,11 @@ SerialPortWritable ( /** Initialize the serial device hardware. - + If no initialization is required, then return RETURN_SUCCESS. If the serial device was successfully initialized, then return RETURN_SUCCESS. If the serial device could not be initialized, then return RETURN_DEVICE_ERROR. - + @retval RETURN_SUCCESS The serial device was initialized. @retval RETURN_DEVICE_ERROR The serial device could not be initialized. @@ -480,7 +480,7 @@ SerialPortInitialize ( RETURN_STATUS Status; UINTN SerialRegisterBase; UINT32 Divisor; - UINT32 CurrentDivisor; + UINT32 CurrentDivisor; BOOLEAN Initialized; // @@ -532,7 +532,7 @@ SerialPortInitialize ( // Verify that both the transmit FIFO and the shift register are empty. // while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)); - + // // Configure baud rate // @@ -555,20 +555,20 @@ SerialPortInitialize ( // // Put Modem Control Register(MCR) into its reset state of 0x00. - // + // SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00); return RETURN_SUCCESS; } /** - Write data from buffer to serial device. + Write data from buffer to serial device. - Writes NumberOfBytes data bytes from Buffer to the serial device. + Writes NumberOfBytes data bytes from Buffer to the serial device. The number of bytes actually written to the serial device is returned. If the return value is less than NumberOfBytes, then the write operation failed. - If Buffer is NULL, then ASSERT(). + If Buffer is NULL, then ASSERT(). If NumberOfBytes is zero, then return 0. @@ -576,7 +576,7 @@ SerialPortInitialize ( @param NumberOfBytes Number of bytes to written to the serial device. @retval 0 NumberOfBytes is 0. - @retval >0 The number of bytes written to the serial device. + @retval >0 The number of bytes written to the serial device. If this value is less than NumberOfBytes, then the write operation failed. **/ @@ -600,7 +600,7 @@ SerialPortWrite ( if (SerialRegisterBase ==0) { return 0; } - + if (NumberOfBytes == 0) { // // Flush the hardware @@ -663,7 +663,7 @@ SerialPortWrite ( @param NumberOfBytes Number of bytes to read from the serial device. @retval 0 NumberOfBytes is 0. - @retval >0 The number of bytes read from the serial device. + @retval >0 The number of bytes read from the serial device. If this value is less than NumberOfBytes, then the read operation failed. **/ @@ -688,7 +688,7 @@ SerialPortRead ( } Mcr = (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS); - + for (Result = 0; NumberOfBytes-- != 0; Result++, Buffer++) { // // Wait for the serial port to have some data. @@ -707,13 +707,13 @@ SerialPortRead ( // SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr); } - + // // Read byte from the receive buffer. // *Buffer = SerialPortReadRegister (SerialRegisterBase, R_UART_RXBUF); } - + return Result; } @@ -736,7 +736,7 @@ SerialPortPoll ( ) { UINTN SerialRegisterBase; - + SerialRegisterBase = GetSerialRegisterBase (); if (SerialRegisterBase ==0) { return FALSE; @@ -753,15 +753,15 @@ SerialPortPoll ( SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS)); } return TRUE; - } - + } + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) { // // Set RTS to let the peer send some data // SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) | B_UART_MCR_RTS)); } - + return FALSE; } diff --git a/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf index e8b340cf91..cd758ae4bf 100644 --- a/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +++ b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf @@ -33,7 +33,7 @@ [Sources] BaseSerialPortLib16550.c - + [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl ## CONSUMES From bb0831670f11b710f36e1932d8ba83f1754f74dd Mon Sep 17 00:00:00 2001 From: "Leahy, Leroy P" Date: Mon, 9 May 2016 10:57:08 -0700 Subject: [PATCH 15/26] CorebootModulePkg/BaseSerialPortLib: Set DTR and RTS Ensure communication between the host and the UEFI system running CorebootPayloadPkg. In cases where the host has flow control enabled and the serial connection is providing the flow control signals, the host will not be able to send data to the UEFI system because DTR and RTS are not present. The host may also discard all output data from the UEFI system because DTR is not present. By setting DTR and RTS in the UART initialization code this case works properly. Change-Id: I393f57104d111472cafcae01d4e43d4ea837be3b Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy Reviewed-by: Prince Agyeman --- .../Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c index 45056363c3..ca6db2306a 100644 --- a/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c +++ b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c @@ -554,9 +554,10 @@ SerialPortInitialize ( SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64))); // - // Put Modem Control Register(MCR) into its reset state of 0x00. + // Set RTS and DTR in Modem Control Register(MCR) // - SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00); + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, + EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_READY); return RETURN_SUCCESS; } From a4fdb495dbf4bd6d741f9deb7db29986551ca8ea Mon Sep 17 00:00:00 2001 From: "Leahy, Leroy P" Date: Mon, 9 May 2016 10:57:21 -0700 Subject: [PATCH 16/26] CorebootModulePkg/PciBusNoEnumerationDxe: Remove white space Remove trailing white space from PciEnumeratorSupport.c. Change-Id: Ia2f354151d46c09b140e2b42609d76fbbf8333f9 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy Reviewed-by: Prince Agyeman --- .../PciEnumeratorSupport.c | 92 +++++++++---------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c b/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c index 27311fd1e2..0b0247dffc 100644 --- a/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c +++ b/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c @@ -2,18 +2,18 @@ Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.
(C) Copyright 2015 Hewlett Packard Enterprise Development LP
-This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD License -which accompanies this distribution. The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. Module Name: PciEnumeratorSupport.c - + Abstract: PCI Bus Driver @@ -24,17 +24,17 @@ Revision History #include "PciBus.h" -EFI_STATUS +EFI_STATUS InitializePPB ( - IN PCI_IO_DEVICE *PciIoDevice + IN PCI_IO_DEVICE *PciIoDevice ); -EFI_STATUS +EFI_STATUS InitializeP2C ( - IN PCI_IO_DEVICE *PciIoDevice + IN PCI_IO_DEVICE *PciIoDevice ); -PCI_IO_DEVICE* +PCI_IO_DEVICE* CreatePciIoDevice ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, IN PCI_TYPE00 *Pci, @@ -72,12 +72,12 @@ PciSearchDevice ( ); -EFI_STATUS +EFI_STATUS DetermineDeviceAttribute ( IN PCI_IO_DEVICE *PciIoDevice ); -EFI_STATUS +EFI_STATUS BarExisted ( IN PCI_IO_DEVICE *PciIoDevice, IN UINTN Offset, @@ -90,10 +90,10 @@ BarExisted ( EFI_DEVICE_PATH_PROTOCOL* CreatePciDevicePath( IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath, - IN PCI_IO_DEVICE *PciIoDevice + IN PCI_IO_DEVICE *PciIoDevice ); -PCI_IO_DEVICE* +PCI_IO_DEVICE* GatherDeviceInfo ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, IN PCI_TYPE00 *Pci, @@ -102,7 +102,7 @@ GatherDeviceInfo ( UINT8 Func ); -PCI_IO_DEVICE* +PCI_IO_DEVICE* GatherPPBInfo ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, IN PCI_TYPE00 *Pci, @@ -255,7 +255,7 @@ Returns: if (EFI_ERROR (Status)) { return Status; } - + // // If the PCI bridge is initialized then enumerate the next level bus // @@ -368,15 +368,15 @@ Returns: if (!PciIoDevice) { return EFI_OUT_OF_RESOURCES; } - + // // Create a device path for this PCI device and store it into its private data // CreatePciDevicePath( Bridge->DevicePath, - PciIoDevice + PciIoDevice ); - + // // Detect this function has option rom // @@ -389,8 +389,8 @@ Returns: } ResetPowerManagementFeature (PciIoDevice); - - } + + } else { PciRomGetRomResourceFromPciOptionRomTable ( &gPciBusDriverBinding, @@ -399,7 +399,7 @@ Returns: ); } - + // // Insert it into a global tree for future reference // @@ -509,7 +509,7 @@ Returns: if (!PciIoDevice) { return NULL; } - + if (gFullEnumeration) { PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED); @@ -593,7 +593,7 @@ Returns: --*/ { PCI_IO_DEVICE *PciIoDevice; - + PciIoDevice = CreatePciIoDevice ( PciRootBridgeIo, Pci, @@ -619,7 +619,7 @@ Returns: // P2C only has one bar that is in 0x10 // PciParseBar(PciIoDevice, 0x10, 0); - + PciIoDevice->Decodes = EFI_BRIDGE_MEM32_DECODE_SUPPORTED | EFI_BRIDGE_PMEM32_DECODE_SUPPORTED | EFI_BRIDGE_IO32_DECODE_SUPPORTED; @@ -742,7 +742,7 @@ DetermineDeviceAttribute ( /*++ Routine Description: - + Determine the related attributes of all devices under a Root Bridge Arguments: @@ -799,7 +799,7 @@ Returns: PciReadCommandRegister(PciIoDevice, &Command); - + if (Command & EFI_PCI_COMMAND_IO_SPACE) { PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_IO; } @@ -812,7 +812,7 @@ Returns: PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_BUS_MASTER; } - if (IS_PCI_BRIDGE (&(PciIoDevice->Pci)) || + if (IS_PCI_BRIDGE (&(PciIoDevice->Pci)) || IS_CARDBUS_BRIDGE (&(PciIoDevice->Pci))){ // @@ -825,12 +825,12 @@ Returns: // // Determine whether the ISA bit is set // If ISA Enable on Bridge is set, the PPB - // will block forwarding 0x100-0x3ff for each 1KB in the + // will block forwarding 0x100-0x3ff for each 1KB in the // first 64KB I/O range. // if ((BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA) != 0) { PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_IO; - } + } // // Determine whether the VGA bit is set @@ -844,13 +844,13 @@ Returns: } // - // if the palette snoop bit is set, then the brige is set to + // if the palette snoop bit is set, then the brige is set to // decode palette IO write // if (Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) { PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO; } - } + } return EFI_SUCCESS; } @@ -997,7 +997,7 @@ Returns: // // Fix the length to support some spefic 64 bit BAR // - Value |= ((UINT32)(-1) << HighBitSet32 (Value)); + Value |= ((UINT32)(-1) << HighBitSet32 (Value)); // // Calculate the size of 64bit bar @@ -1021,7 +1021,7 @@ Returns: break; } } - + // // Check the length again so as to keep compatible with some special bars // @@ -1030,7 +1030,7 @@ Returns: PciIoDevice->PciBar[BarIndex].BaseAddress = 0; PciIoDevice->PciBar[BarIndex].Alignment = 0; } - + // // Increment number of bar // @@ -1220,7 +1220,7 @@ PciEnumeratorLight ( Routine Description: - This routine is used to enumerate entire pci bus system + This routine is used to enumerate entire pci bus system in a given platform Arguments: @@ -1255,11 +1255,11 @@ Returns: // Open the IO Abstraction(s) needed to perform the supported test // Status = gBS->OpenProtocol ( - Controller , - &gEfiDevicePathProtocolGuid, + Controller , + &gEfiDevicePathProtocolGuid, (VOID **)&ParentDevicePath, - gPciBusDriverBinding.DriverBindingHandle, - Controller, + gPciBusDriverBinding.DriverBindingHandle, + Controller, EFI_OPEN_PROTOCOL_BY_DRIVER ); if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) { @@ -1282,7 +1282,7 @@ Returns: } // - // Load all EFI Drivers from all PCI Option ROMs behind the PCI Root Bridge + // Load all EFI Drivers from all PCI Option ROMs behind the PCI Root Bridge // Status = PciRomLoadEfiDriversFromOptionRomTable (&gPciBusDriverBinding, PciRootBridgeIo); @@ -1353,9 +1353,9 @@ Arguments: MinBus - The min bus. MaxBus - The max bus. BusRange - The bus range. - + Returns: - + Status Code. --*/ From deac23ab9678722c84c4ea0f70ff2bbbf04ff3aa Mon Sep 17 00:00:00 2001 From: "Leahy, Leroy P" Date: Mon, 9 May 2016 10:57:35 -0700 Subject: [PATCH 17/26] CorebootPayloadPkg/PciBusNoEnumerationDxe: Skip disabled devices Skip non-bridge devices which are not enabled either for memory or I/O access. Change-Id: I1a39c69a8556b6b9cefd1a2bb191f7e0744ddfb0 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy Reviewed-by: Prince Agyeman --- .../PciBusNoEnumerationDxe/PciEnumeratorSupport.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c b/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c index 0b0247dffc..58b9385a37 100644 --- a/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c +++ b/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c @@ -226,6 +226,15 @@ Returns: if (!EFI_ERROR (Status)) { + // + // Skip non-bridge devices which are not enabled + // + if (((Pci.Hdr.Command & (EFI_PCI_COMMAND_IO_SPACE + | EFI_PCI_COMMAND_MEMORY_SPACE)) == 0) + && (!(IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci)))) { + continue; + } + // // Collect all the information about the PCI device discovered // From 24ca2f3507056e6a86cb0c0f088bba96cd117d71 Mon Sep 17 00:00:00 2001 From: "Leahy, Leroy P" Date: Mon, 9 May 2016 10:57:55 -0700 Subject: [PATCH 18/26] CorebootPayloadPkg/PlatformBdsLib: Pass more serial parameters Pass the serial port baudrate, register stride, input clock rate and ID from coreboot to CorebootPayloadPkg. Change-Id: I37111d23216e4effa2909337af7e8a6de36b61f7 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy Reviewed-by: Prince Agyeman --- CorebootModulePkg/Include/Coreboot.h | 17 +++++- .../Include/Library/CbParseLib.h | 26 +++++---- .../Library/CbParseLib/CbParseLib.c | 32 ++++++++--- .../Library/PlatformBdsLib/BdsPlatform.c | 5 ++ .../Library/PlatformBdsLib/PlatformBdsLib.inf | 6 +++ .../Library/PlatformHookLib/PlatformHookLib.c | 53 ++++++++++++++++++- .../PlatformHookLib/PlatformHookLib.inf | 12 +++-- 7 files changed, 128 insertions(+), 23 deletions(-) diff --git a/CorebootModulePkg/Include/Coreboot.h b/CorebootModulePkg/Include/Coreboot.h index f2f18be2cc..784e0b128a 100644 --- a/CorebootModulePkg/Include/Coreboot.h +++ b/CorebootModulePkg/Include/Coreboot.h @@ -80,7 +80,7 @@ struct imd_root { UINT32 max_entries; UINT32 num_entries; UINT32 flags; - UINT32 entry_align; + UINT32 entry_align; UINT32 max_offset; struct imd_entry entries[0]; }; @@ -165,6 +165,21 @@ struct cb_serial { UINT32 type; UINT32 baseaddr; UINT32 baud; + UINT32 regwidth; + + // Crystal or input frequency to the chip containing the UART. + // Provide the board specific details to allow the payload to + // initialize the chip containing the UART and make independent + // decisions as to which dividers to select and their values + // to eventually arrive at the desired console baud-rate. + UINT32 input_hertz; + + // UART PCI address: bus, device, function + // 1 << 31 - Valid bit, PCI UART in use + // Bus << 20 + // Device << 15 + // Function << 12 + UINT32 uart_pci_addr; }; #define CB_TAG_CONSOLE 0x00010 diff --git a/CorebootModulePkg/Include/Library/CbParseLib.h b/CorebootModulePkg/Include/Library/CbParseLib.h index 170375b365..a023246d71 100644 --- a/CorebootModulePkg/Include/Library/CbParseLib.h +++ b/CorebootModulePkg/Include/Library/CbParseLib.h @@ -30,7 +30,7 @@ CbParseMemoryInfo ( IN UINT64* pLowMemorySize, IN UINT64* pHighMemorySize ); - + /** Acquire the coreboot memory table with the given table id @@ -45,11 +45,11 @@ CbParseMemoryInfo ( **/ RETURN_STATUS CbParseCbMemTable ( - IN UINT32 TableId, + IN UINT32 TableId, IN VOID** pMemTable, IN UINT32* pMemTableSize ); - + /** Acquire the acpi table from coreboot @@ -66,7 +66,7 @@ CbParseAcpiTable ( IN VOID** pMemTable, IN UINT32* pMemTableSize ); - + /** Acquire the smbios table from coreboot @@ -83,7 +83,7 @@ CbParseSmbiosTable ( IN VOID** pMemTable, IN UINT32* pMemTableSize ); - + /** Find the required fadt information @@ -107,13 +107,16 @@ CbParseFadtInfo ( IN UINTN* pPmEvtReg, IN UINTN* pPmGpeEnReg ); - + /** Find the serial port information @param pRegBase Pointer to the base address of serial port registers @param pRegAccessType Pointer to the access type of serial port registers + @param pRegWidth Pointer to the register width in bytes @param pBaudrate Pointer to the serial port baudrate + @param pInputHertz Pointer to the input clock frequency + @param pUartPciAddr Pointer to the UART PCI bus, dev and func address @retval RETURN_SUCCESS Successfully find the serial port information. @retval RETURN_NOT_FOUND Failed to find the serial port information . @@ -121,9 +124,12 @@ CbParseFadtInfo ( **/ RETURN_STATUS CbParseSerialInfo ( - IN UINT32* pRegBase, - IN UINT32* pRegAccessType, - IN UINT32* pBaudrate + OUT UINT32 *pRegBase, + OUT UINT32 *pRegAccessType, + OUT UINT32 *pRegWidth, + OUT UINT32 *pBaudrate, + OUT UINT32 *pInputHertz, + OUT UINT32 *pUartPciAddr ); /** @@ -141,7 +147,7 @@ CbParseGetCbHeader ( IN UINTN Level, IN VOID** HeaderPtr ); - + /** Find the video frame buffer information diff --git a/CorebootModulePkg/Library/CbParseLib/CbParseLib.c b/CorebootModulePkg/Library/CbParseLib/CbParseLib.c index 377abf3c67..7c81a51054 100644 --- a/CorebootModulePkg/Library/CbParseLib/CbParseLib.c +++ b/CorebootModulePkg/Library/CbParseLib/CbParseLib.c @@ -33,7 +33,7 @@ @return the UNIT64 value after convertion. **/ -UINT64 +UINT64 cb_unpack64 ( IN struct cbuint64 val ) @@ -469,12 +469,12 @@ CbParseFadtInfo ( } DEBUG ((EFI_D_INFO, "Reset Value 0x%x\n", Fadt->ResetValue)); - if (pPmEvtReg != NULL) { + if (pPmEvtReg != NULL) { *pPmEvtReg = Fadt->Pm1aEvtBlk; DEBUG ((EFI_D_INFO, "PmEvt Reg 0x%x\n", Fadt->Pm1aEvtBlk)); } - if (pPmGpeEnReg != NULL) { + if (pPmGpeEnReg != NULL) { *pPmGpeEnReg = Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2; DEBUG ((EFI_D_INFO, "PmGpeEn Reg 0x%x\n", *pPmGpeEnReg)); } @@ -519,15 +519,15 @@ CbParseFadtInfo ( *pResetValue = Fadt->ResetValue; DEBUG ((EFI_D_ERROR, "Reset Value 0x%x\n", Fadt->ResetValue)); - if (pPmEvtReg != NULL) { + if (pPmEvtReg != NULL) { *pPmEvtReg = Fadt->Pm1aEvtBlk; DEBUG ((EFI_D_INFO, "PmEvt Reg 0x%x\n", Fadt->Pm1aEvtBlk)); } - if (pPmGpeEnReg != NULL) { + if (pPmGpeEnReg != NULL) { *pPmGpeEnReg = Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2; DEBUG ((EFI_D_INFO, "PmGpeEn Reg 0x%x\n", *pPmGpeEnReg)); - } + } return RETURN_SUCCESS; } } @@ -541,7 +541,10 @@ CbParseFadtInfo ( @param pRegBase Pointer to the base address of serial port registers @param pRegAccessType Pointer to the access type of serial port registers + @param pRegWidth Pointer to the register width in bytes @param pBaudrate Pointer to the serial port baudrate + @param pInputHertz Pointer to the input clock frequency + @param pUartPciAddr Pointer to the UART PCI bus, dev and func address @retval RETURN_SUCCESS Successfully find the serial port information. @retval RETURN_NOT_FOUND Failed to find the serial port information . @@ -551,7 +554,10 @@ RETURN_STATUS CbParseSerialInfo ( OUT UINT32 *pRegBase, OUT UINT32 *pRegAccessType, - OUT UINT32 *pBaudrate + OUT UINT32 *pRegWidth, + OUT UINT32 *pBaudrate, + OUT UINT32 *pInputHertz, + OUT UINT32 *pUartPciAddr ) { struct cb_serial *CbSerial; @@ -569,6 +575,10 @@ CbParseSerialInfo ( *pRegBase = CbSerial->baseaddr; } + if (pRegWidth != NULL) { + *pRegWidth = CbSerial->regwidth; + } + if (pRegAccessType != NULL) { *pRegAccessType = CbSerial->type; } @@ -577,6 +587,14 @@ CbParseSerialInfo ( *pBaudrate = CbSerial->baud; } + if (pInputHertz != NULL) { + *pInputHertz = CbSerial->input_hertz; + } + + if (pUartPciAddr != NULL) { + *pUartPciAddr = CbSerial->uart_pci_addr; + } + return RETURN_SUCCESS; } diff --git a/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c b/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c index ef6a1b26ca..c0a2b19645 100644 --- a/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c +++ b/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c @@ -78,6 +78,10 @@ PlatformBdsInit ( VOID ) { + gUartDeviceNode.BaudRate = PcdGet64 (PcdUartDefaultBaudRate); + gUartDeviceNode.DataBits = PcdGet8 (PcdUartDefaultDataBits); + gUartDeviceNode.Parity = PcdGet8 (PcdUartDefaultParity); + gUartDeviceNode.StopBits = PcdGet8 (PcdUartDefaultStopBits); } @@ -786,6 +790,7 @@ PlatformBdsPolicyBehavior ( DEBUG ((EFI_D_INFO, "PlatformBdsPolicyBehavior\n")); + PlatformBdsInit(); ConnectRootBridge (); // diff --git a/CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf b/CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf index 9c102721d5..b1a79b866c 100644 --- a/CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf +++ b/CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf @@ -45,6 +45,12 @@ DebugLib PcdLib GenericBdsLib + PlatformHookLib + [Pcd] gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits diff --git a/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c b/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c index 8449997050..b1cfb8e2c0 100644 --- a/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c +++ b/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c @@ -14,10 +14,23 @@ #include #include +#include #include #include #include +typedef struct { + UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries. + UINT16 DeviceId; ///< Device ID to match the PCI device + UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz + UINT64 Offset; ///< The byte offset into to the BAR + UINT8 BarIndex; ///< Which BAR to get the UART base address + UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte. + UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes. + UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes. + UINT8 Reserved[2]; +} PCI_SERIAL_PARAMETER; + /** Performs platform specific initialization required for the CPU to access the hardware associated with a SerialPortLib instance. This function does @@ -38,8 +51,16 @@ PlatformHookSerialPortInitialize ( RETURN_STATUS Status; UINT32 SerialRegBase; UINT32 SerialRegAccessType; + UINT32 BaudRate; + UINT32 RegWidth; + UINT32 InputHertz; + UINT32 PayloadParam; + UINT32 DeviceVendor; + PCI_SERIAL_PARAMETER *SerialParam; - Status = CbParseSerialInfo (&SerialRegBase, &SerialRegAccessType, NULL); + Status = CbParseSerialInfo (&SerialRegBase, &SerialRegAccessType, + &RegWidth, &BaudRate, &InputHertz, + &PayloadParam); if (RETURN_ERROR (Status)) { return Status; } @@ -57,6 +78,34 @@ PlatformHookSerialPortInitialize ( return Status; } + Status = PcdSet32S (PcdSerialRegisterStride, RegWidth); + if (RETURN_ERROR (Status)) { + return Status; + } + + Status = PcdSet32S (PcdSerialBaudRate, BaudRate); + if (RETURN_ERROR (Status)) { + return Status; + } + + Status = PcdSet64S (PcdUartDefaultBaudRate, BaudRate); + if (RETURN_ERROR (Status)) { + return Status; + } + + Status = PcdSet32S (PcdSerialClockRate, InputHertz); + if (RETURN_ERROR (Status)) { + return Status; + } + + if (PayloadParam >= 0x80000000) { + DeviceVendor = PciRead32 (PayloadParam & 0x0ffff000); + SerialParam = PcdGetPtr(PcdPciSerialParameters); + SerialParam->VendorId = (UINT16)DeviceVendor; + SerialParam->DeviceId = DeviceVendor >> 16; + SerialParam->ClockRate = InputHertz; + SerialParam->RegisterStride = (UINT8)RegWidth; + } + return RETURN_SUCCESS; } - diff --git a/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf b/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf index e5db75fa95..3230105901 100644 --- a/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf +++ b/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf @@ -19,6 +19,7 @@ MODULE_TYPE = BASE VERSION_STRING = 1.0 LIBRARY_CLASS = PlatformHookLib + CONSTRUCTOR = PlatformHookSerialPortInitialize [Sources] PlatformHookLib.c @@ -26,6 +27,7 @@ [LibraryClasses] CbParseLib PcdLib + PciLib [Packages] MdePkg/MdePkg.dec @@ -33,6 +35,10 @@ CorebootModulePkg/CorebootModulePkg.dec [Pcd] - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## PRODUCES - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES - + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## PRODUCES + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters ## PRODUCES From 2d063646b9f566f227db5df535cf72bec2f34649 Mon Sep 17 00:00:00 2001 From: Linn Crosetto Date: Tue, 10 May 2016 12:16:12 -0600 Subject: [PATCH 19/26] ArmVirtPkg: set PcdMaxVariableSize and PcdMaxAuthVariableSize To support UEFI Secure Boot and the Linux persistent store with UEFI variables, set PcdMaxVariableSize to 0x2000 bytes as is done in OvmfPkg. For reference, the related Ovmf commits: 8cee3de7 2d441ca9 Also increase the maximum size for Authenticated variables in order to handle a larger Signature List size as is done in OvmfPkg. Related Ovmf commit: f5404a3e Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Linn Crosetto Reviewed-by: Laszlo Ersek --- ArmVirtPkg/ArmVirtQemu.dsc | 2 ++ ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 ++ 2 files changed, 4 insertions(+) diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc index 1d48cd0fca..d07593b45e 100644 --- a/ArmVirtPkg/ArmVirtQemu.dsc +++ b/ArmVirtPkg/ArmVirtQemu.dsc @@ -111,6 +111,8 @@ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x4007c000 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 # Size of the region used by UEFI in permanent memory (Reserved 64MB) gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000 diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc index d4134f169c..65e6c87520 100644 --- a/ArmVirtPkg/ArmVirtQemuKernel.dsc +++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc @@ -100,6 +100,8 @@ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x4007c000 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 # Size of the region used by UEFI in permanent memory (Reserved 64MB) gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000 From 814f4306d8f72c56512765de4de36bce774ce62a Mon Sep 17 00:00:00 2001 From: Ruiyu Ni Date: Fri, 29 Apr 2016 17:41:11 +0800 Subject: [PATCH 20/26] MdeModulePkg/PciHostBridgeDxe: Don't miss prefetchable MMIO aperture Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Reviewed-by: Laszlo Ersek --- MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index cda9b49b39..9f756e4c56 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -170,7 +170,8 @@ CreateRootBridge ( CopyMem (&RootBridge->Io, &Bridge->Io, sizeof (PCI_ROOT_BRIDGE_APERTURE)); CopyMem (&RootBridge->Mem, &Bridge->Mem, sizeof (PCI_ROOT_BRIDGE_APERTURE)); CopyMem (&RootBridge->MemAbove4G, &Bridge->MemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE)); - + CopyMem (&RootBridge->PMem, &Bridge->PMem, sizeof (PCI_ROOT_BRIDGE_APERTURE)); + CopyMem (&RootBridge->PMemAbove4G, &Bridge->PMemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE)); for (Index = TypeIo; Index < TypeMax; Index++) { RootBridge->ResAllocNode[Index].Type = Index; From f9607bef04a9abb698f9f8b4518b7955dc326521 Mon Sep 17 00:00:00 2001 From: Ruiyu Ni Date: Fri, 29 Apr 2016 17:38:51 +0800 Subject: [PATCH 21/26] MdeModulePkg/PciHostBridgeDxe: Fix a Base/Limit comparing bug When the aperture base equals to aperture limit, the old code treats the aperture as non-existent. It's not correct because it indicates a range starting with base and the length is 1. The new code corrects the comparing bug. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Cc: Jeff Fan Reviewed-by: Laszlo Ersek --- .../Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 4 ++-- .../Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 24 +++++++++---------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c index 50f1407e7a..07ed54b08e 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c @@ -393,7 +393,7 @@ InitializePciHostBridge ( continue; } - if (RootBridges[Index].Io.Limit > RootBridges[Index].Io.Base) { + if (RootBridges[Index].Io.Base <= RootBridges[Index].Io.Limit) { Status = AddIoSpace ( RootBridges[Index].Io.Base, RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base + 1 @@ -413,7 +413,7 @@ InitializePciHostBridge ( MemApertures[3] = &RootBridges[Index].PMemAbove4G; for (MemApertureIndex = 0; MemApertureIndex < sizeof (MemApertures) / sizeof (MemApertures[0]); MemApertureIndex++) { - if (MemApertures[MemApertureIndex]->Limit > MemApertures[MemApertureIndex]->Base) { + if (MemApertures[MemApertureIndex]->Base <= MemApertures[MemApertureIndex]->Limit) { Status = AddMemoryMappedIoSpace ( MemApertures[MemApertureIndex]->Base, MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1, diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index 9f756e4c56..dbb415ac2d 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -95,25 +95,25 @@ CreateRootBridge ( // // Make sure Mem and MemAbove4G apertures are valid // - if (Bridge->Mem.Base < Bridge->Mem.Limit) { + if (Bridge->Mem.Base <= Bridge->Mem.Limit) { ASSERT (Bridge->Mem.Limit < SIZE_4GB); if (Bridge->Mem.Limit >= SIZE_4GB) { return NULL; } } - if (Bridge->MemAbove4G.Base < Bridge->MemAbove4G.Limit) { + if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) { ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB); if (Bridge->MemAbove4G.Base < SIZE_4GB) { return NULL; } } - if (Bridge->PMem.Base < Bridge->PMem.Limit) { + if (Bridge->PMem.Base <= Bridge->PMem.Limit) { ASSERT (Bridge->PMem.Limit < SIZE_4GB); if (Bridge->PMem.Limit >= SIZE_4GB) { return NULL; } } - if (Bridge->PMemAbove4G.Base < Bridge->PMemAbove4G.Limit) { + if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) { ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB); if (Bridge->PMemAbove4G.Base < SIZE_4GB) { return NULL; @@ -126,10 +126,10 @@ CreateRootBridge ( // support separate windows for Non-prefetchable and Prefetchable // memory. // - ASSERT (Bridge->PMem.Base >= Bridge->PMem.Limit); - ASSERT (Bridge->PMemAbove4G.Base >= Bridge->PMemAbove4G.Limit); - if ((Bridge->PMem.Base < Bridge->PMem.Limit) || - (Bridge->PMemAbove4G.Base < Bridge->PMemAbove4G.Limit) + ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit); + ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit); + if ((Bridge->PMem.Base <= Bridge->PMem.Limit) || + (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) ) { return NULL; } @@ -140,10 +140,10 @@ CreateRootBridge ( // If this bit is not set, then the PCI Root Bridge does not support // 64 bit memory windows. // - ASSERT (Bridge->MemAbove4G.Base >= Bridge->MemAbove4G.Limit); - ASSERT (Bridge->PMemAbove4G.Base >= Bridge->PMemAbove4G.Limit); - if ((Bridge->MemAbove4G.Base < Bridge->MemAbove4G.Limit) || - (Bridge->PMemAbove4G.Base < Bridge->PMemAbove4G.Limit) + ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit); + ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit); + if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) || + (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) ) { return NULL; } From c3933ccbbad7cc00f77f01acea19f6ca4de97bac Mon Sep 17 00:00:00 2001 From: Ruiyu Ni Date: Sat, 30 Apr 2016 09:34:54 +0800 Subject: [PATCH 22/26] OvmfPkg/PciHostBridgeLib: Set correct Base/Limit for absent resource In order to match the previous commit, Base must be strictly larger than Limit if some type of aperture is not available on a PCI root bridge. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Reviewed-by: Laszlo Ersek --- OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c index 1d3d10ad73..9e01498187 100644 --- a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -125,11 +125,11 @@ InitRootBridge ( RootBus->DmaAbove4G = FALSE; RootBus->AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM; - RootBus->PMem.Base = 0; + RootBus->PMem.Base = MAX_UINT64; RootBus->PMem.Limit = 0; - RootBus->PMemAbove4G.Base = 0; + RootBus->PMemAbove4G.Base = MAX_UINT64; RootBus->PMemAbove4G.Limit = 0; - RootBus->MemAbove4G.Base = 0; + RootBus->MemAbove4G.Base = MAX_UINT64; RootBus->MemAbove4G.Limit = 0; if (PcdGet64 (PcdPciMmio64Size) > 0) { From c5be19f378216a07c7783e07973d976407885e75 Mon Sep 17 00:00:00 2001 From: Ruiyu Ni Date: Fri, 29 Apr 2016 16:43:56 +0800 Subject: [PATCH 23/26] MdeModulePkg/PciHostBridgeLib: Add ResourceAssigned field Some platform doesn't require PciBus driver to assign resource to PCI devices which causes PciRootBridgeIo.Configuration() cannot return correct resource information to caller. When resource assignment by PciBus is not mandatory, only light version of PCI bus enumeration is performed, which only collects the device resource consumption and publishes the PciIo instance. The corresponding logic is in PciEnumeratorLight() in PciBus driver. But PciEnumeratorLight() still depends on PciRootBridgeIo.Configuration() returns the starting bus number in order to search down to find all PCI devices under the root bridge. When ResourceAssigned in PCI_ROOT_BRIDGE returned by PciHostBridgeGetRootBridges() is TRUE, PciHostBridge driver treats the Bus/Io/Mem/MemAbove4G/PMem/PMemAbove4G as the resource that are *actually assigned* to the root bridge, instead of the resource that *can be assigned* to the root bridge. So that PciRootBridgeIo.Configuration() can return the correct information. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Reviewed-by: Laszlo Ersek --- MdeModulePkg/Include/Library/PciHostBridgeLib.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MdeModulePkg/Include/Library/PciHostBridgeLib.h b/MdeModulePkg/Include/Library/PciHostBridgeLib.h index eb45cfdd79..d42e9ecdd7 100644 --- a/MdeModulePkg/Include/Library/PciHostBridgeLib.h +++ b/MdeModulePkg/Include/Library/PciHostBridgeLib.h @@ -38,6 +38,8 @@ typedef struct { ///< Extended (4096-byte) Configuration Space. ///< When TRUE, the root bridge supports ///< 256-byte Configuration Space only. + BOOLEAN ResourceAssigned; ///< Resource assignment status of the root bridge. + ///< Set to TRUE if Bus/IO/MMIO resources for root bridge have been assigned. UINT64 AllocationAttributes; ///< Allocation attributes. ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes() From 401f8cd110f7eec7684d948df29e00b44b1468d9 Mon Sep 17 00:00:00 2001 From: Ruiyu Ni Date: Mon, 9 May 2016 13:49:27 +0800 Subject: [PATCH 24/26] MdeModulePkg/PciHostBridgeDxe: Honor ResourceAssigned Change PciHostBridgeDxe driver to not install the PciHostBridgeResourceAllocation protocol and let PciRootBridgeIo.Configuration() return the correct PCI resource assignment information when the ResourceAssigned is TRUE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Cc: Jeff Fan Reviewed-by: Laszlo Ersek --- .../Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 92 +++++++++++++----- .../Bus/Pci/PciHostBridgeDxe/PciRootBridge.h | 4 +- .../Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 96 ++++++++++++------- 3 files changed, 134 insertions(+), 58 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c index 07ed54b08e..c866e88016 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c @@ -338,6 +338,8 @@ InitializePciHostBridge ( UINTN Index; PCI_ROOT_BRIDGE_APERTURE *MemApertures[4]; UINTN MemApertureIndex; + BOOLEAN ResourceAssigned; + LIST_ENTRY *Link; RootBridges = PciHostBridgeGetRootBridges (&RootBridgeCount); if ((RootBridges == NULL) || (RootBridgeCount == 0)) { @@ -358,27 +360,7 @@ InitializePciHostBridge ( HostBridge->Signature = PCI_HOST_BRIDGE_SIGNATURE; HostBridge->CanRestarted = TRUE; InitializeListHead (&HostBridge->RootBridges); - - HostBridge->ResAlloc.NotifyPhase = NotifyPhase; - HostBridge->ResAlloc.GetNextRootBridge = GetNextRootBridge; - HostBridge->ResAlloc.GetAllocAttributes = GetAttributes; - HostBridge->ResAlloc.StartBusEnumeration = StartBusEnumeration; - HostBridge->ResAlloc.SetBusNumbers = SetBusNumbers; - HostBridge->ResAlloc.SubmitResources = SubmitResources; - HostBridge->ResAlloc.GetProposedResources = GetProposedResources; - HostBridge->ResAlloc.PreprocessController = PreprocessController; - - Status = gBS->InstallMultipleProtocolInterfaces ( - &HostBridge->Handle, - &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc, - NULL - ); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR (Status)) { - FreePool (HostBridge); - PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount); - return Status; - } + ResourceAssigned = FALSE; // // Create Root Bridge Device Handle in this Host Bridge @@ -387,18 +369,39 @@ InitializePciHostBridge ( // // Create Root Bridge Handle Instance // - RootBridge = CreateRootBridge (&RootBridges[Index], HostBridge->Handle); + RootBridge = CreateRootBridge (&RootBridges[Index]); ASSERT (RootBridge != NULL); if (RootBridge == NULL) { continue; } + // + // Make sure all root bridges share the same ResourceAssigned value. + // + if (Index == 0) { + ResourceAssigned = RootBridges[Index].ResourceAssigned; + } else { + ASSERT (ResourceAssigned == RootBridges[Index].ResourceAssigned); + } + if (RootBridges[Index].Io.Base <= RootBridges[Index].Io.Limit) { Status = AddIoSpace ( RootBridges[Index].Io.Base, RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base + 1 ); ASSERT_EFI_ERROR (Status); + if (ResourceAssigned) { + Status = gDS->AllocateIoSpace ( + EfiGcdAllocateAddress, + EfiGcdIoTypeIo, + 0, + RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base + 1, + &RootBridges[Index].Io.Base, + gImageHandle, + NULL + ); + ASSERT_EFI_ERROR (Status); + } } // @@ -428,11 +431,55 @@ InitializePciHostBridge ( if (EFI_ERROR (Status)) { DEBUG ((DEBUG_WARN, "PciHostBridge driver failed to set EFI_MEMORY_UC to MMIO aperture - %r.\n", Status)); } + if (ResourceAssigned) { + Status = gDS->AllocateMemorySpace ( + EfiGcdAllocateAddress, + EfiGcdMemoryTypeMemoryMappedIo, + 0, + MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1, + &MemApertures[MemApertureIndex]->Base, + gImageHandle, + NULL + ); + ASSERT_EFI_ERROR (Status); + } } } // // Insert Root Bridge Handle Instance // + InsertTailList (&HostBridge->RootBridges, &RootBridge->Link); + } + + // + // When resources were assigned, it's not needed to expose + // PciHostBridgeResourceAllocation protocol. + // + if (!ResourceAssigned) { + HostBridge->ResAlloc.NotifyPhase = NotifyPhase; + HostBridge->ResAlloc.GetNextRootBridge = GetNextRootBridge; + HostBridge->ResAlloc.GetAllocAttributes = GetAttributes; + HostBridge->ResAlloc.StartBusEnumeration = StartBusEnumeration; + HostBridge->ResAlloc.SetBusNumbers = SetBusNumbers; + HostBridge->ResAlloc.SubmitResources = SubmitResources; + HostBridge->ResAlloc.GetProposedResources = GetProposedResources; + HostBridge->ResAlloc.PreprocessController = PreprocessController; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &HostBridge->Handle, + &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc, + NULL + ); + ASSERT_EFI_ERROR (Status); + } + + for (Link = GetFirstNode (&HostBridge->RootBridges) + ; !IsNull (&HostBridge->RootBridges, Link) + ; Link = GetNextNode (&HostBridge->RootBridges, Link) + ) { + RootBridge = ROOT_BRIDGE_FROM_LINK (Link); + RootBridge->RootBridgeIo.ParentHandle = HostBridge->Handle; + Status = gBS->InstallMultipleProtocolInterfaces ( &RootBridge->Handle, &gEfiDevicePathProtocolGuid, RootBridge->DevicePath, @@ -440,7 +487,6 @@ InitializePciHostBridge ( NULL ); ASSERT_EFI_ERROR (Status); - InsertTailList (&HostBridge->RootBridges, &RootBridge->Link); } PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount); return Status; diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h index aa3f43a511..13185b41ac 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h @@ -90,15 +90,13 @@ typedef struct { Construct the Pci Root Bridge instance. @param Bridge The root bridge instance. - @param HostBridgeHandle Handle to the HostBridge. @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created or NULL if creation fails. **/ PCI_ROOT_BRIDGE_INSTANCE * CreateRootBridge ( - IN PCI_ROOT_BRIDGE *Bridge, - IN EFI_HANDLE HostBridgeHandle + IN PCI_ROOT_BRIDGE *Bridge ); // diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index dbb415ac2d..78811419bf 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -59,20 +59,19 @@ UINT8 mOutStride[] = { Construct the Pci Root Bridge instance. @param Bridge The root bridge instance. - @param HostBridgeHandle Handle to the HostBridge. @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created or NULL if creation fails. **/ PCI_ROOT_BRIDGE_INSTANCE * CreateRootBridge ( - IN PCI_ROOT_BRIDGE *Bridge, - IN EFI_HANDLE HostBridgeHandle + IN PCI_ROOT_BRIDGE *Bridge ) { PCI_ROOT_BRIDGE_INSTANCE *RootBridge; PCI_RESOURCE_TYPE Index; CHAR16 *DevicePathStr; + PCI_ROOT_BRIDGE_APERTURE *Aperture; DevicePathStr = NULL; @@ -120,32 +119,37 @@ CreateRootBridge ( } } - if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) { - // - // If this bit is set, then the PCI Root Bridge does not - // support separate windows for Non-prefetchable and Prefetchable - // memory. - // - ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit); - ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit); - if ((Bridge->PMem.Base <= Bridge->PMem.Limit) || - (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) - ) { - return NULL; + // + // Ignore AllocationAttributes when resources were already assigned. + // + if (!Bridge->ResourceAssigned) { + if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) { + // + // If this bit is set, then the PCI Root Bridge does not + // support separate windows for Non-prefetchable and Prefetchable + // memory. + // + ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit); + ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit); + if ((Bridge->PMem.Base <= Bridge->PMem.Limit) || + (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) + ) { + return NULL; + } } - } - if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) == 0) { - // - // If this bit is not set, then the PCI Root Bridge does not support - // 64 bit memory windows. - // - ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit); - ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit); - if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) || - (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) - ) { - return NULL; + if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) == 0) { + // + // If this bit is not set, then the PCI Root Bridge does not support + // 64 bit memory windows. + // + ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit); + ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit); + if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) || + (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) + ) { + return NULL; + } } } @@ -174,14 +178,42 @@ CreateRootBridge ( CopyMem (&RootBridge->PMemAbove4G, &Bridge->PMemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE)); for (Index = TypeIo; Index < TypeMax; Index++) { - RootBridge->ResAllocNode[Index].Type = Index; - RootBridge->ResAllocNode[Index].Base = 0; - RootBridge->ResAllocNode[Index].Length = 0; - RootBridge->ResAllocNode[Index].Status = ResNone; + switch (Index) { + case TypeBus: + Aperture = &RootBridge->Bus; + break; + case TypeIo: + Aperture = &RootBridge->Io; + break; + case TypeMem32: + Aperture = &RootBridge->Mem; + break; + case TypeMem64: + Aperture = &RootBridge->MemAbove4G; + break; + case TypePMem32: + Aperture = &RootBridge->PMem; + break; + case TypePMem64: + Aperture = &RootBridge->PMemAbove4G; + break; + default: + ASSERT (FALSE); + break; + } + RootBridge->ResAllocNode[Index].Type = Index; + if (Bridge->ResourceAssigned && (Aperture->Limit >= Aperture->Base)) { + RootBridge->ResAllocNode[Index].Base = Aperture->Base; + RootBridge->ResAllocNode[Index].Length = Aperture->Limit - Aperture->Base + 1; + RootBridge->ResAllocNode[Index].Status = ResAllocated; + } else { + RootBridge->ResAllocNode[Index].Base = 0; + RootBridge->ResAllocNode[Index].Length = 0; + RootBridge->ResAllocNode[Index].Status = ResNone; + } } RootBridge->RootBridgeIo.SegmentNumber = Bridge->Segment; - RootBridge->RootBridgeIo.ParentHandle = HostBridgeHandle; RootBridge->RootBridgeIo.PollMem = RootBridgeIoPollMem; RootBridge->RootBridgeIo.PollIo = RootBridgeIoPollIo; RootBridge->RootBridgeIo.Mem.Read = RootBridgeIoMemRead; From c0a2591b30489ead14ada91908646605929b62b2 Mon Sep 17 00:00:00 2001 From: Ruiyu Ni Date: Mon, 9 May 2016 14:03:57 +0800 Subject: [PATCH 25/26] OvmfPkg/PciHostBridgeLib: Change InitRootBridge prototype The patch re-factors the code without functionality impact. Next patch will add code to support OVMF above Xen. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Reviewed-by: Laszlo Ersek --- .../PciHostBridgeLib/PciHostBridgeLib.c | 131 +++++++++++++----- 1 file changed, 93 insertions(+), 38 deletions(-) diff --git a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c index 9e01498187..aeb0bdf84d 100644 --- a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -70,13 +70,20 @@ OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = { } }; +STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 }; /** Initialize a PCI_ROOT_BRIDGE structure. - param[in] RootBusNumber The bus number to store in RootBus. + @param[in] Supports Supported attributes. - param[in] MaxSubBusNumber The inclusive maximum bus number that can be + @param[in] Attributes Initial attributes. + + @param[in] AllocAttributes Allocation attributes. + + @param[in] RootBusNumber The bus number to store in RootBus. + + @param[in] MaxSubBusNumber The inclusive maximum bus number that can be assigned to any subordinate bus found behind any PCI bridge hanging off this root bus. @@ -85,7 +92,17 @@ OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = { RootBusNumber equals MaxSubBusNumber, then the root bus has no room for subordinate buses. - param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the + @param[in] Io IO aperture. + + @param[in] Mem MMIO aperture. + + @param[in] MemAbove4G MMIO aperture above 4G. + + @param[in] PMem Prefetchable MMIO aperture. + + @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G. + + @param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the caller) that should be filled in by this function. @@ -99,9 +116,17 @@ OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = { STATIC EFI_STATUS InitRootBridge ( - IN UINT8 RootBusNumber, - IN UINT8 MaxSubBusNumber, - OUT PCI_ROOT_BRIDGE *RootBus + IN UINT64 Supports, + IN UINT64 Attributes, + IN UINT64 AllocAttributes, + IN UINT8 RootBusNumber, + IN UINT8 MaxSubBusNumber, + IN PCI_ROOT_BRIDGE_APERTURE *Io, + IN PCI_ROOT_BRIDGE_APERTURE *Mem, + IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G, + IN PCI_ROOT_BRIDGE_APERTURE *PMem, + IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G, + OUT PCI_ROOT_BRIDGE *RootBus ) { OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath; @@ -113,39 +138,19 @@ InitRootBridge ( RootBus->Segment = 0; - RootBus->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | - EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | - EFI_PCI_ATTRIBUTE_ISA_IO_16 | - EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | - EFI_PCI_ATTRIBUTE_VGA_MEMORY | - EFI_PCI_ATTRIBUTE_VGA_IO_16 | - EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16; - RootBus->Attributes = RootBus->Supports; + RootBus->Supports = Supports; + RootBus->Attributes = Attributes; RootBus->DmaAbove4G = FALSE; - RootBus->AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM; - RootBus->PMem.Base = MAX_UINT64; - RootBus->PMem.Limit = 0; - RootBus->PMemAbove4G.Base = MAX_UINT64; - RootBus->PMemAbove4G.Limit = 0; - RootBus->MemAbove4G.Base = MAX_UINT64; - RootBus->MemAbove4G.Limit = 0; - - if (PcdGet64 (PcdPciMmio64Size) > 0) { - RootBus->AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE; - RootBus->MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base); - RootBus->MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) + - (PcdGet64 (PcdPciMmio64Size) - 1); - } - + RootBus->AllocationAttributes = AllocAttributes; RootBus->Bus.Base = RootBusNumber; RootBus->Bus.Limit = MaxSubBusNumber; - RootBus->Io.Base = PcdGet64 (PcdPciIoBase); - RootBus->Io.Limit = PcdGet64 (PcdPciIoBase) + (PcdGet64 (PcdPciIoSize) - 1); - RootBus->Mem.Base = PcdGet64 (PcdPciMmio32Base); - RootBus->Mem.Limit = PcdGet64 (PcdPciMmio32Base) + - (PcdGet64 (PcdPciMmio32Size) - 1); + CopyMem (&RootBus->Io, Io, sizeof (*Io)); + CopyMem (&RootBus->Mem, Mem, sizeof (*Mem)); + CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G)); + CopyMem (&RootBus->PMem, PMem, sizeof (*PMem)); + CopyMem (&RootBus->PMemAbove4G, PMemAbove4G, sizeof (*PMemAbove4G)); RootBus->NoExtendedConfigSpace = (PcdGet16 (PcdOvmfHostBridgePciDevId) != INTEL_Q35_MCH_DEVICE_ID); @@ -206,6 +211,34 @@ PciHostBridgeGetRootBridges ( UINTN Initialized; UINTN LastRootBridgeNumber; UINTN RootBridgeNumber; + UINT64 Attributes; + UINT64 AllocationAttributes; + PCI_ROOT_BRIDGE_APERTURE Io; + PCI_ROOT_BRIDGE_APERTURE Mem; + PCI_ROOT_BRIDGE_APERTURE MemAbove4G; + + Attributes = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | + EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | + EFI_PCI_ATTRIBUTE_ISA_IO_16 | + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | + EFI_PCI_ATTRIBUTE_VGA_MEMORY | + EFI_PCI_ATTRIBUTE_VGA_IO_16 | + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16; + + AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM; + if (PcdGet64 (PcdPciMmio64Size) > 0) { + AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE; + MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base); + MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) + + PcdGet64 (PcdPciMmio64Size) - 1; + } else { + CopyMem (&MemAbove4G, &mNonExistAperture, sizeof (mNonExistAperture)); + } + + Io.Base = PcdGet64 (PcdPciIoBase); + Io.Limit = PcdGet64 (PcdPciIoBase) + (PcdGet64 (PcdPciIoSize) - 1); + Mem.Base = PcdGet64 (PcdPciMmio32Base); + Mem.Limit = PcdGet64 (PcdPciMmio32Base) + (PcdGet64 (PcdPciMmio32Size) - 1); *Count = 0; @@ -266,8 +299,19 @@ PciHostBridgeGetRootBridges ( // because now we know how big a bus number range *that* one has, for any // subordinate buses that might exist behind PCI bridges hanging off it. // - Status = InitRootBridge ((UINT8)LastRootBridgeNumber, - (UINT8)(RootBridgeNumber - 1), &Bridges[Initialized]); + Status = InitRootBridge ( + Attributes, + Attributes, + AllocationAttributes, + (UINT8) LastRootBridgeNumber, + (UINT8) (RootBridgeNumber - 1), + &Io, + &Mem, + &MemAbove4G, + &mNonExistAperture, + &mNonExistAperture, + &Bridges[Initialized] + ); if (EFI_ERROR (Status)) { goto FreeBridges; } @@ -280,8 +324,19 @@ PciHostBridgeGetRootBridges ( // Install the last root bus (which might be the only, ie. main, root bus, if // we've found no extra root buses). // - Status = InitRootBridge ((UINT8)LastRootBridgeNumber, PCI_MAX_BUS, - &Bridges[Initialized]); + Status = InitRootBridge ( + Attributes, + Attributes, + AllocationAttributes, + (UINT8) LastRootBridgeNumber, + PCI_MAX_BUS, + &Io, + &Mem, + &MemAbove4G, + &mNonExistAperture, + &mNonExistAperture, + &Bridges[Initialized] + ); if (EFI_ERROR (Status)) { goto FreeBridges; } From 49effaf26ec952905bc7710587c6a58437864cdf Mon Sep 17 00:00:00 2001 From: Ruiyu Ni Date: Tue, 10 May 2016 11:14:45 +0800 Subject: [PATCH 26/26] OvmfPkg/PciHostBridgeLib: Scan for root bridges when running over Xen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Acked-by: Laszlo Ersek Tested-by: Gary Lin --- .../Library/PciHostBridgeLib/PciHostBridge.h | 75 +++ .../PciHostBridgeLib/PciHostBridgeLib.c | 6 +- .../PciHostBridgeLib/PciHostBridgeLib.inf | 3 + OvmfPkg/Library/PciHostBridgeLib/XenSupport.c | 456 ++++++++++++++++++ 4 files changed, 539 insertions(+), 1 deletion(-) create mode 100644 OvmfPkg/Library/PciHostBridgeLib/PciHostBridge.h create mode 100644 OvmfPkg/Library/PciHostBridgeLib/XenSupport.c diff --git a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridge.h b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridge.h new file mode 100644 index 0000000000..c23d40c8ac --- /dev/null +++ b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridge.h @@ -0,0 +1,75 @@ +/** @file + Header file of OVMF instance of PciHostBridgeLib. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +PCI_ROOT_BRIDGE * +ScanForRootBridges ( + UINTN *NumberOfRootBridges +); + +/** + Initialize a PCI_ROOT_BRIDGE structure. + + @param[in] Supports Supported attributes. + + @param[in] Attributes Initial attributes. + + @param[in] AllocAttributes Allocation attributes. + + @param[in] RootBusNumber The bus number to store in RootBus. + + @param[in] MaxSubBusNumber The inclusive maximum bus number that can be + assigned to any subordinate bus found behind any + PCI bridge hanging off this root bus. + + The caller is repsonsible for ensuring that + RootBusNumber <= MaxSubBusNumber. If + RootBusNumber equals MaxSubBusNumber, then the + root bus has no room for subordinate buses. + + @param[in] Io IO aperture. + + @param[in] Mem MMIO aperture. + + @param[in] MemAbove4G MMIO aperture above 4G. + + @param[in] PMem Prefetchable MMIO aperture. + + @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G. + + @param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the + caller) that should be filled in by this + function. + + @retval EFI_SUCCESS Initialization successful. A device path + consisting of an ACPI device path node, with + UID = RootBusNumber, has been allocated and + linked into RootBus. + + @retval EFI_OUT_OF_RESOURCES Memory allocation failed. +**/ +EFI_STATUS +InitRootBridge ( + IN UINT64 Supports, + IN UINT64 Attributes, + IN UINT64 AllocAttributes, + IN UINT8 RootBusNumber, + IN UINT8 MaxSubBusNumber, + IN PCI_ROOT_BRIDGE_APERTURE *Io, + IN PCI_ROOT_BRIDGE_APERTURE *Mem, + IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G, + IN PCI_ROOT_BRIDGE_APERTURE *PMem, + IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G, + OUT PCI_ROOT_BRIDGE *RootBus + ); diff --git a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c index aeb0bdf84d..6ba0ca6831 100644 --- a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -28,6 +28,7 @@ #include #include #include +#include "PciHostBridge.h" #pragma pack(1) @@ -113,7 +114,6 @@ STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 }; @retval EFI_OUT_OF_RESOURCES Memory allocation failed. **/ -STATIC EFI_STATUS InitRootBridge ( IN UINT64 Supports, @@ -217,6 +217,10 @@ PciHostBridgeGetRootBridges ( PCI_ROOT_BRIDGE_APERTURE Mem; PCI_ROOT_BRIDGE_APERTURE MemAbove4G; + if (PcdGetBool (PcdPciDisableBusEnumeration)) { + return ScanForRootBridges (Count); + } + Attributes = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | EFI_PCI_ATTRIBUTE_ISA_IO_16 | diff --git a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf index 7a964c74c6..046ffbde8e 100644 --- a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf +++ b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -32,6 +32,8 @@ [Sources] PciHostBridgeLib.c + XenSupport.c + PciHostBridge.h [Packages] MdeModulePkg/MdeModulePkg.dec @@ -54,3 +56,4 @@ gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration diff --git a/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c b/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c new file mode 100644 index 0000000000..21896637e0 --- /dev/null +++ b/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c @@ -0,0 +1,456 @@ +/** @file + Scan the entire PCI bus for root bridges to support OVMF above Xen. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include + +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include "PciHostBridge.h" + +STATIC +VOID +PcatPciRootBridgeBarExisted ( + IN UINT64 Address, + OUT UINT32 *OriginalValue, + OUT UINT32 *Value + ) +{ + // + // Preserve the original value + // + *OriginalValue = PciRead32 (Address); + + // + // Disable timer interrupt while the BAR is probed + // + DisableInterrupts (); + + PciWrite32 (Address, 0xFFFFFFFF); + *Value = PciRead32 (Address); + PciWrite32 (Address, *OriginalValue); + + // + // Enable interrupt + // + EnableInterrupts (); +} + +STATIC +VOID +PcatPciRootBridgeParseBars ( + IN UINT16 Command, + IN UINTN Bus, + IN UINTN Device, + IN UINTN Function, + IN UINTN BarOffsetBase, + IN UINTN BarOffsetEnd, + IN PCI_ROOT_BRIDGE_APERTURE *Io, + IN PCI_ROOT_BRIDGE_APERTURE *Mem, + IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G, + IN PCI_ROOT_BRIDGE_APERTURE *PMem, + IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G + +) +{ + UINT32 OriginalValue; + UINT32 Value; + UINT32 OriginalUpperValue; + UINT32 UpperValue; + UINT64 Mask; + UINTN Offset; + UINT64 Base; + UINT64 Length; + UINT64 Limit; + PCI_ROOT_BRIDGE_APERTURE *MemAperture; + + for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) { + PcatPciRootBridgeBarExisted ( + PCI_LIB_ADDRESS (Bus, Device, Function, Offset), + &OriginalValue, &Value + ); + if (Value == 0) { + continue; + } + if ((Value & BIT0) == BIT0) { + // + // IO Bar + // + if (Command & EFI_PCI_COMMAND_IO_SPACE) { + Mask = 0xfffffffc; + Base = OriginalValue & Mask; + Length = ((~(Value & Mask)) & Mask) + 0x04; + if (!(Value & 0xFFFF0000)) { + Length &= 0x0000FFFF; + } + Limit = Base + Length - 1; + + if (Base < Limit) { + if (Io->Base > Base) { + Io->Base = Base; + } + if (Io->Limit < Limit) { + Io->Limit = Limit; + } + } + } + } else { + // + // Mem Bar + // + if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) { + + Mask = 0xfffffff0; + Base = OriginalValue & Mask; + Length = Value & Mask; + + if ((Value & (BIT1 | BIT2)) == 0) { + // + // 32bit + // + Length = ((~Length) + 1) & 0xffffffff; + + if ((Value & BIT3) == BIT3) { + MemAperture = PMem; + } else { + MemAperture = Mem; + } + } else { + // + // 64bit + // + Offset += 4; + PcatPciRootBridgeBarExisted ( + PCI_LIB_ADDRESS (Bus, Device, Function, Offset), + &OriginalUpperValue, + &UpperValue + ); + + Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32); + Length = Length | LShiftU64 ((UINT64) UpperValue, 32); + Length = (~Length) + 1; + + if ((Value & BIT3) == BIT3) { + MemAperture = PMemAbove4G; + } else { + MemAperture = MemAbove4G; + } + } + + Limit = Base + Length - 1; + if (Base < Limit) { + if (MemAperture->Base > Base) { + MemAperture->Base = Base; + } + if (MemAperture->Limit < Limit) { + MemAperture->Limit = Limit; + } + } + } + } + } +} + +PCI_ROOT_BRIDGE * +ScanForRootBridges ( + UINTN *NumberOfRootBridges + ) +{ + UINTN PrimaryBus; + UINTN SubBus; + UINT8 Device; + UINT8 Function; + UINTN NumberOfDevices; + UINT64 Address; + PCI_TYPE01 Pci; + UINT64 Attributes; + UINT64 Base; + UINT64 Limit; + UINT64 Value; + PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture; + PCI_ROOT_BRIDGE *RootBridges; + UINTN BarOffsetEnd; + + + *NumberOfRootBridges = 0; + RootBridges = NULL; + + // + // After scanning all the PCI devices on the PCI root bridge's primary bus, + // update the Primary Bus Number for the next PCI root bridge to be this PCI + // root bridge's subordinate bus number + 1. + // + for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) { + SubBus = PrimaryBus; + Attributes = 0; + Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64; + Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0; + // + // Scan all the PCI devices on the primary bus of the PCI root bridge + // + for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) { + + for (Function = 0; Function <= PCI_MAX_FUNC; Function++) { + + // + // Compute the PCI configuration address of the PCI device to probe + // + Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0); + + // + // Read the Vendor ID from the PCI Configuration Header + // + if (PciRead16 (Address) == MAX_UINT16) { + if (Function == 0) { + // + // If the PCI Configuration Read fails, or a PCI device does not + // exist, then skip this entire PCI device + // + break; + } else { + // + // If PCI function != 0, VendorId == 0xFFFF, we continue to search + // PCI function. + // + continue; + } + } + + // + // Read the entire PCI Configuration Header + // + PciReadBuffer (Address, sizeof (Pci), &Pci); + + // + // Increment the number of PCI device found on the primary bus of the + // PCI root bridge + // + NumberOfDevices++; + + // + // Look for devices with the VGA Palette Snoop enabled in the COMMAND + // register of the PCI Config Header + // + if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) { + Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO; + Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16; + } + + BarOffsetEnd = 0; + + // + // PCI-PCI Bridge + // + if (IS_PCI_BRIDGE (&Pci)) { + // + // Get the Bus range that the PPB is decoding + // + if (Pci.Bridge.SubordinateBus > SubBus) { + // + // If the suborinate bus number of the PCI-PCI bridge is greater + // than the PCI root bridge's current subordinate bus number, + // then update the PCI root bridge's subordinate bus number + // + SubBus = Pci.Bridge.SubordinateBus; + } + + // + // Get the I/O range that the PPB is decoding + // + Value = Pci.Bridge.IoBase & 0x0f; + Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8; + Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff; + if (Value == BIT0) { + Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16); + Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16); + } + if (Base < Limit) { + if (Io.Base > Base) { + Io.Base = Base; + } + if (Io.Limit < Limit) { + Io.Limit = Limit; + } + } + + // + // Get the Memory range that the PPB is decoding + // + Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16; + Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff; + if (Base < Limit) { + if (Mem.Base > Base) { + Mem.Base = Base; + } + if (Mem.Limit < Limit) { + Mem.Limit = Limit; + } + } + + // + // Get the Prefetchable Memory range that the PPB is decoding + // + Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f; + Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16; + Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0) + << 16) | 0xfffff; + MemAperture = &PMem; + if (Value == BIT0) { + Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32); + Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32); + MemAperture = &PMemAbove4G; + } + if (Base < Limit) { + if (MemAperture->Base > Base) { + MemAperture->Base = Base; + } + if (MemAperture->Limit < Limit) { + MemAperture->Limit = Limit; + } + } + + // + // Look at the PPB Configuration for legacy decoding attributes + // + if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA) + == EFI_PCI_BRIDGE_CONTROL_ISA) { + Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO; + Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16; + Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO; + } + if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA) + == EFI_PCI_BRIDGE_CONTROL_VGA) { + Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO; + Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY; + Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO; + if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16) + != 0) { + Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16; + Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16; + } + } + + BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]); + } else { + // + // Parse the BARs of the PCI device to get what I/O Ranges, Memory + // Ranges, and Prefetchable Memory Ranges the device is decoding + // + if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) { + BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]); + } + } + + PcatPciRootBridgeParseBars ( + Pci.Hdr.Command, + PrimaryBus, + Device, + Function, + OFFSET_OF (PCI_TYPE00, Device.Bar), + BarOffsetEnd, + &Io, + &Mem, &MemAbove4G, + &PMem, &PMemAbove4G + ); + + // + // See if the PCI device is an IDE controller + // + if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE, + PCI_CLASS_MASS_STORAGE_IDE)) { + if (Pci.Hdr.ClassCode[0] & 0x80) { + Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO; + Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO; + } + if (Pci.Hdr.ClassCode[0] & 0x01) { + Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO; + } + if (Pci.Hdr.ClassCode[0] & 0x04) { + Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO; + } + } + + // + // See if the PCI device is a legacy VGA controller or + // a standard VGA controller + // + if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) || + IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA) + ) { + Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO; + Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16; + Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY; + Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO; + Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16; + } + + // + // See if the PCI Device is a PCI - ISA or PCI - EISA + // or ISA_POSITIVIE_DECODE Bridge device + // + if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) { + if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA || + Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA || + Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) { + Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO; + Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16; + Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO; + } + } + + // + // If this device is not a multi function device, then skip the rest + // of this PCI device + // + if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) { + break; + } + } + } + + // + // If at least one PCI device was found on the primary bus of this PCI + // root bridge, then the PCI root bridge exists. + // + if (NumberOfDevices > 0) { + RootBridges = ReallocatePool ( + (*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE), + (*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE), + RootBridges + ); + ASSERT (RootBridges != NULL); + InitRootBridge ( + Attributes, Attributes, 0, + (UINT8) PrimaryBus, (UINT8) SubBus, + &Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G, + &RootBridges[*NumberOfRootBridges] + ); + RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE; + // + // Increment the index for the next PCI Root Bridge + // + (*NumberOfRootBridges)++; + } + } + + return RootBridges; +}