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Synchronize interface function comment from declaration in library class header file to implementation in library instance. 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6957 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
klu2 2008-12-10 03:28:54 +00:00
parent 530e25f536
commit 070a76b193
12 changed files with 386 additions and 393 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MdePkg/Library/DxeSmbusLib/DxeSmbusLib.c
View File

@ -68,7 +68,7 @@ SmbusLibConstructor (
@param Status Return status for the executed command. @param Status Return status for the executed command.
This is an optional parameter and may be NULL. This is an optional parameter and may be NULL.
@return The actual number of bytes that are executed for this operation.. @return The actual number of bytes that are executed for this operation.
**/ **/
UINTN UINTN

3
MdePkg/Library/UefiDriverEntryPoint/DriverEntryPoint.c
View File

@ -79,7 +79,8 @@ _DriverUnloadHandler (
@param ImageHandle ImageHandle of the loaded driver. @param ImageHandle ImageHandle of the loaded driver.
@param SystemTable Pointer to the EFI System Table. @param SystemTable Pointer to the EFI System Table.
@retval EFI_SUCCESS One or more of the drivers returned a success code. @retval EFI_SUCCESS The DXE Driver, DXE Runtime Driver, DXE SMM Driver,
or UEFI Driver exited normally.
@retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than SystemTable->Hdr.Revision. @retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than SystemTable->Hdr.Revision.
@retval Other Return value from ProcessModuleEntryPointList(). @retval Other Return value from ProcessModuleEntryPointList().

1
MdePkg/Library/UefiLib/UefiLib.c
View File

@ -689,7 +689,6 @@ LookupUnicodeString (
**/ **/
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
LookupUnicodeString2 ( LookupUnicodeString2 (
IN CONST CHAR8 *Language, IN CONST CHAR8 *Language,

26
MdePkg/Library/UefiLib/UefiNotTiano.c
View File

@ -282,17 +282,17 @@ EfiSignalEventLegacyBoot (
@retval Other FvDevicePathNode is valid and pointer to NameGuid was returned. @retval Other FvDevicePathNode is valid and pointer to NameGuid was returned.
**/ **/
EFI_GUID* EFI_GUID *
EFIAPI EFIAPI
EfiGetNameGuidFromFwVolDevicePathNode ( EfiGetNameGuidFromFwVolDevicePathNode (
IN CONST MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvFileDevicePathNode IN CONST MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvDevicePathNode
) )
{ {
ASSERT (FvFileDevicePathNode != NULL); ASSERT (FvDevicePathNode != NULL);
if (DevicePathType (&FvFileDevicePathNode->Header) == MEDIA_DEVICE_PATH && if (DevicePathType (&FvDevicePathNode->Header) == MEDIA_DEVICE_PATH &&
DevicePathSubType (&FvFileDevicePathNode->Header) == MEDIA_PIWG_FW_FILE_DP) { DevicePathSubType (&FvDevicePathNode->Header) == MEDIA_PIWG_FW_FILE_DP) {
return (EFI_GUID *) &FvFileDevicePathNode->FvFileName; return (EFI_GUID *) &FvDevicePathNode->FvFileName;
} }
return NULL; return NULL;
@ -318,20 +318,20 @@ EfiGetNameGuidFromFwVolDevicePathNode (
VOID VOID
EFIAPI EFIAPI
EfiInitializeFwVolDevicepathNode ( EfiInitializeFwVolDevicepathNode (
IN OUT MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvFileDevicePathNode, IN OUT MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvDevicePathNode,
IN CONST EFI_GUID *NameGuid IN CONST EFI_GUID *NameGuid
) )
{ {
ASSERT (FvFileDevicePathNode != NULL); ASSERT (FvDevicePathNode != NULL);
ASSERT (NameGuid != NULL); ASSERT (NameGuid != NULL);
// //
// Use the new Device path that does not conflict with the UEFI // Use the new Device path that does not conflict with the UEFI
// //
FvFileDevicePathNode->Header.Type = MEDIA_DEVICE_PATH; FvDevicePathNode->Header.Type = MEDIA_DEVICE_PATH;
FvFileDevicePathNode->Header.SubType = MEDIA_PIWG_FW_FILE_DP; FvDevicePathNode->Header.SubType = MEDIA_PIWG_FW_FILE_DP;
SetDevicePathNodeLength (&FvFileDevicePathNode->Header, sizeof (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH)); SetDevicePathNodeLength (&FvDevicePathNode->Header, sizeof (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH));
CopyGuid (&FvFileDevicePathNode->FvFileName, NameGuid); CopyGuid (&FvDevicePathNode->FvFileName, NameGuid);
} }

30
MdePkg/Library/UefiMemoryLib/MemLibInternals.h
View File

@ -36,38 +36,42 @@
#include <Library/BaseLib.h> #include <Library/BaseLib.h>
/** /**
Copy Length bytes from Source to Destination. Copies a source buffer to a destination buffer, and returns the destination buffer.
@param DestinationBuffer Target of copy This function wraps the gBS->CopyMem().
@param SourceBuffer Place to copy from
@param Length Number of bytes to copy
@return Destination @param DestinationBuffer Pointer to the destination buffer of the memory copy.
@param SourceBuffer Pointer to the source buffer of the memory copy.
@param Length Number of bytes to copy from SourceBuffer to DestinationBuffer.
@return DestinationBuffer.
**/ **/
VOID * VOID *
EFIAPI EFIAPI
InternalMemCopyMem ( InternalMemCopyMem (
OUT VOID *DestinationBuffer, OUT VOID *Destination,
IN CONST VOID *SourceBuffer, IN CONST VOID *Source,
IN UINTN Length IN UINTN Length
); );
/** /**
Set Buffer to Value for Size bytes. Fills a target buffer with a byte value, and returns the target buffer.
@param Buffer Memory to set. This function wraps the gBS->SetMem().
@param Length Number of bytes to set
@param Value Value of the set operation.
@return Buffer @param Buffer Memory to set.
@param Size Number of bytes to set.
@param Value Value of the set operation.
@return Buffer.
**/ **/
VOID * VOID *
EFIAPI EFIAPI
InternalMemSetMem ( InternalMemSetMem (
OUT VOID *Buffer, OUT VOID *Buffer,
IN UINTN Length, IN UINTN Size,
IN UINT8 Value IN UINT8 Value
); );

31
MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
View File

@ -143,9 +143,12 @@ DxePciLibPciRootBridgeIoWriteWorker (
} }
/** /**
Register a PCI device so PCI configuration registers may be accessed after Registers a PCI device so PCI configuration registers may be accessed after
SetVirtualAddressMap(). SetVirtualAddressMap().
Registers the PCI device specified by Address so all the PCI configuration registers
associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
If Address > 0x0FFFFFFF, then ASSERT(). If Address > 0x0FFFFFFF, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and @param Address Address that encodes the PCI Bus, Device, Function and
@ -181,7 +184,7 @@ PciRegisterForRuntimeAccess (
@param Address Address that encodes the PCI Bus, Device, Function and @param Address Address that encodes the PCI Bus, Device, Function and
Register. Register.
@return The value read from the PCI configuration register. @return The read value from the PCI configuration register.
**/ **/
UINT8 UINT8
@ -206,7 +209,7 @@ PciRead8 (
@param Address Address that encodes the PCI Bus, Device, Function and @param Address Address that encodes the PCI Bus, Device, Function and
Register. Register.
@param Data The value to write. @param Value The value to write.
@return The value written to the PCI configuration register. @return The value written to the PCI configuration register.
@ -215,12 +218,12 @@ UINT8
EFIAPI EFIAPI
PciWrite8 ( PciWrite8 (
IN UINTN Address, IN UINTN Address,
IN UINT8 Data IN UINT8 Value
) )
{ {
ASSERT_INVALID_PCI_ADDRESS (Address, 0); ASSERT_INVALID_PCI_ADDRESS (Address, 0);
return (UINT8) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Data); return (UINT8) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);
} }
/** /**
@ -526,7 +529,7 @@ PciBitFieldAndThenOr8 (
@param Address Address that encodes the PCI Bus, Device, Function and @param Address Address that encodes the PCI Bus, Device, Function and
Register. Register.
@return The value read from the PCI configuration register. @return The read value from the PCI configuration register.
**/ **/
UINT16 UINT16
@ -552,7 +555,7 @@ PciRead16 (
@param Address Address that encodes the PCI Bus, Device, Function and @param Address Address that encodes the PCI Bus, Device, Function and
Register. Register.
@param Data The value to write. @param Value The value to write.
@return The value written to the PCI configuration register. @return The value written to the PCI configuration register.
@ -561,12 +564,12 @@ UINT16
EFIAPI EFIAPI
PciWrite16 ( PciWrite16 (
IN UINTN Address, IN UINTN Address,
IN UINT16 Data IN UINT16 Value
) )
{ {
ASSERT_INVALID_PCI_ADDRESS (Address, 1); ASSERT_INVALID_PCI_ADDRESS (Address, 1);
return (UINT16) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Data); return (UINT16) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);
} }
/** /**
@ -880,7 +883,7 @@ PciBitFieldAndThenOr16 (
@param Address Address that encodes the PCI Bus, Device, Function and @param Address Address that encodes the PCI Bus, Device, Function and
Register. Register.
@return The value read from the PCI configuration register. @return The read value from the PCI configuration register.
**/ **/
UINT32 UINT32
@ -906,7 +909,7 @@ PciRead32 (
@param Address Address that encodes the PCI Bus, Device, Function and @param Address Address that encodes the PCI Bus, Device, Function and
Register. Register.
@param Data The value to write. @param Value The value to write.
@return The value written to the PCI configuration register. @return The value written to the PCI configuration register.
@ -915,12 +918,12 @@ UINT32
EFIAPI EFIAPI
PciWrite32 ( PciWrite32 (
IN UINTN Address, IN UINTN Address,
IN UINT32 Data IN UINT32 Value
) )
{ {
ASSERT_INVALID_PCI_ADDRESS (Address, 3); ASSERT_INVALID_PCI_ADDRESS (Address, 3);
return DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Data); return DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Value);
} }
/** /**
@ -1339,7 +1342,7 @@ PciReadBuffer (
@param Size Size in bytes of the transfer. @param Size Size in bytes of the transfer.
@param Buffer Pointer to a buffer containing the data to write. @param Buffer Pointer to a buffer containing the data to write.
@return Size @return Size written to StartAddress.
**/ **/
UINTN UINTN

582
MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
View File

@ -271,21 +271,19 @@ PciSegmentRegisterForRuntimeAccess (
Reads an 8-bit PCI configuration register. Reads an 8-bit PCI configuration register.
Reads and returns the 8-bit PCI configuration register specified by Address. Reads and returns the 8-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are This function must guarantee that all PCI read and write operations are serialized.
serialized.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
Register.
@return The value read from the PCI configuration register. @return The 8-bit PCI configuration register specified by Address.
**/ **/
UINT8 UINT8
EFIAPI EFIAPI
PciSegmentRead8 ( PciSegmentRead8 (
IN UINT64 Address IN UINT64 Address
) )
{ {
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
@ -296,15 +294,13 @@ PciSegmentRead8 (
/** /**
Writes an 8-bit PCI configuration register. Writes an 8-bit PCI configuration register.
Writes the 8-bit PCI configuration register specified by Address with the Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
value specified by Value. Value is returned. This function must guarantee Value is returned. This function must guarantee that all PCI read and write operations are serialized.
that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If Address > 0x0FFFFFFF, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
Register. @param Value The value to write.
@param Data The value to write.
@return The value written to the PCI configuration register. @return The value written to the PCI configuration register.
@ -312,103 +308,94 @@ PciSegmentRead8 (
UINT8 UINT8
EFIAPI EFIAPI
PciSegmentWrite8 ( PciSegmentWrite8 (
IN UINT64 Address, IN UINT64 Address,
IN UINT8 Data IN UINT8 Value
) )
{ {
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
return (UINT8) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Data); return (UINT8) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);
} }
/** /**
Performs a bitwise OR of an 8-bit PCI configuration register with Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
an 8-bit value.
Reads the 8-bit PCI configuration register specified by Address, performs a Reads the 8-bit PCI configuration register specified by Address,
bitwise OR between the read result and the value specified by performs a bitwise OR between the read result and the value specified by OrData,
OrData, and writes the result to the 8-bit PCI configuration register and writes the result to the 8-bit PCI configuration register specified by Address.
specified by Address. The value written to the PCI configuration register is The value written to the PCI configuration register is returned.
returned. This function must guarantee that all PCI read and write operations This function must guarantee that all PCI read and write operations are serialized.
are serialized.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
Register. @param OrData The value to OR with the PCI configuration register.
@param OrData The value to OR with the PCI configuration register.
@return The value written back to the PCI configuration register. @return The value written to the PCI configuration register.
**/ **/
UINT8 UINT8
EFIAPI EFIAPI
PciSegmentOr8 ( PciSegmentOr8 (
IN UINT64 Address, IN UINT64 Address,
IN UINT8 OrData IN UINT8 OrData
) )
{ {
return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData)); return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));
} }
/** /**
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
value.
Reads the 8-bit PCI configuration register specified by Address, performs a
bitwise AND between the read result and the value specified by AndData, and
writes the result to the 8-bit PCI configuration register specified by
Address. The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are
serialized.
Reads the 8-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
and writes the result to the 8-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
Register. @param AndData The value to AND with the PCI configuration register.
@param AndData The value to AND with the PCI configuration register.
@return The value written back to the PCI configuration register. @return The value written to the PCI configuration register.
**/ **/
UINT8 UINT8
EFIAPI EFIAPI
PciSegmentAnd8 ( PciSegmentAnd8 (
IN UINT64 Address, IN UINT64 Address,
IN UINT8 AndData IN UINT8 AndData
) )
{ {
return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData)); return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));
} }
/** /**
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
value, followed a bitwise OR with another 8-bit value. followed a bitwise OR with another 8-bit value.
Reads the 8-bit PCI configuration register specified by Address, performs a Reads the 8-bit PCI configuration register specified by Address,
bitwise AND between the read result and the value specified by AndData, performs a bitwise AND between the read result and the value specified by AndData,
performs a bitwise OR between the result of the AND operation and performs a bitwise OR between the result of the AND operation and the value specified by OrData,
the value specified by OrData, and writes the result to the 8-bit PCI and writes the result to the 8-bit PCI configuration register specified by Address.
configuration register specified by Address. The value written to the PCI The value written to the PCI configuration register is returned.
configuration register is returned. This function must guarantee that all PCI This function must guarantee that all PCI read and write operations are serialized.
read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
Register. @param AndData The value to AND with the PCI configuration register.
@param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the PCI configuration register.
@param OrData The value to OR with the result of the AND operation.
@return The value written back to the PCI configuration register. @return The value written to the PCI configuration register.
**/ **/
UINT8 UINT8
EFIAPI EFIAPI
PciSegmentAndThenOr8 ( PciSegmentAndThenOr8 (
IN UINT64 Address, IN UINT64 Address,
IN UINT8 AndData, IN UINT8 AndData,
IN UINT8 OrData IN UINT8 OrData
) )
{ {
return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData)); return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));
@ -438,9 +425,9 @@ PciSegmentAndThenOr8 (
UINT8 UINT8
EFIAPI EFIAPI
PciSegmentBitFieldRead8 ( PciSegmentBitFieldRead8 (
IN UINT64 Address, IN UINT64 Address,
IN UINTN StartBit, IN UINTN StartBit,
IN UINTN EndBit IN UINTN EndBit
) )
{ {
return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit); return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
@ -472,10 +459,10 @@ PciSegmentBitFieldRead8 (
UINT8 UINT8
EFIAPI EFIAPI
PciSegmentBitFieldWrite8 ( PciSegmentBitFieldWrite8 (
IN UINT64 Address, IN UINT64 Address,
IN UINTN StartBit, IN UINTN StartBit,
IN UINTN EndBit, IN UINTN EndBit,
IN UINT8 Value IN UINT8 Value
) )
{ {
return PciSegmentWrite8 ( return PciSegmentWrite8 (
@ -513,10 +500,10 @@ PciSegmentBitFieldWrite8 (
UINT8 UINT8
EFIAPI EFIAPI
PciSegmentBitFieldOr8 ( PciSegmentBitFieldOr8 (
IN UINT64 Address, IN UINT64 Address,
IN UINTN StartBit, IN UINTN StartBit,
IN UINTN EndBit, IN UINTN EndBit,
IN UINT8 OrData IN UINT8 OrData
) )
{ {
return PciSegmentWrite8 ( return PciSegmentWrite8 (
@ -554,10 +541,10 @@ PciSegmentBitFieldOr8 (
UINT8 UINT8
EFIAPI EFIAPI
PciSegmentBitFieldAnd8 ( PciSegmentBitFieldAnd8 (
IN UINT64 Address, IN UINT64 Address,
IN UINTN StartBit, IN UINTN StartBit,
IN UINTN EndBit, IN UINTN EndBit,
IN UINT8 AndData IN UINT8 AndData
) )
{ {
return PciSegmentWrite8 ( return PciSegmentWrite8 (
@ -598,11 +585,11 @@ PciSegmentBitFieldAnd8 (
UINT8 UINT8
EFIAPI EFIAPI
PciSegmentBitFieldAndThenOr8 ( PciSegmentBitFieldAndThenOr8 (
IN UINT64 Address, IN UINT64 Address,
IN UINTN StartBit, IN UINTN StartBit,
IN UINTN EndBit, IN UINTN EndBit,
IN UINT8 AndData, IN UINT8 AndData,
IN UINT8 OrData IN UINT8 OrData
) )
{ {
return PciSegmentWrite8 ( return PciSegmentWrite8 (
@ -615,21 +602,20 @@ PciSegmentBitFieldAndThenOr8 (
Reads a 16-bit PCI configuration register. Reads a 16-bit PCI configuration register.
Reads and returns the 16-bit PCI configuration register specified by Address. Reads and returns the 16-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are This function must guarantee that all PCI read and write operations are serialized.
serialized.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
Register.
@return The value read from the PCI configuration register. @return The 16-bit PCI configuration register specified by Address.
**/ **/
UINT16 UINT16
EFIAPI EFIAPI
PciSegmentRead16 ( PciSegmentRead16 (
IN UINT64 Address IN UINT64 Address
) )
{ {
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
@ -640,29 +626,28 @@ PciSegmentRead16 (
/** /**
Writes a 16-bit PCI configuration register. Writes a 16-bit PCI configuration register.
Writes the 16-bit PCI configuration register specified by Address with the Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
value specified by Value. Value is returned. This function must guarantee Value is returned. This function must guarantee that all PCI read and write operations are serialized.
that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
Register. @param Value The value to write.
@param Data The value to write.
@return The value written to the PCI configuration register. @return The parameter of Value.
**/ **/
UINT16 UINT16
EFIAPI EFIAPI
PciSegmentWrite16 ( PciSegmentWrite16 (
IN UINT64 Address, IN UINT64 Address,
IN UINT16 Data IN UINT16 Value
) )
{ {
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
return (UINT16) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Data); return (UINT16) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);
} }
/** /**
@ -677,6 +662,7 @@ PciSegmentWrite16 (
are serialized. are serialized.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and @param Address Address that encodes the PCI Segment, Bus, Device, Function and
Register. Register.
@ -688,71 +674,68 @@ PciSegmentWrite16 (
UINT16 UINT16
EFIAPI EFIAPI
PciSegmentOr16 ( PciSegmentOr16 (
IN UINT64 Address, IN UINT64 Address,
IN UINT16 OrData IN UINT16 OrData
) )
{ {
return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData)); return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
} }
/** /**
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
value.
Reads the 16-bit PCI configuration register specified by Address, performs a Reads the 16-bit PCI configuration register specified by Address,
bitwise AND between the read result and the value specified by AndData, and performs a bitwise AND between the read result and the value specified by AndData,
writes the result to the 16-bit PCI configuration register specified by and writes the result to the 16-bit PCI configuration register specified by Address.
Address. The value written to the PCI configuration register is returned. The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are This function must guarantee that all PCI read and write operations are serialized.
serialized.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
Register. @param AndData The value to AND with the PCI configuration register.
@param AndData The value to AND with the PCI configuration register.
@return The value written back to the PCI configuration register. @return The value written to the PCI configuration register.
**/ **/
UINT16 UINT16
EFIAPI EFIAPI
PciSegmentAnd16 ( PciSegmentAnd16 (
IN UINT64 Address, IN UINT64 Address,
IN UINT16 AndData IN UINT16 AndData
) )
{ {
return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData)); return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
} }
/** /**
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
value, followed a bitwise OR with another 16-bit value. followed a bitwise OR with another 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a Reads the 16-bit PCI configuration register specified by Address,
bitwise AND between the read result and the value specified by AndData, performs a bitwise AND between the read result and the value specified by AndData,
performs a bitwise OR between the result of the AND operation and performs a bitwise OR between the result of the AND operation and the value specified by OrData,
the value specified by OrData, and writes the result to the 16-bit PCI and writes the result to the 16-bit PCI configuration register specified by Address.
configuration register specified by Address. The value written to the PCI The value written to the PCI configuration register is returned.
configuration register is returned. This function must guarantee that all PCI This function must guarantee that all PCI read and write operations are serialized.
read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
Register. @param AndData The value to AND with the PCI configuration register.
@param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the PCI configuration register.
@param OrData The value to OR with the result of the AND operation.
@return The value written back to the PCI configuration register. @return The value written to the PCI configuration register.
**/ **/
UINT16 UINT16
EFIAPI EFIAPI
PciSegmentAndThenOr16 ( PciSegmentAndThenOr16 (
IN UINT64 Address, IN UINT64 Address,
IN UINT16 AndData, IN UINT16 AndData,
IN UINT16 OrData IN UINT16 OrData
) )
{ {
return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData)); return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
@ -766,6 +749,7 @@ PciSegmentAndThenOr16 (
returned. returned.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
If StartBit is greater than 15, then ASSERT(). If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
@ -782,9 +766,9 @@ PciSegmentAndThenOr16 (
UINT16 UINT16
EFIAPI EFIAPI
PciSegmentBitFieldRead16 ( PciSegmentBitFieldRead16 (
IN UINT64 Address, IN UINT64 Address,
IN UINTN StartBit, IN UINTN StartBit,
IN UINTN EndBit IN UINTN EndBit
) )
{ {
return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit); return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
@ -799,6 +783,7 @@ PciSegmentBitFieldRead16 (
16-bit register is returned. 16-bit register is returned.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
If StartBit is greater than 15, then ASSERT(). If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
@ -816,10 +801,10 @@ PciSegmentBitFieldRead16 (
UINT16 UINT16
EFIAPI EFIAPI
PciSegmentBitFieldWrite16 ( PciSegmentBitFieldWrite16 (
IN UINT64 Address, IN UINT64 Address,
IN UINTN StartBit, IN UINTN StartBit,
IN UINTN EndBit, IN UINTN EndBit,
IN UINT16 Value IN UINT16 Value
) )
{ {
return PciSegmentWrite16 ( return PciSegmentWrite16 (
@ -829,17 +814,12 @@ PciSegmentBitFieldWrite16 (
} }
/** /**
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and Reads the 16-bit PCI configuration register specified by Address,
writes the result back to the bit field in the 16-bit port. performs a bitwise OR between the read result and the value specified by OrData,
and writes the result to the 16-bit PCI configuration register specified by Address.
Reads the 16-bit PCI configuration register specified by Address, performs a
bitwise OR between the read result and the value specified by
OrData, and writes the result to the 16-bit PCI configuration register
specified by Address. The value written to the PCI configuration register is
returned. This function must guarantee that all PCI read and write operations
are serialized. Extra left bits in OrData are stripped.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
If StartBit is greater than 15, then ASSERT(). If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
@ -857,10 +837,10 @@ PciSegmentBitFieldWrite16 (
UINT16 UINT16
EFIAPI EFIAPI
PciSegmentBitFieldOr16 ( PciSegmentBitFieldOr16 (
IN UINT64 Address, IN UINT64 Address,
IN UINTN StartBit, IN UINTN StartBit,
IN UINTN EndBit, IN UINTN EndBit,
IN UINT16 OrData IN UINT16 OrData
) )
{ {
return PciSegmentWrite16 ( return PciSegmentWrite16 (
@ -870,38 +850,39 @@ PciSegmentBitFieldOr16 (
} }
/** /**
Reads a bit field in a 16-bit PCI configuration register, performs a bitwise Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
AND, and writes the result back to the bit field in the 16-bit register. and writes the result back to the bit field in the 16-bit port.
Reads the 16-bit PCI configuration register specified by Address, performs a Reads the 16-bit PCI configuration register specified by Address,
bitwise AND between the read result and the value specified by AndData, and performs a bitwise OR between the read result and the value specified by OrData,
writes the result to the 16-bit PCI configuration register specified by and writes the result to the 16-bit PCI configuration register specified by Address.
Address. The value written to the PCI configuration register is returned. The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are This function must guarantee that all PCI read and write operations are serialized.
serialized. Extra left bits in AndData are stripped. Extra left bits in OrData are stripped.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If StartBit is greater than 15, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
If EndBit is greater than 15, then ASSERT(). If StartBit is greater than 7, then ASSERT().
If EndBit is greater than 7, then ASSERT().
If EndBit is less than StartBit, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
@param Address PCI configuration register to write. @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param StartBit The ordinal of the least significant bit in the bit field. @param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15. The ordinal of the least significant bit in a byte is bit 0.
@param EndBit The ordinal of the most significant bit in the bit field. @param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15. The ordinal of the most significant bit in a byte is bit 7.
@param AndData The value to AND with the PCI configuration register. @param AndData The value to AND with the read value from the PCI configuration register.
@return The value written back to the PCI configuration register. @return The value written to the PCI configuration register.
**/ **/
UINT16 UINT16
EFIAPI EFIAPI
PciSegmentBitFieldAnd16 ( PciSegmentBitFieldAnd16 (
IN UINT64 Address, IN UINT64 Address,
IN UINTN StartBit, IN UINTN StartBit,
IN UINTN EndBit, IN UINTN EndBit,
IN UINT16 AndData IN UINT16 AndData
) )
{ {
return PciSegmentWrite16 ( return PciSegmentWrite16 (
@ -942,11 +923,11 @@ PciSegmentBitFieldAnd16 (
UINT16 UINT16
EFIAPI EFIAPI
PciSegmentBitFieldAndThenOr16 ( PciSegmentBitFieldAndThenOr16 (
IN UINT64 Address, IN UINT64 Address,
IN UINTN StartBit, IN UINTN StartBit,
IN UINTN EndBit, IN UINTN EndBit,
IN UINT16 AndData, IN UINT16 AndData,
IN UINT16 OrData IN UINT16 OrData
) )
{ {
return PciSegmentWrite16 ( return PciSegmentWrite16 (
@ -959,21 +940,20 @@ PciSegmentBitFieldAndThenOr16 (
Reads a 32-bit PCI configuration register. Reads a 32-bit PCI configuration register.
Reads and returns the 32-bit PCI configuration register specified by Address. Reads and returns the 32-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are This function must guarantee that all PCI read and write operations are serialized.
serialized.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
Register.
@return The value read from the PCI configuration register. @return The 32-bit PCI configuration register specified by Address.
**/ **/
UINT32 UINT32
EFIAPI EFIAPI
PciSegmentRead32 ( PciSegmentRead32 (
IN UINT64 Address IN UINT64 Address
) )
{ {
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
@ -984,119 +964,113 @@ PciSegmentRead32 (
/** /**
Writes a 32-bit PCI configuration register. Writes a 32-bit PCI configuration register.
Writes the 32-bit PCI configuration register specified by Address with the Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
value specified by Value. Value is returned. This function must guarantee Value is returned. This function must guarantee that all PCI read and write operations are serialized.
that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
Register. @param Value The value to write.
@param Data The value to write.
@return The parameter of Value.
**/
UINT32
EFIAPI
PciSegmentWrite32 (
IN UINT64 Address,
IN UINT32 Value
)
{
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
return DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Value);
}
/**
Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
Reads the 32-bit PCI configuration register specified by Address,
performs a bitwise OR between the read result and the value specified by OrData,
and writes the result to the 32-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register. @return The value written to the PCI configuration register.
**/
UINT32
EFIAPI
PciSegmentWrite32 (
IN UINT64 Address,
IN UINT32 Data
)
{
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
return DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Data);
}
/**
Performs a bitwise OR of a 32-bit PCI configuration register with
a 32-bit value.
Reads the 32-bit PCI configuration register specified by Address, performs a
bitwise OR between the read result and the value specified by
OrData, and writes the result to the 32-bit PCI configuration register
specified by Address. The value written to the PCI configuration register is
returned. This function must guarantee that all PCI read and write operations
are serialized.
If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and
Register.
@param OrData The value to OR with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/ **/
UINT32 UINT32
EFIAPI EFIAPI
PciSegmentOr32 ( PciSegmentOr32 (
IN UINT64 Address, IN UINT64 Address,
IN UINT32 OrData IN UINT32 OrData
) )
{ {
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData); return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
} }
/** /**
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
value.
Reads the 32-bit PCI configuration register specified by Address, performs a Reads the 32-bit PCI configuration register specified by Address,
bitwise AND between the read result and the value specified by AndData, and performs a bitwise AND between the read result and the value specified by AndData,
writes the result to the 32-bit PCI configuration register specified by and writes the result to the 32-bit PCI configuration register specified by Address.
Address. The value written to the PCI configuration register is returned. The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are This function must guarantee that all PCI read and write operations are serialized.
serialized.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
Register. @param AndData The value to AND with the PCI configuration register.
@param AndData The value to AND with the PCI configuration register.
@return The value written back to the PCI configuration register. @return The value written to the PCI configuration register.
**/ **/
UINT32 UINT32
EFIAPI EFIAPI
PciSegmentAnd32 ( PciSegmentAnd32 (
IN UINT64 Address, IN UINT64 Address,
IN UINT32 AndData IN UINT32 AndData
) )
{ {
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData); return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
} }
/** /**
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
value, followed a bitwise OR with another 32-bit value. followed a bitwise OR with another 32-bit value.
Reads the 32-bit PCI configuration register specified by Address, performs a Reads the 32-bit PCI configuration register specified by Address,
bitwise AND between the read result and the value specified by AndData, performs a bitwise AND between the read result and the value specified by AndData,
performs a bitwise OR between the result of the AND operation and performs a bitwise OR between the result of the AND operation and the value specified by OrData,
the value specified by OrData, and writes the result to the 32-bit PCI and writes the result to the 32-bit PCI configuration register specified by Address.
configuration register specified by Address. The value written to the PCI The value written to the PCI configuration register is returned.
configuration register is returned. This function must guarantee that all PCI This function must guarantee that all PCI read and write operations are serialized.
read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
Register. @param AndData The value to AND with the PCI configuration register.
@param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the PCI configuration register.
@param OrData The value to OR with the result of the AND operation.
@return The value written back to the PCI configuration register. @return The value written to the PCI configuration register.
**/ **/
UINT32 UINT32
EFIAPI EFIAPI
PciSegmentAndThenOr32 ( PciSegmentAndThenOr32 (
IN UINT64 Address, IN UINT64 Address,
IN UINT32 AndData, IN UINT32 AndData,
IN UINT32 OrData IN UINT32 OrData
) )
{ {
return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData); return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
@ -1110,6 +1084,7 @@ PciSegmentAndThenOr32 (
returned. returned.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
If StartBit is greater than 31, then ASSERT(). If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
@ -1126,9 +1101,9 @@ PciSegmentAndThenOr32 (
UINT32 UINT32
EFIAPI EFIAPI
PciSegmentBitFieldRead32 ( PciSegmentBitFieldRead32 (
IN UINT64 Address, IN UINT64 Address,
IN UINTN StartBit, IN UINTN StartBit,
IN UINTN EndBit IN UINTN EndBit
) )
{ {
return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit); return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
@ -1143,6 +1118,7 @@ PciSegmentBitFieldRead32 (
32-bit register is returned. 32-bit register is returned.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
If StartBit is greater than 31, then ASSERT(). If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
@ -1160,10 +1136,10 @@ PciSegmentBitFieldRead32 (
UINT32 UINT32
EFIAPI EFIAPI
PciSegmentBitFieldWrite32 ( PciSegmentBitFieldWrite32 (
IN UINT64 Address, IN UINT64 Address,
IN UINTN StartBit, IN UINTN StartBit,
IN UINTN EndBit, IN UINTN EndBit,
IN UINT32 Value IN UINT32 Value
) )
{ {
return PciSegmentWrite32 ( return PciSegmentWrite32 (
@ -1201,10 +1177,10 @@ PciSegmentBitFieldWrite32 (
UINT32 UINT32
EFIAPI EFIAPI
PciSegmentBitFieldOr32 ( PciSegmentBitFieldOr32 (
IN UINT64 Address, IN UINT64 Address,
IN UINTN StartBit, IN UINTN StartBit,
IN UINTN EndBit, IN UINTN EndBit,
IN UINT32 OrData IN UINT32 OrData
) )
{ {
return PciSegmentWrite32 ( return PciSegmentWrite32 (
@ -1217,18 +1193,19 @@ PciSegmentBitFieldOr32 (
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
AND, and writes the result back to the bit field in the 32-bit register. AND, and writes the result back to the bit field in the 32-bit register.
Reads the 32-bit PCI configuration register specified by Address, performs a
bitwise AND between the read result and the value specified by AndData, and
writes the result to the 32-bit PCI configuration register specified by
Address. The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are
serialized. Extra left bits in AndData are stripped.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
AND between the read result and the value specified by AndData, and writes the result
to the 32-bit PCI configuration register specified by Address. The value written to
the PCI configuration register is returned. This function must guarantee that all PCI
read and write operations are serialized. Extra left bits in AndData are stripped.
If any reserved bits in Address are set, then ASSERT(). If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
If StartBit is greater than 31, then ASSERT(). If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
@param Address PCI configuration register to write. @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field. @param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31. Range 0..31.
@ -1242,10 +1219,10 @@ PciSegmentBitFieldOr32 (
UINT32 UINT32
EFIAPI EFIAPI
PciSegmentBitFieldAnd32 ( PciSegmentBitFieldAnd32 (
IN UINT64 Address, IN UINT64 Address,
IN UINTN StartBit, IN UINTN StartBit,
IN UINTN EndBit, IN UINTN EndBit,
IN UINT32 AndData IN UINT32 AndData
) )
{ {
return PciSegmentWrite32 ( return PciSegmentWrite32 (
@ -1286,11 +1263,11 @@ PciSegmentBitFieldAnd32 (
UINT32 UINT32
EFIAPI EFIAPI
PciSegmentBitFieldAndThenOr32 ( PciSegmentBitFieldAndThenOr32 (
IN UINT64 Address, IN UINT64 Address,
IN UINTN StartBit, IN UINTN StartBit,
IN UINTN EndBit, IN UINTN EndBit,
IN UINT32 AndData, IN UINT32 AndData,
IN UINT32 OrData IN UINT32 OrData
) )
{ {
return PciSegmentWrite32 ( return PciSegmentWrite32 (
@ -1302,28 +1279,32 @@ PciSegmentBitFieldAndThenOr32 (
/** /**
Reads a range of PCI configuration registers into a caller supplied buffer. Reads a range of PCI configuration registers into a caller supplied buffer.
Reads the range of PCI configuration registers specified by StartAddress Reads the range of PCI configuration registers specified by StartAddress and
and Size into the buffer specified by Buffer. Size into the buffer specified by Buffer. This function only allows the PCI
This function only allows the PCI configuration registers from a single PCI function to be read. configuration registers from a single PCI function to be read. Size is
Size is returned. returned. When possible 32-bit PCI configuration read cycles are used to read
from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
and 16-bit PCI configuration read cycles may be used at the beginning and the
end of the range.
If any reserved bits in StartAddress are set, then ASSERT(). If StartAddress > 0x0FFFFFFF, then ASSERT().
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().
@param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register. @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
Function and Register.
@param Size Size in bytes of the transfer. @param Size Size in bytes of the transfer.
@param Buffer Pointer to a buffer receiving the data read. @param Buffer Pointer to a buffer receiving the data read.
@return The parameter of Size. @return Size
**/ **/
UINTN UINTN
EFIAPI EFIAPI
PciSegmentReadBuffer ( PciSegmentReadBuffer (
IN UINT64 StartAddress, IN UINT64 StartAddress,
IN UINTN Size, IN UINTN Size,
OUT VOID *Buffer OUT VOID *Buffer
) )
{ {
UINTN ReturnValue; UINTN ReturnValue;
@ -1393,18 +1374,23 @@ PciSegmentReadBuffer (
} }
/** /**
Copies the data in a caller supplied buffer to a specified range of PCI configuration space. Copies the data in a caller supplied buffer to a specified range of PCI
configuration space.
Writes the range of PCI configuration registers specified by StartAddress Writes the range of PCI configuration registers specified by StartAddress and
and Size from the buffer specified by Buffer. Size from the buffer specified by Buffer. This function only allows the PCI
This function only allows the PCI configuration registers from a single PCI function to be written. configuration registers from a single PCI function to be written. Size is
Size is returned. returned. When possible 32-bit PCI configuration write cycles are used to
write from StartAdress to StartAddress + Size. Due to alignment restrictions,
8-bit and 16-bit PCI configuration write cycles may be used at the beginning
and the end of the range.
If any reserved bits in StartAddress are set, then ASSERT(). If StartAddress > 0x0FFFFFFF, then ASSERT().
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().
@param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register. @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
Function and Register.
@param Size Size in bytes of the transfer. @param Size Size in bytes of the transfer.
@param Buffer Pointer to a buffer containing the data to write. @param Buffer Pointer to a buffer containing the data to write.
@ -1414,9 +1400,9 @@ PciSegmentReadBuffer (
UINTN UINTN
EFIAPI EFIAPI
PciSegmentWriteBuffer ( PciSegmentWriteBuffer (
IN UINT64 StartAddress, IN UINT64 StartAddress,
IN UINTN Size, IN UINTN Size,
IN VOID *Buffer IN VOID *Buffer
) )
{ {
UINTN ReturnValue; UINTN ReturnValue;

36
MdePkg/Library/UefiRuntimeLib/RuntimeService.c
View File

@ -87,7 +87,7 @@ EFI_STATUS
EFIAPI EFIAPI
EfiGetTime ( EfiGetTime (
OUT EFI_TIME *Time, OUT EFI_TIME *Time,
OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL
) )
{ {
return mRT->GetTime (Time, Capabilities); return mRT->GetTime (Time, Capabilities);
@ -186,7 +186,7 @@ EFI_STATUS
EFIAPI EFIAPI
EfiSetWakeupTime ( EfiSetWakeupTime (
IN BOOLEAN Enable, IN BOOLEAN Enable,
IN EFI_TIME *Time OPTIONAL IN EFI_TIME *Time OPTIONAL
) )
{ {
return mRT->SetWakeupTime (Enable, Time); return mRT->SetWakeupTime (Enable, Time);
@ -226,11 +226,11 @@ EfiSetWakeupTime (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
EfiGetVariable ( EfiGetVariable (
IN CHAR16 *VariableName, IN CHAR16 *VariableName,
IN EFI_GUID * VendorGuid, IN EFI_GUID *VendorGuid,
OUT UINT32 *Attributes OPTIONAL, OUT UINT32 *Attributes OPTIONAL,
IN OUT UINTN *DataSize, IN OUT UINTN *DataSize,
OUT VOID *Data OUT VOID *Data
) )
{ {
return mRT->GetVariable (VariableName, VendorGuid, Attributes, DataSize, Data); return mRT->GetVariable (VariableName, VendorGuid, Attributes, DataSize, Data);
@ -545,9 +545,9 @@ EfiSetVirtualAddressMap (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
EfiUpdateCapsule ( EfiUpdateCapsule (
IN EFI_CAPSULE_HEADER **CapsuleHeaderArray, IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,
IN UINTN CapsuleCount, IN UINTN CapsuleCount,
IN EFI_PHYSICAL_ADDRESS ScatterGatherList OPTIONAL IN EFI_PHYSICAL_ADDRESS ScatterGatherList OPTIONAL
) )
{ {
return mRT->UpdateCapsule ( return mRT->UpdateCapsule (
@ -595,10 +595,10 @@ EfiUpdateCapsule (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
EfiQueryCapsuleCapabilities ( EfiQueryCapsuleCapabilities (
IN EFI_CAPSULE_HEADER **CapsuleHeaderArray, IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,
IN UINTN CapsuleCount, IN UINTN CapsuleCount,
OUT UINT64 *MaximumCapsuleSize, OUT UINT64 *MaximumCapsuleSize,
OUT EFI_RESET_TYPE *ResetType OUT EFI_RESET_TYPE *ResetType
) )
{ {
return mRT->QueryCapsuleCapabilities ( return mRT->QueryCapsuleCapabilities (
@ -647,10 +647,10 @@ EfiQueryCapsuleCapabilities (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
EfiQueryVariableInfo ( EfiQueryVariableInfo (
IN UINT32 Attributes, IN UINT32 Attributes,
OUT UINT64 *MaximumVariableStorageSize, OUT UINT64 *MaximumVariableStorageSize,
OUT UINT64 *RemainingVariableStorageSize, OUT UINT64 *RemainingVariableStorageSize,
OUT UINT64 *MaximumVariableSize OUT UINT64 *MaximumVariableSize
) )
{ {
return mRT->QueryVariableInfo ( return mRT->QueryVariableInfo (

4
MdePkg/Library/UefiScsiLib/UefiScsiLib.c
View File

@ -192,7 +192,7 @@ ScsiTestUnitReadyCommand (
SCSI I/O Protocol in the UEFI Specification SCSI I/O Protocol in the UEFI Specification
for details on the possible return values. for details on the possible return values.
@param[out] TargetStatus The status returned by the SCSI target specified @param[out] TargetStatus The status returned by the SCSI target specified
by ScsiIo when the SCSI Request Packat was by ScsiIo when the SCSI Request Packet was
executed on the SCSI Host Controller. executed on the SCSI Host Controller.
See the EFI SCSI I/O Protocol in the UEFI See the EFI SCSI I/O Protocol in the UEFI
Specification for details on the possible Specification for details on the possible
@ -338,7 +338,7 @@ ScsiInquiryCommand (
UEFI Specification for details on the possible UEFI Specification for details on the possible
return values. return values.
@param[out] TargetStatus The status returned by the SCSI target specified @param[out] TargetStatus The status returned by the SCSI target specified
by ScsiIo when the SCSI Request Packat was executed by ScsiIo when the SCSI Request Packet was executed
on the SCSI Host Controller. See the EFI SCSI on the SCSI Host Controller. See the EFI SCSI
I/O Protocol in the UEFI Specification for details I/O Protocol in the UEFI Specification for details
on the possible return values. on the possible return values.

6
MdePkg/Library/UefiUsbLib/Hid.c
View File

@ -98,7 +98,7 @@ UsbGetHidDescriptor (
@retval EFI_SUCCESS The request executed successfully. @retval EFI_SUCCESS The request executed successfully.
@retval EFI_OUT_OF_RESOURCES The request could not be completed because the @retval EFI_OUT_OF_RESOURCES The request could not be completed because the
buffer specifed by DescriptorLength and DescriptorBuffer buffer specified by DescriptorLength and DescriptorBuffer
is not large enough to hold the result of the request. is not large enough to hold the result of the request.
@retval EFI_TIMEOUT A timeout occurred executing the request. @retval EFI_TIMEOUT A timeout occurred executing the request.
@retval EFI_DEVICE_ERROR The request failed due to a device error. @retval EFI_DEVICE_ERROR The request failed due to a device error.
@ -389,7 +389,7 @@ UsbSetReportRequest (
IN UINT8 Interface, IN UINT8 Interface,
IN UINT8 ReportId, IN UINT8 ReportId,
IN UINT8 ReportType, IN UINT8 ReportType,
IN UINT16 ReportLength, IN UINT16 ReportLen,
IN UINT8 *Report IN UINT8 *Report
) )
{ {
@ -415,7 +415,7 @@ UsbSetReportRequest (
EfiUsbDataOut, EfiUsbDataOut,
TIMEOUT_VALUE, TIMEOUT_VALUE,
Report, Report,
ReportLength, ReportLen,
&Status &Status
); );

2
MdePkg/Library/UefiUsbLib/UsbDxeLib.c
View File

@ -590,7 +590,7 @@ UsbGetStatus (
Retrieve the USB endpoint descriptor specified by UsbIo and EndPoint. Retrieve the USB endpoint descriptor specified by UsbIo and EndPoint.
If the USB endpoint descriptor can not be retrieved, then return EFI_NOT_FOUND. If the USB endpoint descriptor can not be retrieved, then return EFI_NOT_FOUND.
If the endpoint descriptor is found, then clear the halt fature of this USB endpoint. If the endpoint descriptor is found, then clear the halt feature of this USB endpoint.
The status of the transfer is returned in Status. The status of the transfer is returned in Status.
If UsbIo is NULL, then ASSERT(). If UsbIo is NULL, then ASSERT().
If Status is NULL, then ASSERT(). If Status is NULL, then ASSERT().