mirror of https://github.com/acidanthera/audk.git
Synchronize interface function comment from declaration in library class header file to implementation in library instance.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6957 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
klu2
parent
530e25f536
commit
070a76b193
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@ -68,7 +68,7 @@ SmbusLibConstructor (
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@param Status Return status for the executed command.
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This is an optional parameter and may be NULL.
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@return The actual number of bytes that are executed for this operation..
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@return The actual number of bytes that are executed for this operation.
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**/
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UINTN
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@ -79,7 +79,8 @@ _DriverUnloadHandler (
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@param ImageHandle ImageHandle of the loaded driver.
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@param SystemTable Pointer to the EFI System Table.
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@retval EFI_SUCCESS One or more of the drivers returned a success code.
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@retval EFI_SUCCESS The DXE Driver, DXE Runtime Driver, DXE SMM Driver,
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or UEFI Driver exited normally.
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@retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than SystemTable->Hdr.Revision.
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@retval Other Return value from ProcessModuleEntryPointList().
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@ -689,7 +689,6 @@ LookupUnicodeString (
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**/
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EFI_STATUS
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EFIAPI
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LookupUnicodeString2 (
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IN CONST CHAR8 *Language,
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@ -282,17 +282,17 @@ EfiSignalEventLegacyBoot (
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@retval Other FvDevicePathNode is valid and pointer to NameGuid was returned.
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**/
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EFI_GUID*
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EFI_GUID *
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EFIAPI
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EfiGetNameGuidFromFwVolDevicePathNode (
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IN CONST MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvFileDevicePathNode
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IN CONST MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvDevicePathNode
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)
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{
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ASSERT (FvFileDevicePathNode != NULL);
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ASSERT (FvDevicePathNode != NULL);
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if (DevicePathType (&FvFileDevicePathNode->Header) == MEDIA_DEVICE_PATH &&
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DevicePathSubType (&FvFileDevicePathNode->Header) == MEDIA_PIWG_FW_FILE_DP) {
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return (EFI_GUID *) &FvFileDevicePathNode->FvFileName;
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if (DevicePathType (&FvDevicePathNode->Header) == MEDIA_DEVICE_PATH &&
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DevicePathSubType (&FvDevicePathNode->Header) == MEDIA_PIWG_FW_FILE_DP) {
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return (EFI_GUID *) &FvDevicePathNode->FvFileName;
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}
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return NULL;
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@ -318,20 +318,20 @@ EfiGetNameGuidFromFwVolDevicePathNode (
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VOID
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EFIAPI
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EfiInitializeFwVolDevicepathNode (
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IN OUT MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvFileDevicePathNode,
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IN CONST EFI_GUID *NameGuid
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IN OUT MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvDevicePathNode,
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IN CONST EFI_GUID *NameGuid
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)
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{
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ASSERT (FvFileDevicePathNode != NULL);
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ASSERT (FvDevicePathNode != NULL);
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ASSERT (NameGuid != NULL);
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//
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// Use the new Device path that does not conflict with the UEFI
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//
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FvFileDevicePathNode->Header.Type = MEDIA_DEVICE_PATH;
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FvFileDevicePathNode->Header.SubType = MEDIA_PIWG_FW_FILE_DP;
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SetDevicePathNodeLength (&FvFileDevicePathNode->Header, sizeof (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH));
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FvDevicePathNode->Header.Type = MEDIA_DEVICE_PATH;
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FvDevicePathNode->Header.SubType = MEDIA_PIWG_FW_FILE_DP;
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SetDevicePathNodeLength (&FvDevicePathNode->Header, sizeof (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH));
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CopyGuid (&FvFileDevicePathNode->FvFileName, NameGuid);
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CopyGuid (&FvDevicePathNode->FvFileName, NameGuid);
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}
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@ -36,38 +36,42 @@
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#include <Library/BaseLib.h>
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/**
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Copy Length bytes from Source to Destination.
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Copies a source buffer to a destination buffer, and returns the destination buffer.
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@param DestinationBuffer Target of copy
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@param SourceBuffer Place to copy from
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@param Length Number of bytes to copy
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This function wraps the gBS->CopyMem().
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@return Destination
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@param DestinationBuffer Pointer to the destination buffer of the memory copy.
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@param SourceBuffer Pointer to the source buffer of the memory copy.
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@param Length Number of bytes to copy from SourceBuffer to DestinationBuffer.
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@return DestinationBuffer.
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**/
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VOID *
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EFIAPI
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InternalMemCopyMem (
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OUT VOID *DestinationBuffer,
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IN CONST VOID *SourceBuffer,
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OUT VOID *Destination,
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IN CONST VOID *Source,
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IN UINTN Length
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);
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/**
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Set Buffer to Value for Size bytes.
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Fills a target buffer with a byte value, and returns the target buffer.
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@param Buffer Memory to set.
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@param Length Number of bytes to set
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@param Value Value of the set operation.
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This function wraps the gBS->SetMem().
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@return Buffer
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@param Buffer Memory to set.
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@param Size Number of bytes to set.
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@param Value Value of the set operation.
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@return Buffer.
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**/
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VOID *
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EFIAPI
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InternalMemSetMem (
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OUT VOID *Buffer,
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IN UINTN Length,
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IN UINTN Size,
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IN UINT8 Value
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);
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@ -143,9 +143,12 @@ DxePciLibPciRootBridgeIoWriteWorker (
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}
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/**
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Register a PCI device so PCI configuration registers may be accessed after
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Registers a PCI device so PCI configuration registers may be accessed after
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SetVirtualAddressMap().
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Registers the PCI device specified by Address so all the PCI configuration registers
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associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
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If Address > 0x0FFFFFFF, then ASSERT().
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@param Address Address that encodes the PCI Bus, Device, Function and
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@ -181,7 +184,7 @@ PciRegisterForRuntimeAccess (
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@return The value read from the PCI configuration register.
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@return The read value from the PCI configuration register.
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**/
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UINT8
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@ -206,7 +209,7 @@ PciRead8 (
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@param Data The value to write.
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@param Value The value to write.
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@return The value written to the PCI configuration register.
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@ -215,12 +218,12 @@ UINT8
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EFIAPI
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PciWrite8 (
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IN UINTN Address,
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IN UINT8 Data
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IN UINT8 Value
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)
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{
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ASSERT_INVALID_PCI_ADDRESS (Address, 0);
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return (UINT8) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Data);
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return (UINT8) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);
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}
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/**
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@ -526,7 +529,7 @@ PciBitFieldAndThenOr8 (
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@return The value read from the PCI configuration register.
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@return The read value from the PCI configuration register.
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**/
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UINT16
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@ -552,7 +555,7 @@ PciRead16 (
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@param Data The value to write.
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@param Value The value to write.
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@return The value written to the PCI configuration register.
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@ -561,12 +564,12 @@ UINT16
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EFIAPI
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PciWrite16 (
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IN UINTN Address,
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IN UINT16 Data
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IN UINT16 Value
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)
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{
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ASSERT_INVALID_PCI_ADDRESS (Address, 1);
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return (UINT16) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Data);
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return (UINT16) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);
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}
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/**
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@ -880,7 +883,7 @@ PciBitFieldAndThenOr16 (
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@return The value read from the PCI configuration register.
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@return The read value from the PCI configuration register.
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**/
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UINT32
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@ -906,7 +909,7 @@ PciRead32 (
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@param Data The value to write.
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@param Value The value to write.
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@return The value written to the PCI configuration register.
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@ -915,12 +918,12 @@ UINT32
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EFIAPI
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PciWrite32 (
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IN UINTN Address,
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IN UINT32 Data
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IN UINT32 Value
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)
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{
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ASSERT_INVALID_PCI_ADDRESS (Address, 3);
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return DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Data);
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return DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Value);
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}
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/**
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@ -1339,7 +1342,7 @@ PciReadBuffer (
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@param Size Size in bytes of the transfer.
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@param Buffer Pointer to a buffer containing the data to write.
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@return Size
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@return Size written to StartAddress.
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**/
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UINTN
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@ -271,21 +271,19 @@ PciSegmentRegisterForRuntimeAccess (
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Reads an 8-bit PCI configuration register.
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Reads and returns the 8-bit PCI configuration register specified by Address.
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This function must guarantee that all PCI read and write operations are
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serialized.
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This function must guarantee that all PCI read and write operations are serialized.
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If any reserved bits in Address are set, then ASSERT().
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@param Address Address that encodes the PCI Segment, Bus, Device, Function and
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Register.
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@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
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@return The value read from the PCI configuration register.
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@return The 8-bit PCI configuration register specified by Address.
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**/
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UINT8
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EFIAPI
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PciSegmentRead8 (
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IN UINT64 Address
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IN UINT64 Address
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)
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{
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ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
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@ -296,15 +294,13 @@ PciSegmentRead8 (
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/**
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Writes an 8-bit PCI configuration register.
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Writes the 8-bit PCI configuration register specified by Address with the
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value specified by Value. Value is returned. This function must guarantee
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that all PCI read and write operations are serialized.
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Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
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Value is returned. This function must guarantee that all PCI read and write operations are serialized.
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If any reserved bits in Address are set, then ASSERT().
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If Address > 0x0FFFFFFF, then ASSERT().
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@param Address Address that encodes the PCI Segment, Bus, Device, Function and
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Register.
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@param Data The value to write.
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@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
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@param Value The value to write.
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@return The value written to the PCI configuration register.
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@ -312,103 +308,94 @@ PciSegmentRead8 (
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UINT8
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EFIAPI
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PciSegmentWrite8 (
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IN UINT64 Address,
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IN UINT8 Data
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IN UINT64 Address,
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IN UINT8 Value
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)
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{
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ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
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return (UINT8) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Data);
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return (UINT8) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);
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}
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/**
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Performs a bitwise OR of an 8-bit PCI configuration register with
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an 8-bit value.
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Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
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Reads the 8-bit PCI configuration register specified by Address, performs a
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bitwise OR between the read result and the value specified by
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OrData, and writes the result to the 8-bit PCI configuration register
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specified by Address. The value written to the PCI configuration register is
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returned. This function must guarantee that all PCI read and write operations
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are serialized.
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Reads the 8-bit PCI configuration register specified by Address,
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performs a bitwise OR between the read result and the value specified by OrData,
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and writes the result to the 8-bit PCI configuration register specified by Address.
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The value written to the PCI configuration register is returned.
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This function must guarantee that all PCI read and write operations are serialized.
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If any reserved bits in Address are set, then ASSERT().
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@param Address Address that encodes the PCI Segment, Bus, Device, Function and
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Register.
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@param OrData The value to OR with the PCI configuration register.
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@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
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@param OrData The value to OR with the PCI configuration register.
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@return The value written back to the PCI configuration register.
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@return The value written to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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PciSegmentOr8 (
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IN UINT64 Address,
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IN UINT8 OrData
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IN UINT64 Address,
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IN UINT8 OrData
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)
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{
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return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));
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}
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/**
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Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
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value.
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Reads the 8-bit PCI configuration register specified by Address, performs a
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bitwise AND between the read result and the value specified by AndData, and
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writes the result to the 8-bit PCI configuration register specified by
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Address. The value written to the PCI configuration register is returned.
|
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This function must guarantee that all PCI read and write operations are
|
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serialized.
|
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Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
|
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|
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Reads the 8-bit PCI configuration register specified by Address,
|
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performs a bitwise AND between the read result and the value specified by AndData,
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and writes the result to the 8-bit PCI configuration register specified by Address.
|
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The value written to the PCI configuration register is returned.
|
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This function must guarantee that all PCI read and write operations are serialized.
|
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If any reserved bits in Address are set, then ASSERT().
|
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|
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@param Address Address that encodes the PCI Segment, Bus, Device, Function and
|
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Register.
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@param AndData The value to AND with the PCI configuration register.
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@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
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@param AndData The value to AND with the PCI configuration register.
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@return The value written back to the PCI configuration register.
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@return The value written to the PCI configuration register.
|
||||
|
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**/
|
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UINT8
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EFIAPI
|
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PciSegmentAnd8 (
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IN UINT64 Address,
|
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IN UINT8 AndData
|
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IN UINT64 Address,
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IN UINT8 AndData
|
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)
|
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{
|
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return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));
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}
|
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|
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/**
|
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Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
|
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value, followed a bitwise OR with another 8-bit value.
|
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Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
|
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followed a bitwise OR with another 8-bit value.
|
||||
|
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Reads the 8-bit PCI configuration register specified by Address, performs a
|
||||
bitwise AND between the read result and the value specified by AndData,
|
||||
performs a bitwise OR between the result of the AND operation and
|
||||
the value specified by OrData, and writes the result to the 8-bit PCI
|
||||
configuration register specified by Address. The value written to the PCI
|
||||
configuration register is returned. This function must guarantee that all PCI
|
||||
read and write operations are serialized.
|
||||
Reads the 8-bit PCI configuration register specified by Address,
|
||||
performs a bitwise AND between the read result and the value specified by AndData,
|
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performs a bitwise OR between the result of the AND operation and the value specified by OrData,
|
||||
and writes the result to the 8-bit PCI configuration register specified by Address.
|
||||
The value written to the PCI configuration register is returned.
|
||||
This function must guarantee that all PCI read and write operations are serialized.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function and
|
||||
Register.
|
||||
@param AndData The value to AND with the PCI configuration register.
|
||||
@param OrData The value to OR with the result of the AND operation.
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
||||
@param AndData The value to AND with the PCI configuration register.
|
||||
@param OrData The value to OR with the PCI configuration register.
|
||||
|
||||
@return The value written back to the PCI configuration register.
|
||||
@return The value written to the PCI configuration register.
|
||||
|
||||
**/
|
||||
UINT8
|
||||
EFIAPI
|
||||
PciSegmentAndThenOr8 (
|
||||
IN UINT64 Address,
|
||||
IN UINT8 AndData,
|
||||
IN UINT8 OrData
|
||||
IN UINT64 Address,
|
||||
IN UINT8 AndData,
|
||||
IN UINT8 OrData
|
||||
)
|
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{
|
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return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));
|
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|
|
@ -438,9 +425,9 @@ PciSegmentAndThenOr8 (
|
|||
UINT8
|
||||
EFIAPI
|
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PciSegmentBitFieldRead8 (
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit
|
||||
)
|
||||
{
|
||||
return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
|
||||
|
|
@ -472,10 +459,10 @@ PciSegmentBitFieldRead8 (
|
|||
UINT8
|
||||
EFIAPI
|
||||
PciSegmentBitFieldWrite8 (
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT8 Value
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT8 Value
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite8 (
|
||||
|
|
@ -513,10 +500,10 @@ PciSegmentBitFieldWrite8 (
|
|||
UINT8
|
||||
EFIAPI
|
||||
PciSegmentBitFieldOr8 (
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT8 OrData
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT8 OrData
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite8 (
|
||||
|
|
@ -554,10 +541,10 @@ PciSegmentBitFieldOr8 (
|
|||
UINT8
|
||||
EFIAPI
|
||||
PciSegmentBitFieldAnd8 (
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT8 AndData
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT8 AndData
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite8 (
|
||||
|
|
@ -598,11 +585,11 @@ PciSegmentBitFieldAnd8 (
|
|||
UINT8
|
||||
EFIAPI
|
||||
PciSegmentBitFieldAndThenOr8 (
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT8 AndData,
|
||||
IN UINT8 OrData
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT8 AndData,
|
||||
IN UINT8 OrData
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite8 (
|
||||
|
|
@ -615,21 +602,20 @@ PciSegmentBitFieldAndThenOr8 (
|
|||
Reads a 16-bit PCI configuration register.
|
||||
|
||||
Reads and returns the 16-bit PCI configuration register specified by Address.
|
||||
This function must guarantee that all PCI read and write operations are
|
||||
serialized.
|
||||
This function must guarantee that all PCI read and write operations are serialized.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
||||
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function and
|
||||
Register.
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
||||
|
||||
@return The value read from the PCI configuration register.
|
||||
@return The 16-bit PCI configuration register specified by Address.
|
||||
|
||||
**/
|
||||
UINT16
|
||||
EFIAPI
|
||||
PciSegmentRead16 (
|
||||
IN UINT64 Address
|
||||
IN UINT64 Address
|
||||
)
|
||||
{
|
||||
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
|
||||
|
|
@ -640,29 +626,28 @@ PciSegmentRead16 (
|
|||
/**
|
||||
Writes a 16-bit PCI configuration register.
|
||||
|
||||
Writes the 16-bit PCI configuration register specified by Address with the
|
||||
value specified by Value. Value is returned. This function must guarantee
|
||||
that all PCI read and write operations are serialized.
|
||||
Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
|
||||
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
||||
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function and
|
||||
Register.
|
||||
@param Data The value to write.
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
||||
@param Value The value to write.
|
||||
|
||||
@return The value written to the PCI configuration register.
|
||||
@return The parameter of Value.
|
||||
|
||||
**/
|
||||
UINT16
|
||||
EFIAPI
|
||||
PciSegmentWrite16 (
|
||||
IN UINT64 Address,
|
||||
IN UINT16 Data
|
||||
IN UINT64 Address,
|
||||
IN UINT16 Value
|
||||
)
|
||||
{
|
||||
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
|
||||
|
||||
return (UINT16) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Data);
|
||||
return (UINT16) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -677,6 +662,7 @@ PciSegmentWrite16 (
|
|||
are serialized.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
||||
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function and
|
||||
Register.
|
||||
|
|
@ -688,71 +674,68 @@ PciSegmentWrite16 (
|
|||
UINT16
|
||||
EFIAPI
|
||||
PciSegmentOr16 (
|
||||
IN UINT64 Address,
|
||||
IN UINT16 OrData
|
||||
IN UINT64 Address,
|
||||
IN UINT16 OrData
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
|
||||
}
|
||||
|
||||
/**
|
||||
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
|
||||
value.
|
||||
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
|
||||
|
||||
Reads the 16-bit PCI configuration register specified by Address, performs a
|
||||
bitwise AND between the read result and the value specified by AndData, and
|
||||
writes the result to the 16-bit PCI configuration register specified by
|
||||
Address. The value written to the PCI configuration register is returned.
|
||||
This function must guarantee that all PCI read and write operations are
|
||||
serialized.
|
||||
Reads the 16-bit PCI configuration register specified by Address,
|
||||
performs a bitwise AND between the read result and the value specified by AndData,
|
||||
and writes the result to the 16-bit PCI configuration register specified by Address.
|
||||
The value written to the PCI configuration register is returned.
|
||||
This function must guarantee that all PCI read and write operations are serialized.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
||||
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function and
|
||||
Register.
|
||||
@param AndData The value to AND with the PCI configuration register.
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
||||
@param AndData The value to AND with the PCI configuration register.
|
||||
|
||||
@return The value written back to the PCI configuration register.
|
||||
@return The value written to the PCI configuration register.
|
||||
|
||||
**/
|
||||
UINT16
|
||||
EFIAPI
|
||||
PciSegmentAnd16 (
|
||||
IN UINT64 Address,
|
||||
IN UINT16 AndData
|
||||
IN UINT64 Address,
|
||||
IN UINT16 AndData
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
|
||||
}
|
||||
|
||||
/**
|
||||
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
|
||||
value, followed a bitwise OR with another 16-bit value.
|
||||
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
|
||||
followed a bitwise OR with another 16-bit value.
|
||||
|
||||
Reads the 16-bit PCI configuration register specified by Address, performs a
|
||||
bitwise AND between the read result and the value specified by AndData,
|
||||
performs a bitwise OR between the result of the AND operation and
|
||||
the value specified by OrData, and writes the result to the 16-bit PCI
|
||||
configuration register specified by Address. The value written to the PCI
|
||||
configuration register is returned. This function must guarantee that all PCI
|
||||
read and write operations are serialized.
|
||||
Reads the 16-bit PCI configuration register specified by Address,
|
||||
performs a bitwise AND between the read result and the value specified by AndData,
|
||||
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
|
||||
and writes the result to the 16-bit PCI configuration register specified by Address.
|
||||
The value written to the PCI configuration register is returned.
|
||||
This function must guarantee that all PCI read and write operations are serialized.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
||||
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function and
|
||||
Register.
|
||||
@param AndData The value to AND with the PCI configuration register.
|
||||
@param OrData The value to OR with the result of the AND operation.
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
||||
@param AndData The value to AND with the PCI configuration register.
|
||||
@param OrData The value to OR with the PCI configuration register.
|
||||
|
||||
@return The value written back to the PCI configuration register.
|
||||
@return The value written to the PCI configuration register.
|
||||
|
||||
**/
|
||||
UINT16
|
||||
EFIAPI
|
||||
PciSegmentAndThenOr16 (
|
||||
IN UINT64 Address,
|
||||
IN UINT16 AndData,
|
||||
IN UINT16 OrData
|
||||
IN UINT64 Address,
|
||||
IN UINT16 AndData,
|
||||
IN UINT16 OrData
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
|
||||
|
|
@ -766,6 +749,7 @@ PciSegmentAndThenOr16 (
|
|||
returned.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
||||
If StartBit is greater than 15, then ASSERT().
|
||||
If EndBit is greater than 15, then ASSERT().
|
||||
If EndBit is less than StartBit, then ASSERT().
|
||||
|
|
@ -782,9 +766,9 @@ PciSegmentAndThenOr16 (
|
|||
UINT16
|
||||
EFIAPI
|
||||
PciSegmentBitFieldRead16 (
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit
|
||||
)
|
||||
{
|
||||
return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
|
||||
|
|
@ -799,6 +783,7 @@ PciSegmentBitFieldRead16 (
|
|||
16-bit register is returned.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
||||
If StartBit is greater than 15, then ASSERT().
|
||||
If EndBit is greater than 15, then ASSERT().
|
||||
If EndBit is less than StartBit, then ASSERT().
|
||||
|
|
@ -816,10 +801,10 @@ PciSegmentBitFieldRead16 (
|
|||
UINT16
|
||||
EFIAPI
|
||||
PciSegmentBitFieldWrite16 (
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT16 Value
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT16 Value
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite16 (
|
||||
|
|
@ -829,17 +814,12 @@ PciSegmentBitFieldWrite16 (
|
|||
}
|
||||
|
||||
/**
|
||||
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
|
||||
writes the result back to the bit field in the 16-bit port.
|
||||
|
||||
Reads the 16-bit PCI configuration register specified by Address, performs a
|
||||
bitwise OR between the read result and the value specified by
|
||||
OrData, and writes the result to the 16-bit PCI configuration register
|
||||
specified by Address. The value written to the PCI configuration register is
|
||||
returned. This function must guarantee that all PCI read and write operations
|
||||
are serialized. Extra left bits in OrData are stripped.
|
||||
Reads the 16-bit PCI configuration register specified by Address,
|
||||
performs a bitwise OR between the read result and the value specified by OrData,
|
||||
and writes the result to the 16-bit PCI configuration register specified by Address.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
||||
If StartBit is greater than 15, then ASSERT().
|
||||
If EndBit is greater than 15, then ASSERT().
|
||||
If EndBit is less than StartBit, then ASSERT().
|
||||
|
|
@ -857,10 +837,10 @@ PciSegmentBitFieldWrite16 (
|
|||
UINT16
|
||||
EFIAPI
|
||||
PciSegmentBitFieldOr16 (
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT16 OrData
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT16 OrData
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite16 (
|
||||
|
|
@ -870,38 +850,39 @@ PciSegmentBitFieldOr16 (
|
|||
}
|
||||
|
||||
/**
|
||||
Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
|
||||
AND, and writes the result back to the bit field in the 16-bit register.
|
||||
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
|
||||
and writes the result back to the bit field in the 16-bit port.
|
||||
|
||||
Reads the 16-bit PCI configuration register specified by Address, performs a
|
||||
bitwise AND between the read result and the value specified by AndData, and
|
||||
writes the result to the 16-bit PCI configuration register specified by
|
||||
Address. The value written to the PCI configuration register is returned.
|
||||
This function must guarantee that all PCI read and write operations are
|
||||
serialized. Extra left bits in AndData are stripped.
|
||||
Reads the 16-bit PCI configuration register specified by Address,
|
||||
performs a bitwise OR between the read result and the value specified by OrData,
|
||||
and writes the result to the 16-bit PCI configuration register specified by Address.
|
||||
The value written to the PCI configuration register is returned.
|
||||
This function must guarantee that all PCI read and write operations are serialized.
|
||||
Extra left bits in OrData are stripped.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If StartBit is greater than 15, then ASSERT().
|
||||
If EndBit is greater than 15, then ASSERT().
|
||||
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
||||
If StartBit is greater than 7, then ASSERT().
|
||||
If EndBit is greater than 7, then ASSERT().
|
||||
If EndBit is less than StartBit, then ASSERT().
|
||||
|
||||
@param Address PCI configuration register to write.
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
||||
@param StartBit The ordinal of the least significant bit in the bit field.
|
||||
Range 0..15.
|
||||
The ordinal of the least significant bit in a byte is bit 0.
|
||||
@param EndBit The ordinal of the most significant bit in the bit field.
|
||||
Range 0..15.
|
||||
@param AndData The value to AND with the PCI configuration register.
|
||||
The ordinal of the most significant bit in a byte is bit 7.
|
||||
@param AndData The value to AND with the read value from the PCI configuration register.
|
||||
|
||||
@return The value written back to the PCI configuration register.
|
||||
@return The value written to the PCI configuration register.
|
||||
|
||||
**/
|
||||
UINT16
|
||||
EFIAPI
|
||||
PciSegmentBitFieldAnd16 (
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT16 AndData
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT16 AndData
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite16 (
|
||||
|
|
@ -942,11 +923,11 @@ PciSegmentBitFieldAnd16 (
|
|||
UINT16
|
||||
EFIAPI
|
||||
PciSegmentBitFieldAndThenOr16 (
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT16 AndData,
|
||||
IN UINT16 OrData
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT16 AndData,
|
||||
IN UINT16 OrData
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite16 (
|
||||
|
|
@ -959,21 +940,20 @@ PciSegmentBitFieldAndThenOr16 (
|
|||
Reads a 32-bit PCI configuration register.
|
||||
|
||||
Reads and returns the 32-bit PCI configuration register specified by Address.
|
||||
This function must guarantee that all PCI read and write operations are
|
||||
serialized.
|
||||
This function must guarantee that all PCI read and write operations are serialized.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
||||
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function and
|
||||
Register.
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
||||
|
||||
@return The value read from the PCI configuration register.
|
||||
@return The 32-bit PCI configuration register specified by Address.
|
||||
|
||||
**/
|
||||
UINT32
|
||||
EFIAPI
|
||||
PciSegmentRead32 (
|
||||
IN UINT64 Address
|
||||
IN UINT64 Address
|
||||
)
|
||||
{
|
||||
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
|
||||
|
|
@ -984,119 +964,113 @@ PciSegmentRead32 (
|
|||
/**
|
||||
Writes a 32-bit PCI configuration register.
|
||||
|
||||
Writes the 32-bit PCI configuration register specified by Address with the
|
||||
value specified by Value. Value is returned. This function must guarantee
|
||||
that all PCI read and write operations are serialized.
|
||||
Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
|
||||
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
||||
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function and
|
||||
Register.
|
||||
@param Data The value to write.
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
||||
@param Value The value to write.
|
||||
|
||||
@return The parameter of Value.
|
||||
|
||||
**/
|
||||
UINT32
|
||||
EFIAPI
|
||||
PciSegmentWrite32 (
|
||||
IN UINT64 Address,
|
||||
IN UINT32 Value
|
||||
)
|
||||
{
|
||||
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
|
||||
|
||||
return DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Value);
|
||||
}
|
||||
|
||||
/**
|
||||
Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
|
||||
|
||||
Reads the 32-bit PCI configuration register specified by Address,
|
||||
performs a bitwise OR between the read result and the value specified by OrData,
|
||||
and writes the result to the 32-bit PCI configuration register specified by Address.
|
||||
The value written to the PCI configuration register is returned.
|
||||
This function must guarantee that all PCI read and write operations are serialized.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
||||
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
||||
@param OrData The value to OR with the PCI configuration register.
|
||||
|
||||
@return The value written to the PCI configuration register.
|
||||
|
||||
**/
|
||||
UINT32
|
||||
EFIAPI
|
||||
PciSegmentWrite32 (
|
||||
IN UINT64 Address,
|
||||
IN UINT32 Data
|
||||
)
|
||||
{
|
||||
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
|
||||
|
||||
return DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Data);
|
||||
}
|
||||
|
||||
/**
|
||||
Performs a bitwise OR of a 32-bit PCI configuration register with
|
||||
a 32-bit value.
|
||||
|
||||
Reads the 32-bit PCI configuration register specified by Address, performs a
|
||||
bitwise OR between the read result and the value specified by
|
||||
OrData, and writes the result to the 32-bit PCI configuration register
|
||||
specified by Address. The value written to the PCI configuration register is
|
||||
returned. This function must guarantee that all PCI read and write operations
|
||||
are serialized.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function and
|
||||
Register.
|
||||
@param OrData The value to OR with the PCI configuration register.
|
||||
|
||||
@return The value written back to the PCI configuration register.
|
||||
|
||||
**/
|
||||
UINT32
|
||||
EFIAPI
|
||||
PciSegmentOr32 (
|
||||
IN UINT64 Address,
|
||||
IN UINT32 OrData
|
||||
IN UINT64 Address,
|
||||
IN UINT32 OrData
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
|
||||
}
|
||||
|
||||
/**
|
||||
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
|
||||
value.
|
||||
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
|
||||
|
||||
Reads the 32-bit PCI configuration register specified by Address, performs a
|
||||
bitwise AND between the read result and the value specified by AndData, and
|
||||
writes the result to the 32-bit PCI configuration register specified by
|
||||
Address. The value written to the PCI configuration register is returned.
|
||||
This function must guarantee that all PCI read and write operations are
|
||||
serialized.
|
||||
Reads the 32-bit PCI configuration register specified by Address,
|
||||
performs a bitwise AND between the read result and the value specified by AndData,
|
||||
and writes the result to the 32-bit PCI configuration register specified by Address.
|
||||
The value written to the PCI configuration register is returned.
|
||||
This function must guarantee that all PCI read and write operations are serialized.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
||||
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function and
|
||||
Register.
|
||||
@param AndData The value to AND with the PCI configuration register.
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
||||
@param AndData The value to AND with the PCI configuration register.
|
||||
|
||||
@return The value written back to the PCI configuration register.
|
||||
@return The value written to the PCI configuration register.
|
||||
|
||||
**/
|
||||
UINT32
|
||||
EFIAPI
|
||||
PciSegmentAnd32 (
|
||||
IN UINT64 Address,
|
||||
IN UINT32 AndData
|
||||
IN UINT64 Address,
|
||||
IN UINT32 AndData
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
|
||||
}
|
||||
|
||||
/**
|
||||
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
|
||||
value, followed a bitwise OR with another 32-bit value.
|
||||
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
|
||||
followed a bitwise OR with another 32-bit value.
|
||||
|
||||
Reads the 32-bit PCI configuration register specified by Address, performs a
|
||||
bitwise AND between the read result and the value specified by AndData,
|
||||
performs a bitwise OR between the result of the AND operation and
|
||||
the value specified by OrData, and writes the result to the 32-bit PCI
|
||||
configuration register specified by Address. The value written to the PCI
|
||||
configuration register is returned. This function must guarantee that all PCI
|
||||
read and write operations are serialized.
|
||||
Reads the 32-bit PCI configuration register specified by Address,
|
||||
performs a bitwise AND between the read result and the value specified by AndData,
|
||||
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
|
||||
and writes the result to the 32-bit PCI configuration register specified by Address.
|
||||
The value written to the PCI configuration register is returned.
|
||||
This function must guarantee that all PCI read and write operations are serialized.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
||||
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function and
|
||||
Register.
|
||||
@param AndData The value to AND with the PCI configuration register.
|
||||
@param OrData The value to OR with the result of the AND operation.
|
||||
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
||||
@param AndData The value to AND with the PCI configuration register.
|
||||
@param OrData The value to OR with the PCI configuration register.
|
||||
|
||||
@return The value written back to the PCI configuration register.
|
||||
@return The value written to the PCI configuration register.
|
||||
|
||||
**/
|
||||
UINT32
|
||||
EFIAPI
|
||||
PciSegmentAndThenOr32 (
|
||||
IN UINT64 Address,
|
||||
IN UINT32 AndData,
|
||||
IN UINT32 OrData
|
||||
IN UINT64 Address,
|
||||
IN UINT32 AndData,
|
||||
IN UINT32 OrData
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
|
||||
|
|
@ -1110,6 +1084,7 @@ PciSegmentAndThenOr32 (
|
|||
returned.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
||||
If StartBit is greater than 31, then ASSERT().
|
||||
If EndBit is greater than 31, then ASSERT().
|
||||
If EndBit is less than StartBit, then ASSERT().
|
||||
|
|
@ -1126,9 +1101,9 @@ PciSegmentAndThenOr32 (
|
|||
UINT32
|
||||
EFIAPI
|
||||
PciSegmentBitFieldRead32 (
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit
|
||||
)
|
||||
{
|
||||
return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
|
||||
|
|
@ -1143,6 +1118,7 @@ PciSegmentBitFieldRead32 (
|
|||
32-bit register is returned.
|
||||
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
||||
If StartBit is greater than 31, then ASSERT().
|
||||
If EndBit is greater than 31, then ASSERT().
|
||||
If EndBit is less than StartBit, then ASSERT().
|
||||
|
|
@ -1160,10 +1136,10 @@ PciSegmentBitFieldRead32 (
|
|||
UINT32
|
||||
EFIAPI
|
||||
PciSegmentBitFieldWrite32 (
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT32 Value
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT32 Value
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite32 (
|
||||
|
|
@ -1201,10 +1177,10 @@ PciSegmentBitFieldWrite32 (
|
|||
UINT32
|
||||
EFIAPI
|
||||
PciSegmentBitFieldOr32 (
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT32 OrData
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT32 OrData
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite32 (
|
||||
|
|
@ -1217,18 +1193,19 @@ PciSegmentBitFieldOr32 (
|
|||
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
|
||||
AND, and writes the result back to the bit field in the 32-bit register.
|
||||
|
||||
Reads the 32-bit PCI configuration register specified by Address, performs a
|
||||
bitwise AND between the read result and the value specified by AndData, and
|
||||
writes the result to the 32-bit PCI configuration register specified by
|
||||
Address. The value written to the PCI configuration register is returned.
|
||||
This function must guarantee that all PCI read and write operations are
|
||||
serialized. Extra left bits in AndData are stripped.
|
||||
|
||||
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
|
||||
AND between the read result and the value specified by AndData, and writes the result
|
||||
to the 32-bit PCI configuration register specified by Address. The value written to
|
||||
the PCI configuration register is returned. This function must guarantee that all PCI
|
||||
read and write operations are serialized. Extra left bits in AndData are stripped.
|
||||
If any reserved bits in Address are set, then ASSERT().
|
||||
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
||||
If StartBit is greater than 31, then ASSERT().
|
||||
If EndBit is greater than 31, then ASSERT().
|
||||
If EndBit is less than StartBit, then ASSERT().
|
||||
|
||||
|
||||
@param Address PCI configuration register to write.
|
||||
@param StartBit The ordinal of the least significant bit in the bit field.
|
||||
Range 0..31.
|
||||
|
|
@ -1242,10 +1219,10 @@ PciSegmentBitFieldOr32 (
|
|||
UINT32
|
||||
EFIAPI
|
||||
PciSegmentBitFieldAnd32 (
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT32 AndData
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT32 AndData
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite32 (
|
||||
|
|
@ -1286,11 +1263,11 @@ PciSegmentBitFieldAnd32 (
|
|||
UINT32
|
||||
EFIAPI
|
||||
PciSegmentBitFieldAndThenOr32 (
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT32 AndData,
|
||||
IN UINT32 OrData
|
||||
IN UINT64 Address,
|
||||
IN UINTN StartBit,
|
||||
IN UINTN EndBit,
|
||||
IN UINT32 AndData,
|
||||
IN UINT32 OrData
|
||||
)
|
||||
{
|
||||
return PciSegmentWrite32 (
|
||||
|
|
@ -1302,28 +1279,32 @@ PciSegmentBitFieldAndThenOr32 (
|
|||
/**
|
||||
Reads a range of PCI configuration registers into a caller supplied buffer.
|
||||
|
||||
Reads the range of PCI configuration registers specified by StartAddress
|
||||
and Size into the buffer specified by Buffer.
|
||||
This function only allows the PCI configuration registers from a single PCI function to be read.
|
||||
Size is returned.
|
||||
Reads the range of PCI configuration registers specified by StartAddress and
|
||||
Size into the buffer specified by Buffer. This function only allows the PCI
|
||||
configuration registers from a single PCI function to be read. Size is
|
||||
returned. When possible 32-bit PCI configuration read cycles are used to read
|
||||
from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
|
||||
and 16-bit PCI configuration read cycles may be used at the beginning and the
|
||||
end of the range.
|
||||
|
||||
If any reserved bits in StartAddress are set, then ASSERT().
|
||||
If StartAddress > 0x0FFFFFFF, then ASSERT().
|
||||
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
|
||||
If Size > 0 and Buffer is NULL, then ASSERT().
|
||||
|
||||
@param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
||||
@param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
|
||||
Function and Register.
|
||||
@param Size Size in bytes of the transfer.
|
||||
@param Buffer Pointer to a buffer receiving the data read.
|
||||
|
||||
@return The parameter of Size.
|
||||
@return Size
|
||||
|
||||
**/
|
||||
UINTN
|
||||
EFIAPI
|
||||
PciSegmentReadBuffer (
|
||||
IN UINT64 StartAddress,
|
||||
IN UINTN Size,
|
||||
OUT VOID *Buffer
|
||||
IN UINT64 StartAddress,
|
||||
IN UINTN Size,
|
||||
OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
UINTN ReturnValue;
|
||||
|
|
@ -1393,18 +1374,23 @@ PciSegmentReadBuffer (
|
|||
}
|
||||
|
||||
/**
|
||||
Copies the data in a caller supplied buffer to a specified range of PCI configuration space.
|
||||
Copies the data in a caller supplied buffer to a specified range of PCI
|
||||
configuration space.
|
||||
|
||||
Writes the range of PCI configuration registers specified by StartAddress
|
||||
and Size from the buffer specified by Buffer.
|
||||
This function only allows the PCI configuration registers from a single PCI function to be written.
|
||||
Size is returned.
|
||||
Writes the range of PCI configuration registers specified by StartAddress and
|
||||
Size from the buffer specified by Buffer. This function only allows the PCI
|
||||
configuration registers from a single PCI function to be written. Size is
|
||||
returned. When possible 32-bit PCI configuration write cycles are used to
|
||||
write from StartAdress to StartAddress + Size. Due to alignment restrictions,
|
||||
8-bit and 16-bit PCI configuration write cycles may be used at the beginning
|
||||
and the end of the range.
|
||||
|
||||
If any reserved bits in StartAddress are set, then ASSERT().
|
||||
If StartAddress > 0x0FFFFFFF, then ASSERT().
|
||||
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
|
||||
If Size > 0 and Buffer is NULL, then ASSERT().
|
||||
|
||||
@param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
||||
@param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
|
||||
Function and Register.
|
||||
@param Size Size in bytes of the transfer.
|
||||
@param Buffer Pointer to a buffer containing the data to write.
|
||||
|
||||
|
|
@ -1414,9 +1400,9 @@ PciSegmentReadBuffer (
|
|||
UINTN
|
||||
EFIAPI
|
||||
PciSegmentWriteBuffer (
|
||||
IN UINT64 StartAddress,
|
||||
IN UINTN Size,
|
||||
IN VOID *Buffer
|
||||
IN UINT64 StartAddress,
|
||||
IN UINTN Size,
|
||||
IN VOID *Buffer
|
||||
)
|
||||
{
|
||||
UINTN ReturnValue;
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@ EFI_STATUS
|
|||
EFIAPI
|
||||
EfiGetTime (
|
||||
OUT EFI_TIME *Time,
|
||||
OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL
|
||||
OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL
|
||||
)
|
||||
{
|
||||
return mRT->GetTime (Time, Capabilities);
|
||||
|
|
@ -186,7 +186,7 @@ EFI_STATUS
|
|||
EFIAPI
|
||||
EfiSetWakeupTime (
|
||||
IN BOOLEAN Enable,
|
||||
IN EFI_TIME *Time OPTIONAL
|
||||
IN EFI_TIME *Time OPTIONAL
|
||||
)
|
||||
{
|
||||
return mRT->SetWakeupTime (Enable, Time);
|
||||
|
|
@ -226,11 +226,11 @@ EfiSetWakeupTime (
|
|||
EFI_STATUS
|
||||
EFIAPI
|
||||
EfiGetVariable (
|
||||
IN CHAR16 *VariableName,
|
||||
IN EFI_GUID * VendorGuid,
|
||||
OUT UINT32 *Attributes OPTIONAL,
|
||||
IN OUT UINTN *DataSize,
|
||||
OUT VOID *Data
|
||||
IN CHAR16 *VariableName,
|
||||
IN EFI_GUID *VendorGuid,
|
||||
OUT UINT32 *Attributes OPTIONAL,
|
||||
IN OUT UINTN *DataSize,
|
||||
OUT VOID *Data
|
||||
)
|
||||
{
|
||||
return mRT->GetVariable (VariableName, VendorGuid, Attributes, DataSize, Data);
|
||||
|
|
@ -545,9 +545,9 @@ EfiSetVirtualAddressMap (
|
|||
EFI_STATUS
|
||||
EFIAPI
|
||||
EfiUpdateCapsule (
|
||||
IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,
|
||||
IN UINTN CapsuleCount,
|
||||
IN EFI_PHYSICAL_ADDRESS ScatterGatherList OPTIONAL
|
||||
IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,
|
||||
IN UINTN CapsuleCount,
|
||||
IN EFI_PHYSICAL_ADDRESS ScatterGatherList OPTIONAL
|
||||
)
|
||||
{
|
||||
return mRT->UpdateCapsule (
|
||||
|
|
@ -595,10 +595,10 @@ EfiUpdateCapsule (
|
|||
EFI_STATUS
|
||||
EFIAPI
|
||||
EfiQueryCapsuleCapabilities (
|
||||
IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,
|
||||
IN UINTN CapsuleCount,
|
||||
OUT UINT64 *MaximumCapsuleSize,
|
||||
OUT EFI_RESET_TYPE *ResetType
|
||||
IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,
|
||||
IN UINTN CapsuleCount,
|
||||
OUT UINT64 *MaximumCapsuleSize,
|
||||
OUT EFI_RESET_TYPE *ResetType
|
||||
)
|
||||
{
|
||||
return mRT->QueryCapsuleCapabilities (
|
||||
|
|
@ -647,10 +647,10 @@ EfiQueryCapsuleCapabilities (
|
|||
EFI_STATUS
|
||||
EFIAPI
|
||||
EfiQueryVariableInfo (
|
||||
IN UINT32 Attributes,
|
||||
OUT UINT64 *MaximumVariableStorageSize,
|
||||
OUT UINT64 *RemainingVariableStorageSize,
|
||||
OUT UINT64 *MaximumVariableSize
|
||||
IN UINT32 Attributes,
|
||||
OUT UINT64 *MaximumVariableStorageSize,
|
||||
OUT UINT64 *RemainingVariableStorageSize,
|
||||
OUT UINT64 *MaximumVariableSize
|
||||
)
|
||||
{
|
||||
return mRT->QueryVariableInfo (
|
||||
|
|
|
|||
|
|
@ -192,7 +192,7 @@ ScsiTestUnitReadyCommand (
|
|||
SCSI I/O Protocol in the UEFI Specification
|
||||
for details on the possible return values.
|
||||
@param[out] TargetStatus The status returned by the SCSI target specified
|
||||
by ScsiIo when the SCSI Request Packat was
|
||||
by ScsiIo when the SCSI Request Packet was
|
||||
executed on the SCSI Host Controller.
|
||||
See the EFI SCSI I/O Protocol in the UEFI
|
||||
Specification for details on the possible
|
||||
|
|
@ -338,7 +338,7 @@ ScsiInquiryCommand (
|
|||
UEFI Specification for details on the possible
|
||||
return values.
|
||||
@param[out] TargetStatus The status returned by the SCSI target specified
|
||||
by ScsiIo when the SCSI Request Packat was executed
|
||||
by ScsiIo when the SCSI Request Packet was executed
|
||||
on the SCSI Host Controller. See the EFI SCSI
|
||||
I/O Protocol in the UEFI Specification for details
|
||||
on the possible return values.
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ UsbGetHidDescriptor (
|
|||
|
||||
@retval EFI_SUCCESS The request executed successfully.
|
||||
@retval EFI_OUT_OF_RESOURCES The request could not be completed because the
|
||||
buffer specifed by DescriptorLength and DescriptorBuffer
|
||||
buffer specified by DescriptorLength and DescriptorBuffer
|
||||
is not large enough to hold the result of the request.
|
||||
@retval EFI_TIMEOUT A timeout occurred executing the request.
|
||||
@retval EFI_DEVICE_ERROR The request failed due to a device error.
|
||||
|
|
@ -389,7 +389,7 @@ UsbSetReportRequest (
|
|||
IN UINT8 Interface,
|
||||
IN UINT8 ReportId,
|
||||
IN UINT8 ReportType,
|
||||
IN UINT16 ReportLength,
|
||||
IN UINT16 ReportLen,
|
||||
IN UINT8 *Report
|
||||
)
|
||||
{
|
||||
|
|
@ -415,7 +415,7 @@ UsbSetReportRequest (
|
|||
EfiUsbDataOut,
|
||||
TIMEOUT_VALUE,
|
||||
Report,
|
||||
ReportLength,
|
||||
ReportLen,
|
||||
&Status
|
||||
);
|
||||
|
||||
|
|
|
|||
|
|
@ -590,7 +590,7 @@ UsbGetStatus (
|
|||
|
||||
Retrieve the USB endpoint descriptor specified by UsbIo and EndPoint.
|
||||
If the USB endpoint descriptor can not be retrieved, then return EFI_NOT_FOUND.
|
||||
If the endpoint descriptor is found, then clear the halt fature of this USB endpoint.
|
||||
If the endpoint descriptor is found, then clear the halt feature of this USB endpoint.
|
||||
The status of the transfer is returned in Status.
|
||||
If UsbIo is NULL, then ASSERT().
|
||||
If Status is NULL, then ASSERT().
|
||||
|
|
|
|||
Loading…
Reference in New Issue