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UefiCpuPkg MtrrLib: For MtrrSetAllMtrrs(), do not set FE/E bits in IA32_MTRR_DEF_TYPE MSR after the MSR is restored. 

Signed-off-by: Sun Rui <rui.sun@intel.com>
Reviewed-by: Fan Jeff <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13182 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
rsun3 2012-04-11 01:41:29 +00:00
parent 48604ef952
commit 0779e5bfb0
1 changed files with 27 additions and 11 deletions
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38
UefiCpuPkg/Library/MtrrLib/MtrrLib.c
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@ -1,7 +1,7 @@
/** @file
MTRR setting library
Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -203,26 +203,20 @@ PreMtrrChange (
return Value;
}
/**
Cleaning up after programming MTRRs.
This function will do some clean up after programming MTRRs:
enable MTRR caching functionality, and enable cache
Flush all TLBs, re-enable caching, restore CR4.
@param Cr4 CR4 value to restore
**/
VOID
PostMtrrChange (
UINTN Cr4
PostMtrrChangeEnableCache (
IN UINTN Cr4
)
{
//
// Enable Cache MTRR
//
AsmMsrBitFieldWrite64 (MTRR_LIB_IA32_MTRR_DEF_TYPE, 10, 11, 3);
//
// Flush all TLBs
//
@ -239,6 +233,28 @@ PostMtrrChange (
AsmWriteCr4 (Cr4);
}
/**
Cleaning up after programming MTRRs.
This function will do some clean up after programming MTRRs:
enable MTRR caching functionality, and enable cache
@param Cr4 CR4 value to restore
**/
VOID
PostMtrrChange (
IN UINTN Cr4
)
{
//
// Enable Cache MTRR
//
AsmMsrBitFieldWrite64 (MTRR_LIB_IA32_MTRR_DEF_TYPE, 10, 11, 3);
PostMtrrChangeEnableCache (Cr4);
}
/**
Programs fixed MTRRs registers.
@ -1502,7 +1518,7 @@ MtrrSetAllMtrrs (
//
AsmWriteMsr64 (MTRR_LIB_IA32_MTRR_DEF_TYPE, MtrrSetting->MtrrDefType);
PostMtrrChange (Cr4);
PostMtrrChangeEnableCache (Cr4);
return MtrrSetting;
}