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ArmPkg/ArmLib: Add ArmHasTrbe () helper function 

Create a helper function to query whether ID_AA64MFR1_EL1 indicates
presence of the Trace Buffer Extension (TRBE). This feature is only
visible in AARCH64 state.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
This commit is contained in:
Sami Mujawar 2023-09-22 15:35:15 +01:00 committed by mergify[bot]
parent 09fd4e4172
commit 08431081a3
3 changed files with 31 additions and 0 deletions
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3
ArmPkg/Include/Chipset/AArch64.h
View File

@ -31,6 +31,9 @@
#define AARCH64_PFR0_FP (0xF << 16) #define AARCH64_PFR0_FP (0xF << 16)
#define AARCH64_PFR0_GIC (0xF << 24) #define AARCH64_PFR0_GIC (0xF << 24)
// ID_AA64DFR0 - AArch64 Debug Feature Register 0 definitions
#define AARCH64_DFR0_TRBE (0xFULL << 44)
// SCR - Secure Configuration Register definitions // SCR - Secure Configuration Register definitions
#define SCR_NS (1 << 0) #define SCR_NS (1 << 0)
#define SCR_IRQ (1 << 1) #define SCR_IRQ (1 << 1)

13
ArmPkg/Include/Library/ArmLib.h
View File

@ -780,6 +780,19 @@ EFIAPI
ArmHasVhe ( ArmHasVhe (
VOID VOID
); );
/**
Checks whether the CPU implements the Trace Buffer Extension.
@retval TRUE FEAT_TRBE is implemented.
@retval FALSE FEAT_TRBE is not mplemented.
**/
BOOLEAN
EFIAPI
ArmHasTrbe (
VOID
);
#endif // MDE_CPU_AARCH64 #endif // MDE_CPU_AARCH64
#ifdef MDE_CPU_ARM #ifdef MDE_CPU_ARM

15
ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
View File

@ -119,3 +119,18 @@ ArmHasVhe (
{ {
return ((ArmReadIdAA64Mmfr1 () & AARCH64_MMFR1_VH) != 0); return ((ArmReadIdAA64Mmfr1 () & AARCH64_MMFR1_VH) != 0);
} }
/**
Checks whether the CPU implements the Trace Buffer Extension.
@retval TRUE FEAT_TRBE is implemented.
@retval FALSE FEAT_TRBE is not mplemented.
**/
BOOLEAN
EFIAPI
ArmHasTrbe (
VOID
)
{
return ((ArmReadIdAA64Dfr0 () & AARCH64_DFR0_TRBE) != 0);
}