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ArmPlatformPkg: Add PCD for SBSA Watchdog Count 

The Juno and FVP platform implement the SBSA Watchdog timers.
Added PcdWatchdogCount to specify the number of Watchdog timers
that are available.

This allows configurability and an option to disable the watchdog
timers if required for testing.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Sami Mujawar 2017-05-22 15:27:50 +01:00 committed by Leif Lindholm
parent baee8efb36
commit 08e94eee94
2 changed files with 4 additions and 3 deletions
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3
ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h
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@ -1,6 +1,6 @@
/** @file /** @file
* *
* Copyright (c) 2013-2014, ARM Limited. All rights reserved. * Copyright (c) 2013-2017, ARM Limited. All rights reserved.
* *
* This program and the accompanying materials * This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License * are licensed and made available under the terms and conditions of the BSD License
@ -108,7 +108,6 @@
JunoRevision = ARM_VE_BOARD_SYS_ID_REV( SysId ); \ JunoRevision = ARM_VE_BOARD_SYS_ID_REV( SysId ); \
} }
#define JUNO_WATCHDOG_COUNT 2
// Define if the exported ACPI Tables are based on ACPI 5.0 spec or latest // Define if the exported ACPI Tables are based on ACPI 5.0 spec or latest
//#define ARM_JUNO_ACPI_5_0 //#define ARM_JUNO_ACPI_5_0

4
ArmPlatformPkg/ArmPlatformPkg.dec
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@ -1,6 +1,6 @@
#/** @file #/** @file
# #
# Copyright (c) 2011-2016, ARM Limited. All rights reserved. # Copyright (c) 2011-2017, ARM Limited. All rights reserved.
# Copyright (c) 2015, Intel Corporation. All rights reserved. # Copyright (c) 2015, Intel Corporation. All rights reserved.
# #
# This program and the accompanying materials # This program and the accompanying materials
@ -131,6 +131,8 @@
gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024 gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022 gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
gArmPlatformTokenSpaceGuid.PcdWatchdogCount|0x0|UINT32|0x00000033
[PcdsFixedAtBuild.ARM] [PcdsFixedAtBuild.ARM]
# Stack for CPU Cores in Secure Monitor Mode # Stack for CPU Cores in Secure Monitor Mode
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007