mirror of https://github.com/acidanthera/audk.git
MdeModulePkg/Ufs: Refine EDKII_UFS_HOST_CONTROLLER_PROTOCOL interface
The EDKII_UFS_HOST_CONTROLLER_PROTOCOL is refined to provide interfaces accessing UFS host controller MMIO register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17533 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Feng Tian
erictian
parent
500e2ac246
commit
095f077993
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@ -2,7 +2,7 @@
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UfsHcDxe driver is used to provide platform-dependent info, mainly UFS host controller
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MMIO base, to upper layer UFS drivers.
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Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -39,9 +39,12 @@ UFS_HOST_CONTROLLER_PRIVATE_DATA gUfsHcTemplate = {
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UfsHcFreeBuffer,
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UfsHcMap,
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UfsHcUnmap,
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UfsHcFlush
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UfsHcFlush,
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UfsHcMmioRead,
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UfsHcMmioWrite
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},
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NULL, // PciIo
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0, // BarIndex
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0 // PciAttributes
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};
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@ -64,25 +67,32 @@ UfsHcGetMmioBar (
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UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT8 BarIndex;
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BarDesc;
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if ((This == NULL) || (MmioBar == NULL)) {
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return EFI_INVALID_PARAMETER;
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}
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Private = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);
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PciIo = Private->PciIo;
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BarDesc = NULL;
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Private = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);
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PciIo = Private->PciIo;
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BarIndex = Private->BarIndex;
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Status = PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint8,
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PCI_BASE_ADDRESSREG_OFFSET,
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sizeof (UINT32),
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MmioBar
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);
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if (!EFI_ERROR (Status)) {
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*MmioBar &= (UINTN)~0xF;
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Status = PciIo->GetBarAttributes (
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PciIo,
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BarIndex,
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NULL,
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(VOID**) &BarDesc
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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*MmioBar = (UINTN)BarDesc->AddrRangeMin;
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FreePool (BarDesc);
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return Status;
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}
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@ -272,6 +282,90 @@ UfsHcFlush (
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return Status;
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}
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/**
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Enable a UFS bus driver to access UFS MMIO registers in the UFS Host Controller memory space.
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@param This A pointer to the EDKII_UFS_HOST_CONTROLLER_PROTOCOL instance.
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@param Width Signifies the width of the memory operations.
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@param Offset The offset within the UFS Host Controller MMIO space to start the
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memory operation.
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@param Count The number of memory operations to perform.
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@param Buffer For read operations, the destination buffer to store the results.
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For write operations, the source buffer to write data from.
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@retval EFI_SUCCESS The data was read from or written to the UFS host controller.
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@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
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valid for the UFS Host Controller memory space.
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@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
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@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
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**/
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EFI_STATUS
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EFIAPI
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UfsHcMmioRead (
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IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
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IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL_WIDTH Width,
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IN UINT64 Offset,
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IN UINTN Count,
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IN OUT VOID *Buffer
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)
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{
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UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT8 BarIndex;
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Private = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);
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PciIo = Private->PciIo;
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BarIndex = Private->BarIndex;
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Status = PciIo->Mem.Read (PciIo, (EFI_PCI_IO_PROTOCOL_WIDTH)Width, BarIndex, Offset, Count, Buffer);
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return Status;
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}
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/**
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Enable a UFS bus driver to access UFS MMIO registers in the UFS Host Controller memory space.
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@param This A pointer to the EDKII_UFS_HOST_CONTROLLER_PROTOCOL instance.
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@param Width Signifies the width of the memory operations.
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@param Offset The offset within the UFS Host Controller MMIO space to start the
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memory operation.
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@param Count The number of memory operations to perform.
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@param Buffer For read operations, the destination buffer to store the results.
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For write operations, the source buffer to write data from.
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@retval EFI_SUCCESS The data was read from or written to the UFS host controller.
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@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
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valid for the UFS Host Controller memory space.
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@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
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@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
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**/
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EFI_STATUS
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EFIAPI
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UfsHcMmioWrite (
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IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
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IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL_WIDTH Width,
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IN UINT64 Offset,
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IN UINTN Count,
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IN OUT VOID *Buffer
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)
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{
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UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT8 BarIndex;
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Private = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);
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PciIo = Private->PciIo;
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BarIndex = Private->BarIndex;
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Status = PciIo->Mem.Write (PciIo, (EFI_PCI_IO_PROTOCOL_WIDTH)Width, BarIndex, Offset, Count, Buffer);
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return Status;
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}
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/**
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Tests to see if this driver supports a given controller. If a child device is provided,
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it further tests to see if this driver supports creating a handle for the specified child device.
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@ -468,10 +562,13 @@ UfsHcDriverBindingStart (
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EFI_PCI_IO_PROTOCOL *PciIo;
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UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;
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UINT64 Supports;
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UINT8 BarIndex;
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BarDesc;
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PciIo = NULL;
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Private = NULL;
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Supports = 0;
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BarDesc = NULL;
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//
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// Now test and open the EfiPciIoProtocol
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@ -507,6 +604,28 @@ UfsHcDriverBindingStart (
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Private->PciIo = PciIo;
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for (BarIndex = 0; BarIndex < PCI_MAX_BAR; BarIndex++) {
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Status = PciIo->GetBarAttributes (
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PciIo,
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BarIndex,
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NULL,
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(VOID**) &BarDesc
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);
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if (Status == EFI_UNSUPPORTED) {
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continue;
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} else if (EFI_ERROR (Status)) {
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goto Done;
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}
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if (BarDesc->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
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Private->BarIndex = BarIndex;
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FreePool (BarDesc);
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break;
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}
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FreePool (BarDesc);
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}
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Status = PciIo->Attributes (
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PciIo,
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EfiPciIoAttributeOperationGet,
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@ -2,7 +2,7 @@
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UfsHcDxe driver is used to provide platform-dependent info, mainly UFS host controller
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MMIO base, to upper layer UFS drivers.
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Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -19,6 +19,7 @@
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#include <Uefi.h>
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#include <IndustryStandard/Pci.h>
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#include <IndustryStandard/Acpi.h>
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#include <Protocol/ComponentName.h>
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#include <Protocol/ComponentName2.h>
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@ -56,6 +57,7 @@ struct _UFS_HOST_CONTROLLER_PRIVATE_DATA {
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EDKII_UFS_HOST_CONTROLLER_PROTOCOL UfsHc;
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EFI_PCI_IO_PROTOCOL *PciIo;
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UINT8 BarIndex;
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UINT64 PciAttributes;
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};
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@ -450,4 +452,60 @@ UfsHcFlush (
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IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This
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);
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/**
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Enable a UFS bus driver to access UFS MMIO registers in the UFS Host Controller memory space.
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@param This A pointer to the EDKII_UFS_HOST_CONTROLLER_PROTOCOL instance.
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@param Width Signifies the width of the memory operations.
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@param Offset The offset within the UFS Host Controller MMIO space to start the
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memory operation.
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@param Count The number of memory operations to perform.
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@param Buffer For read operations, the destination buffer to store the results.
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For write operations, the source buffer to write data from.
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@retval EFI_SUCCESS The data was read from or written to the UFS host controller.
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@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
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valid for the UFS Host Controller memory space.
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@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
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@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
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**/
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EFI_STATUS
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EFIAPI
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UfsHcMmioRead (
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IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
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IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL_WIDTH Width,
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IN UINT64 Offset,
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IN UINTN Count,
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IN OUT VOID *Buffer
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);
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/**
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Enable a UFS bus driver to access UFS MMIO registers in the UFS Host Controller memory space.
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@param This A pointer to the EDKII_UFS_HOST_CONTROLLER_PROTOCOL instance.
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@param Width Signifies the width of the memory operations.
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@param Offset The offset within the UFS Host Controller MMIO space to start the
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memory operation.
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@param Count The number of memory operations to perform.
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@param Buffer For read operations, the destination buffer to store the results.
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For write operations, the source buffer to write data from.
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@retval EFI_SUCCESS The data was read from or written to the UFS host controller.
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@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
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valid for the UFS Host Controller memory space.
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@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
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@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
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**/
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EFI_STATUS
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EFIAPI
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UfsHcMmioWrite (
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IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
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IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL_WIDTH Width,
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IN UINT64 Offset,
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IN UINTN Count,
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IN OUT VOID *Buffer
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);
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#endif
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@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -27,7 +27,6 @@
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#include <Library/MemoryAllocationLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/IoLib.h>
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#include <Library/TimerLib.h>
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#include "UfsPassThruHci.h"
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@ -52,7 +52,6 @@
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UefiDriverEntryPoint
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DebugLib
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DevicePathLib
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IoLib
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TimerLib
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[Protocols]
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@ -2,7 +2,7 @@
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UfsPassThruDxe driver is used to produce EFI_EXT_SCSI_PASS_THRU protocol interface
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for upper layer application to execute UFS-supported SCSI cmds.
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Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
|
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which accompanies this distribution. The full text of the license may be found at
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@ -16,29 +16,93 @@
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#include "UfsPassThru.h"
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/**
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Wait for the value of the specified system memory set to the test value.
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Read 32bits data from specified UFS MMIO register.
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@param Address The system memory address to test.
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@param MaskValue The mask value of memory.
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@param TestValue The test value of memory.
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@param Timeout The time out value for wait memory set, uses 100ns as a unit.
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@param[in] Private The pointer to the UFS_PASS_THRU_PRIVATE_DATA data structure.
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@param[in] Offset The offset within the UFS Host Controller MMIO space to start
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the memory operation.
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@param[out] Value The data buffer to store.
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@retval EFI_TIMEOUT The system memory setting is time out.
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@retval EFI_SUCCESS The system memory is correct set.
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@retval EFI_TIMEOUT The operation is time out.
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@retval EFI_SUCCESS The operation succeeds.
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@retval Others The operation fails.
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**/
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EFI_STATUS
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UfsMmioRead32 (
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IN UFS_PASS_THRU_PRIVATE_DATA *Private,
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IN UINTN Offset,
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OUT UINT32 *Value
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)
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{
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EDKII_UFS_HOST_CONTROLLER_PROTOCOL *UfsHc;
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EFI_STATUS Status;
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UfsHc = Private->UfsHostController;
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Status = UfsHc->Read (UfsHc, EfiUfsHcWidthUint32, Offset, 1, Value);
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return Status;
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}
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/**
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Write 32bits data to specified UFS MMIO register.
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@param[in] Private The pointer to the UFS_PASS_THRU_PRIVATE_DATA data structure.
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@param[in] Offset The offset within the UFS Host Controller MMIO space to start
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the memory operation.
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@param[in] Value The data to write.
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|
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@retval EFI_TIMEOUT The operation is time out.
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@retval EFI_SUCCESS The operation succeeds.
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@retval Others The operation fails.
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**/
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EFI_STATUS
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UfsMmioWrite32 (
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IN UFS_PASS_THRU_PRIVATE_DATA *Private,
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IN UINTN Offset,
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IN UINT32 Value
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)
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{
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EDKII_UFS_HOST_CONTROLLER_PROTOCOL *UfsHc;
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EFI_STATUS Status;
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UfsHc = Private->UfsHostController;
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Status = UfsHc->Write (UfsHc, EfiUfsHcWidthUint32, Offset, 1, &Value);
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return Status;
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}
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/**
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Wait for the value of the specified system memory set to the test value.
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@param[in] Private The pointer to the UFS_PASS_THRU_PRIVATE_DATA data structure.
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@param[in] Offset The offset within the UFS Host Controller MMIO space to start
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the memory operation.
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@param[in] MaskValue The mask value of memory.
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@param[in] TestValue The test value of memory.
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@param[in] Timeout The time out value for wait memory set, uses 100ns as a unit.
|
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|
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@retval EFI_TIMEOUT The system memory setting is time out.
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@retval EFI_SUCCESS The system memory is correct set.
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@retval Others The operation fails.
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**/
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EFI_STATUS
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EFIAPI
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UfsWaitMemSet (
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IN UINTN Address,
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IN UINT32 MaskValue,
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IN UINT32 TestValue,
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IN UINT64 Timeout
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IN UFS_PASS_THRU_PRIVATE_DATA *Private,
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IN UINTN Offset,
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IN UINT32 MaskValue,
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IN UINT32 TestValue,
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IN UINT64 Timeout
|
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)
|
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{
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UINT32 Value;
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UINT64 Delay;
|
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BOOLEAN InfiniteWait;
|
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EFI_STATUS Status;
|
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|
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if (Timeout == 0) {
|
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InfiniteWait = TRUE;
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|
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@ -52,7 +116,12 @@ UfsWaitMemSet (
|
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//
|
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// Access PCI MMIO space to see if the value is the tested one.
|
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//
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Value = MmioRead32 (Address) & MaskValue;
|
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Status = UfsMmioRead32 (Private, Offset, &Value);
|
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if (EFI_ERROR (Status)) {
|
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return Status;
|
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}
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Value &= MaskValue;
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|
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if (Value == TestValue) {
|
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return EFI_SUCCESS;
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|
|
@ -712,26 +781,33 @@ UfsFindAvailableSlotInTmrl (
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@param[in] Slot The slot to be started.
|
||||
|
||||
**/
|
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VOID
|
||||
EFI_STATUS
|
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UfsStartExecCmd (
|
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IN UFS_PASS_THRU_PRIVATE_DATA *Private,
|
||||
IN UINT8 Slot
|
||||
)
|
||||
{
|
||||
UINTN UfsHcBase;
|
||||
UINTN Address;
|
||||
UINT32 Data;
|
||||
EFI_STATUS Status;
|
||||
|
||||
UfsHcBase = Private->UfsHcBase;
|
||||
|
||||
Address = UfsHcBase + UFS_HC_UTRLRSR_OFFSET;
|
||||
Data = MmioRead32 (Address);
|
||||
if ((Data & UFS_HC_UTRLRSR) != UFS_HC_UTRLRSR) {
|
||||
MmioWrite32 (Address, UFS_HC_UTRLRSR);
|
||||
Status = UfsMmioRead32 (Private, UFS_HC_UTRLRSR_OFFSET, &Data);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
Address = UfsHcBase + UFS_HC_UTRLDBR_OFFSET;
|
||||
MmioWrite32 (Address, BIT0 << Slot);
|
||||
if ((Data & UFS_HC_UTRLRSR) != UFS_HC_UTRLRSR) {
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_UTRLRSR_OFFSET, UFS_HC_UTRLRSR);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
}
|
||||
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_UTRLDBR_OFFSET, BIT0 << Slot);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -741,25 +817,33 @@ UfsStartExecCmd (
|
|||
@param[in] Slot The slot to be stop.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFI_STATUS
|
||||
UfsStopExecCmd (
|
||||
IN UFS_PASS_THRU_PRIVATE_DATA *Private,
|
||||
IN UINT8 Slot
|
||||
)
|
||||
{
|
||||
UINTN UfsHcBase;
|
||||
UINTN Address;
|
||||
UINT32 Data;
|
||||
EFI_STATUS Status;
|
||||
|
||||
UfsHcBase = Private->UfsHcBase;
|
||||
|
||||
Address = UfsHcBase + UFS_HC_UTRLDBR_OFFSET;
|
||||
Data = MmioRead32 (Address);
|
||||
if ((Data & (BIT0 << Slot)) != 0) {
|
||||
Address = UfsHcBase + UFS_HC_UTRLCLR_OFFSET;
|
||||
Data = MmioRead32 (Address);
|
||||
MmioWrite32 (Address, (Data & ~(BIT0 << Slot)));
|
||||
Status = UfsMmioRead32 (Private, UFS_HC_UTRLDBR_OFFSET, &Data);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
if ((Data & (BIT0 << Slot)) != 0) {
|
||||
Status = UfsMmioRead32 (Private, UFS_HC_UTRLCLR_OFFSET, &Data);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_UTRLCLR_OFFSET, Data & ~(BIT0 << Slot));
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -793,7 +877,6 @@ UfsRwDeviceDesc (
|
|||
UFS_DEVICE_MANAGEMENT_REQUEST_PACKET Packet;
|
||||
UINT8 Slot;
|
||||
UTP_TRD *Trd;
|
||||
UINTN Address;
|
||||
UTP_QUERY_RESP_UPIU *QueryResp;
|
||||
UINT32 CmdDescSize;
|
||||
UINT16 ReturnDataSize;
|
||||
|
|
@ -852,8 +935,7 @@ UfsRwDeviceDesc (
|
|||
//
|
||||
// Wait for the completion of the transfer request.
|
||||
//
|
||||
Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET;
|
||||
Status = UfsWaitMemSet (Address, BIT0, 0, Packet.Timeout);
|
||||
Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0, 0, Packet.Timeout);
|
||||
if (EFI_ERROR (Status)) {
|
||||
goto Exit;
|
||||
}
|
||||
|
|
@ -922,7 +1004,6 @@ UfsRwAttributes (
|
|||
UFS_DEVICE_MANAGEMENT_REQUEST_PACKET Packet;
|
||||
UINT8 Slot;
|
||||
UTP_TRD *Trd;
|
||||
UINTN Address;
|
||||
UTP_QUERY_RESP_UPIU *QueryResp;
|
||||
UINT32 CmdDescSize;
|
||||
UINT32 ReturnData;
|
||||
|
|
@ -977,8 +1058,7 @@ UfsRwAttributes (
|
|||
//
|
||||
// Wait for the completion of the transfer request.
|
||||
//
|
||||
Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET;
|
||||
Status = UfsWaitMemSet (Address, BIT0, 0, Packet.Timeout);
|
||||
Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0, 0, Packet.Timeout);
|
||||
if (EFI_ERROR (Status)) {
|
||||
goto Exit;
|
||||
}
|
||||
|
|
@ -1038,7 +1118,6 @@ UfsRwFlags (
|
|||
UFS_DEVICE_MANAGEMENT_REQUEST_PACKET Packet;
|
||||
UINT8 Slot;
|
||||
UTP_TRD *Trd;
|
||||
UINTN Address;
|
||||
UTP_QUERY_RESP_UPIU *QueryResp;
|
||||
UINT32 CmdDescSize;
|
||||
VOID *CmdDescHost;
|
||||
|
|
@ -1103,8 +1182,7 @@ UfsRwFlags (
|
|||
//
|
||||
// Wait for the completion of the transfer request.
|
||||
//
|
||||
Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET;
|
||||
Status = UfsWaitMemSet (Address, BIT0, 0, Packet.Timeout);
|
||||
Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0, 0, Packet.Timeout);
|
||||
if (EFI_ERROR (Status)) {
|
||||
goto Exit;
|
||||
}
|
||||
|
|
@ -1237,7 +1315,6 @@ UfsExecNopCmds (
|
|||
UTP_TRD *Trd;
|
||||
UTP_NOP_IN_UPIU *NopInUpiu;
|
||||
UINT32 CmdDescSize;
|
||||
UINTN Address;
|
||||
VOID *CmdDescHost;
|
||||
VOID *CmdDescMapping;
|
||||
EDKII_UFS_HOST_CONTROLLER_PROTOCOL *UfsHc;
|
||||
|
|
@ -1272,8 +1349,7 @@ UfsExecNopCmds (
|
|||
//
|
||||
// Wait for the completion of the transfer request.
|
||||
//
|
||||
Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET;
|
||||
Status = UfsWaitMemSet (Address, BIT0, 0, UFS_TIMEOUT);
|
||||
Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0, 0, UFS_TIMEOUT);
|
||||
if (EFI_ERROR (Status)) {
|
||||
goto Exit;
|
||||
}
|
||||
|
|
@ -1328,7 +1404,6 @@ UfsExecScsiCmds (
|
|||
EFI_STATUS Status;
|
||||
UINT8 Slot;
|
||||
UTP_TRD *Trd;
|
||||
UINTN Address;
|
||||
UINT32 CmdDescSize;
|
||||
UTP_RESPONSE_UPIU *Response;
|
||||
UINT16 SenseDataLen;
|
||||
|
|
@ -1414,9 +1489,8 @@ UfsExecScsiCmds (
|
|||
|
||||
//
|
||||
// Wait for the completion of the transfer request.
|
||||
//
|
||||
Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET;
|
||||
Status = UfsWaitMemSet (Address, BIT0, 0, Packet->Timeout);
|
||||
//
|
||||
Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0, 0, Packet->Timeout);
|
||||
if (EFI_ERROR (Status)) {
|
||||
goto Exit;
|
||||
}
|
||||
|
|
@ -1506,18 +1580,21 @@ UfsExecUicCommands (
|
|||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINTN Address;
|
||||
UINT32 Data;
|
||||
UINTN UfsHcBase;
|
||||
|
||||
UfsHcBase = Private->UfsHcBase;
|
||||
Address = UfsHcBase + UFS_HC_IS_OFFSET;
|
||||
Data = MmioRead32 (Address);
|
||||
Status = UfsMmioRead32 (Private, UFS_HC_IS_OFFSET, &Data);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
if ((Data & UFS_HC_IS_UCCS) == UFS_HC_IS_UCCS) {
|
||||
//
|
||||
// Clear IS.BIT10 UIC Command Completion Status (UCCS) at first.
|
||||
//
|
||||
MmioWrite32 (Address, Data);
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_IS_OFFSET, Data);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
|
|
@ -1525,41 +1602,48 @@ UfsExecUicCommands (
|
|||
// only after all the UIC command argument registers (UICCMDARG1, UICCMDARG2 and UICCMDARG3)
|
||||
// are set.
|
||||
//
|
||||
Address = UfsHcBase + UFS_HC_UCMD_ARG1_OFFSET;
|
||||
MmioWrite32 (Address, Arg1);
|
||||
|
||||
Address = UfsHcBase + UFS_HC_UCMD_ARG2_OFFSET;
|
||||
MmioWrite32 (Address, Arg2);
|
||||
|
||||
Address = UfsHcBase + UFS_HC_UCMD_ARG3_OFFSET;
|
||||
MmioWrite32 (Address, Arg3);
|
||||
|
||||
//
|
||||
// Host software shall only set the UICCMD if HCS.UCRDY is set to 1.
|
||||
//
|
||||
Address = Private->UfsHcBase + UFS_HC_STATUS_OFFSET;
|
||||
Status = UfsWaitMemSet (Address, UFS_HC_HCS_UCRDY, UFS_HC_HCS_UCRDY, UFS_TIMEOUT);
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG1_OFFSET, Arg1);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
Address = UfsHcBase + UFS_HC_UIC_CMD_OFFSET;
|
||||
MmioWrite32 (Address, (UINT32)UicOpcode);
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG2_OFFSET, Arg2);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG3_OFFSET, Arg3);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
//
|
||||
// Host software shall only set the UICCMD if HCS.UCRDY is set to 1.
|
||||
//
|
||||
Status = UfsWaitMemSet (Private, UFS_HC_STATUS_OFFSET, UFS_HC_HCS_UCRDY, UFS_HC_HCS_UCRDY, UFS_TIMEOUT);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_UIC_CMD_OFFSET, (UINT32)UicOpcode);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
//
|
||||
// UFS 2.0 spec section 5.3.1 Offset:0x20 IS.Bit10 UIC Command Completion Status (UCCS)
|
||||
// This bit is set to '1' by the host controller upon completion of a UIC command.
|
||||
//
|
||||
Address = UfsHcBase + UFS_HC_IS_OFFSET;
|
||||
Data = MmioRead32 (Address);
|
||||
Status = UfsWaitMemSet (Address, UFS_HC_IS_UCCS, UFS_HC_IS_UCCS, UFS_TIMEOUT);
|
||||
Status = UfsWaitMemSet (Private, UFS_HC_IS_OFFSET, UFS_HC_IS_UCCS, UFS_HC_IS_UCCS, UFS_TIMEOUT);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
if (UicOpcode != UfsUicDmeReset) {
|
||||
Address = UfsHcBase + UFS_HC_UCMD_ARG2_OFFSET;
|
||||
Data = MmioRead32 (Address);
|
||||
Status = UfsMmioRead32 (Private, UFS_HC_UCMD_ARG2_OFFSET, &Data);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
if ((Data & 0xFF) != 0) {
|
||||
DEBUG_CODE_BEGIN();
|
||||
DumpUicCmdExecResult (UicOpcode, (UINT8)(Data & 0xFF));
|
||||
|
|
@ -1571,11 +1655,13 @@ UfsExecUicCommands (
|
|||
//
|
||||
// Check value of HCS.DP and make sure that there is a device attached to the Link.
|
||||
//
|
||||
Address = UfsHcBase + UFS_HC_STATUS_OFFSET;
|
||||
Data = MmioRead32 (Address);
|
||||
Status = UfsMmioRead32 (Private, UFS_HC_STATUS_OFFSET, &Data);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
if ((Data & UFS_HC_HCS_DP) == 0) {
|
||||
Address = UfsHcBase + UFS_HC_IS_OFFSET;
|
||||
Status = UfsWaitMemSet (Address, UFS_HC_IS_ULSS, UFS_HC_IS_ULSS, UFS_TIMEOUT);
|
||||
Status = UfsWaitMemSet (Private, UFS_HC_IS_OFFSET, UFS_HC_IS_ULSS, UFS_HC_IS_ULSS, UFS_TIMEOUT);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return EFI_DEVICE_ERROR;
|
||||
}
|
||||
|
|
@ -1694,7 +1780,6 @@ UfsEnableHostController (
|
|||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINTN Address;
|
||||
UINT32 Data;
|
||||
|
||||
//
|
||||
|
|
@ -1702,17 +1787,23 @@ UfsEnableHostController (
|
|||
//
|
||||
// Reinitialize the UFS host controller if HCE bit of HC register is set.
|
||||
//
|
||||
Address = Private->UfsHcBase + UFS_HC_ENABLE_OFFSET;
|
||||
Data = MmioRead32 (Address);
|
||||
Status = UfsMmioRead32 (Private, UFS_HC_ENABLE_OFFSET, &Data);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
if ((Data & UFS_HC_HCE_EN) == UFS_HC_HCE_EN) {
|
||||
//
|
||||
// Write a 0 to the HCE register at first to disable the host controller.
|
||||
//
|
||||
MmioWrite32 (Address, 0);
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_ENABLE_OFFSET, 0);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
//
|
||||
// Wait until HCE is read as '0' before continuing.
|
||||
//
|
||||
Status = UfsWaitMemSet (Address, UFS_HC_HCE_EN, 0, UFS_TIMEOUT);
|
||||
Status = UfsWaitMemSet (Private, UFS_HC_ENABLE_OFFSET, UFS_HC_HCE_EN, 0, UFS_TIMEOUT);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return EFI_DEVICE_ERROR;
|
||||
}
|
||||
|
|
@ -1721,11 +1812,15 @@ UfsEnableHostController (
|
|||
//
|
||||
// Write a 1 to the HCE register to enable the UFS host controller.
|
||||
//
|
||||
MmioWrite32 (Address, UFS_HC_HCE_EN);
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_ENABLE_OFFSET, UFS_HC_HCE_EN);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
//
|
||||
// Wait until HCE is read as '1' before continuing.
|
||||
//
|
||||
Status = UfsWaitMemSet (Address, UFS_HC_HCE_EN, UFS_HC_HCE_EN, UFS_TIMEOUT);
|
||||
Status = UfsWaitMemSet (Private, UFS_HC_ENABLE_OFFSET, UFS_HC_HCE_EN, UFS_HC_HCE_EN, UFS_TIMEOUT);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return EFI_DEVICE_ERROR;
|
||||
}
|
||||
|
|
@ -1789,7 +1884,6 @@ UfsInitTaskManagementRequestList (
|
|||
IN UFS_PASS_THRU_PRIVATE_DATA *Private
|
||||
)
|
||||
{
|
||||
UINTN Address;
|
||||
UINT32 Data;
|
||||
UINT8 Nutmrs;
|
||||
VOID *CmdDescHost;
|
||||
|
|
@ -1803,8 +1897,12 @@ UfsInitTaskManagementRequestList (
|
|||
CmdDescHost = NULL;
|
||||
CmdDescMapping = NULL;
|
||||
CmdDescPhyAddr = 0;
|
||||
Address = Private->UfsHcBase + UFS_HC_CAP_OFFSET;
|
||||
Data = MmioRead32 (Address);
|
||||
|
||||
Status = UfsMmioRead32 (Private, UFS_HC_CAP_OFFSET, &Data);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
Private->Capabilities = Data;
|
||||
|
||||
//
|
||||
|
|
@ -1820,10 +1918,15 @@ UfsInitTaskManagementRequestList (
|
|||
// Program the UTP Task Management Request List Base Address and UTP Task Management
|
||||
// Request List Base Address with a 64-bit address allocated at step 6.
|
||||
//
|
||||
Address = Private->UfsHcBase + UFS_HC_UTMRLBA_OFFSET;
|
||||
MmioWrite32 (Address, (UINT32)(UINTN)CmdDescPhyAddr);
|
||||
Address = Private->UfsHcBase + UFS_HC_UTMRLBAU_OFFSET;
|
||||
MmioWrite32 (Address, (UINT32)RShiftU64 ((UINT64)CmdDescPhyAddr, 32));
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_UTMRLBA_OFFSET, (UINT32)(UINTN)CmdDescPhyAddr);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_UTMRLBAU_OFFSET, (UINT32)RShiftU64 ((UINT64)CmdDescPhyAddr, 32));
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
Private->UtpTmrlBase = CmdDescHost;
|
||||
Private->Nutmrs = Nutmrs;
|
||||
Private->TmrlMapping = CmdDescMapping;
|
||||
|
|
@ -1832,8 +1935,10 @@ UfsInitTaskManagementRequestList (
|
|||
// Enable the UTP Task Management Request List by setting the UTP Task Management
|
||||
// Request List RunStop Register (UTMRLRSR) to '1'.
|
||||
//
|
||||
Address = Private->UfsHcBase + UFS_HC_UTMRLRSR_OFFSET;
|
||||
MmioWrite32 (Address, UFS_HC_UTMRLRSR);
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_UTMRLRSR_OFFSET, UFS_HC_UTMRLRSR);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
|
@ -1852,7 +1957,6 @@ UfsInitTransferRequestList (
|
|||
IN UFS_PASS_THRU_PRIVATE_DATA *Private
|
||||
)
|
||||
{
|
||||
UINTN Address;
|
||||
UINT32 Data;
|
||||
UINT8 Nutrs;
|
||||
VOID *CmdDescHost;
|
||||
|
|
@ -1866,8 +1970,12 @@ UfsInitTransferRequestList (
|
|||
CmdDescHost = NULL;
|
||||
CmdDescMapping = NULL;
|
||||
CmdDescPhyAddr = 0;
|
||||
Address = Private->UfsHcBase + UFS_HC_CAP_OFFSET;
|
||||
Data = MmioRead32 (Address);
|
||||
|
||||
Status = UfsMmioRead32 (Private, UFS_HC_CAP_OFFSET, &Data);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
Private->Capabilities = Data;
|
||||
|
||||
//
|
||||
|
|
@ -1883,10 +1991,16 @@ UfsInitTransferRequestList (
|
|||
// Program the UTP Transfer Request List Base Address and UTP Transfer Request List
|
||||
// Base Address with a 64-bit address allocated at step 8.
|
||||
//
|
||||
Address = Private->UfsHcBase + UFS_HC_UTRLBA_OFFSET;
|
||||
MmioWrite32 (Address, (UINT32)(UINTN)CmdDescPhyAddr);
|
||||
Address = Private->UfsHcBase + UFS_HC_UTRLBAU_OFFSET;
|
||||
MmioWrite32 (Address, (UINT32)RShiftU64 ((UINT64)CmdDescPhyAddr, 32));
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_UTRLBA_OFFSET, (UINT32)(UINTN)CmdDescPhyAddr);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_UTRLBAU_OFFSET, (UINT32)RShiftU64 ((UINT64)CmdDescPhyAddr, 32));
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
Private->UtpTrlBase = CmdDescHost;
|
||||
Private->Nutrs = Nutrs;
|
||||
Private->TrlMapping = CmdDescMapping;
|
||||
|
|
@ -1895,8 +2009,10 @@ UfsInitTransferRequestList (
|
|||
// Enable the UTP Transfer Request List by setting the UTP Transfer Request List
|
||||
// RunStop Register (UTRLRSR) to '1'.
|
||||
//
|
||||
Address = Private->UfsHcBase + UFS_HC_UTRLRSR_OFFSET;
|
||||
MmioWrite32 (Address, UFS_HC_UTRLRSR);
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_UTRLRSR_OFFSET, UFS_HC_UTRLRSR);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
|
@ -1960,35 +2076,44 @@ UfsControllerStop (
|
|||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINTN Address;
|
||||
UINT32 Data;
|
||||
|
||||
//
|
||||
// Enable the UTP Task Management Request List by setting the UTP Task Management
|
||||
// Request List RunStop Register (UTMRLRSR) to '1'.
|
||||
//
|
||||
Address = Private->UfsHcBase + UFS_HC_UTMRLRSR_OFFSET;
|
||||
MmioWrite32 (Address, 0);
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_UTMRLRSR_OFFSET, 0);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
//
|
||||
// Enable the UTP Transfer Request List by setting the UTP Transfer Request List
|
||||
// RunStop Register (UTRLRSR) to '1'.
|
||||
//
|
||||
Address = Private->UfsHcBase + UFS_HC_UTRLRSR_OFFSET;
|
||||
MmioWrite32 (Address, 0);
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_UTRLRSR_OFFSET, 0);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
//
|
||||
// Write a 0 to the HCE register in order to disable the host controller.
|
||||
//
|
||||
Address = Private->UfsHcBase + UFS_HC_ENABLE_OFFSET;
|
||||
Data = MmioRead32 (Address);
|
||||
Status = UfsMmioRead32 (Private, UFS_HC_ENABLE_OFFSET, &Data);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
ASSERT ((Data & UFS_HC_HCE_EN) == UFS_HC_HCE_EN);
|
||||
MmioWrite32 (Address, 0);
|
||||
|
||||
Status = UfsMmioWrite32 (Private, UFS_HC_ENABLE_OFFSET, 0);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
//
|
||||
// Wait until HCE is read as '0' before continuing.
|
||||
//
|
||||
Status = UfsWaitMemSet (Address, UFS_HC_HCE_EN, 0, UFS_TIMEOUT);
|
||||
Status = UfsWaitMemSet (Private, UFS_HC_ENABLE_OFFSET, UFS_HC_HCE_EN, 0, UFS_TIMEOUT);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return EFI_DEVICE_ERROR;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
EDKII Universal Flash Storage Host Controller Protocol.
|
||||
|
||||
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
|
|
@ -185,6 +185,42 @@ EFI_STATUS
|
|||
IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This
|
||||
);
|
||||
|
||||
typedef enum {
|
||||
EfiUfsHcWidthUint8 = 0,
|
||||
EfiUfsHcWidthUint16,
|
||||
EfiUfsHcWidthUint32,
|
||||
EfiUfsHcWidthUint64,
|
||||
EfiUfsHcWidthMaximum
|
||||
} EDKII_UFS_HOST_CONTROLLER_PROTOCOL_WIDTH;
|
||||
|
||||
/**
|
||||
Enable a UFS bus driver to access UFS MMIO registers in the UFS Host Controller memory space.
|
||||
|
||||
@param This A pointer to the EDKII_UFS_HOST_CONTROLLER_PROTOCOL instance.
|
||||
@param Width Signifies the width of the memory operations.
|
||||
@param Offset The offset within the UFS Host Controller MMIO space to start the
|
||||
memory operation.
|
||||
@param Count The number of memory operations to perform.
|
||||
@param Buffer For read operations, the destination buffer to store the results.
|
||||
For write operations, the source buffer to write data from.
|
||||
|
||||
@retval EFI_SUCCESS The data was read from or written to the UFS host controller.
|
||||
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
|
||||
valid for the UFS Host Controller memory space.
|
||||
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
|
||||
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
|
||||
|
||||
**/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EDKII_UFS_HC_MMIO_READ_WRITE)(
|
||||
IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
|
||||
IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 Offset,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
);
|
||||
|
||||
///
|
||||
/// UFS Host Controller Protocol structure.
|
||||
///
|
||||
|
|
@ -195,6 +231,8 @@ struct _EDKII_UFS_HOST_CONTROLLER_PROTOCOL {
|
|||
EDKII_UFS_HC_MAP Map;
|
||||
EDKII_UFS_HC_UNMAP Unmap;
|
||||
EDKII_UFS_HC_FLUSH Flush;
|
||||
EDKII_UFS_HC_MMIO_READ_WRITE Read;
|
||||
EDKII_UFS_HC_MMIO_READ_WRITE Write;
|
||||
};
|
||||
|
||||
///
|
||||
|
|
|
|||
Loading…
Reference in New Issue