mirror of https://github.com/acidanthera/audk.git
MdePkg/BaseLib: Add MemoryFence implementation for RiscV64
Cc: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Leif Lindholm <leif@nuviainc.com> Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
parent
c32c5911c4
commit
097aeeb119
|
@ -4,7 +4,7 @@
|
|||
# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>
|
||||
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
|
||||
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
|
||||
# Copyright (c) 2020 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
|
@ -401,6 +401,7 @@
|
|||
RiscV64/DisableInterrupts.c
|
||||
RiscV64/EnableInterrupts.c
|
||||
RiscV64/CpuPause.c
|
||||
RiscV64/MemoryFence.S | GCC
|
||||
RiscV64/RiscVSetJumpLongJump.S | GCC
|
||||
RiscV64/RiscVCpuBreakpoint.S | GCC
|
||||
RiscV64/RiscVCpuPause.S | GCC
|
||||
|
|
|
@ -0,0 +1,22 @@
|
|||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// MemoryFence() for RiscV64
|
||||
//
|
||||
// Copyright (c) 2021, Hewlett Packard Enterprise Development. All rights reserved.
|
||||
//
|
||||
// SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.p2align 2
|
||||
|
||||
ASM_GLOBAL ASM_PFX(MemoryFence)
|
||||
|
||||
//
|
||||
// Memory fence for RiscV64
|
||||
//
|
||||
//
|
||||
ASM_PFX(MemoryFence):
|
||||
fence // Fence on all memory and I/O
|
||||
ret
|
Loading…
Reference in New Issue