mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/CpuMpPei: support stack guard feature
This feature is the same as Stack Guard enabled in driver CpuDxe but applies to PEI phase. Due to the specialty in PEI module dispatching, this driver is changed to do the actual initialization in notify callback of event gEfiPeiMemoryDiscoveredPpiGuid. This can let the stack guard apply to as most PEI drivers as possible. To let Stack Guard work, some simple page table management code are introduced to setup Guard page at base of stack for each processor. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: "Ware, Ryan R" <ryan.r.ware@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
Jian J Wang
parent
e09b6b5953
commit
0a0d5296e4
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@ -408,6 +408,277 @@ PeiWhoAmI (
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return MpInitLibWhoAmI (ProcessorNumber);
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}
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/**
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Get GDT register value.
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This function is mainly for AP purpose because AP may have different GDT
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table than BSP.
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@param[in,out] Buffer The pointer to private data buffer.
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**/
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VOID
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EFIAPI
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GetGdtr (
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IN OUT VOID *Buffer
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)
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{
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AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer);
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}
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/**
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Initializes CPU exceptions handlers for the sake of stack switch requirement.
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This function is a wrapper of InitializeCpuExceptionHandlersEx. It's mainly
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for the sake of AP's init because of EFI_AP_PROCEDURE API requirement.
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@param[in,out] Buffer The pointer to private data buffer.
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**/
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VOID
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EFIAPI
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InitializeExceptionStackSwitchHandlers (
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IN OUT VOID *Buffer
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)
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{
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CPU_EXCEPTION_INIT_DATA *EssData;
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IA32_DESCRIPTOR Idtr;
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EFI_STATUS Status;
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EssData = Buffer;
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//
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// We don't plan to replace IDT table with a new one, but we should not assume
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// the AP's IDT is the same as BSP's IDT either.
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//
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AsmReadIdtr (&Idtr);
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EssData->Ia32.IdtTable = (VOID *)Idtr.Base;
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EssData->Ia32.IdtTableSize = Idtr.Limit + 1;
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Status = InitializeCpuExceptionHandlersEx (NULL, EssData);
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ASSERT_EFI_ERROR (Status);
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}
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/**
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Initializes MP exceptions handlers for the sake of stack switch requirement.
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This function will allocate required resources required to setup stack switch
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and pass them through CPU_EXCEPTION_INIT_DATA to each logic processor.
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**/
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VOID
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InitializeMpExceptionStackSwitchHandlers (
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VOID
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)
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{
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EFI_STATUS Status;
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UINTN Index;
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UINTN Bsp;
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UINTN ExceptionNumber;
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UINTN OldGdtSize;
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UINTN NewGdtSize;
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UINTN NewStackSize;
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IA32_DESCRIPTOR Gdtr;
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CPU_EXCEPTION_INIT_DATA EssData;
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UINT8 *GdtBuffer;
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UINT8 *StackTop;
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UINTN NumberOfProcessors;
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if (!PcdGetBool (PcdCpuStackGuard)) {
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return;
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}
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MpInitLibGetNumberOfProcessors(&NumberOfProcessors, NULL);
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MpInitLibWhoAmI (&Bsp);
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ExceptionNumber = FixedPcdGetSize (PcdCpuStackSwitchExceptionList);
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NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber;
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Status = PeiServicesAllocatePool (
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NewStackSize * NumberOfProcessors,
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(VOID **)&StackTop
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);
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ASSERT(StackTop != NULL);
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if (EFI_ERROR (Status)) {
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ASSERT_EFI_ERROR (Status);
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return;
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}
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StackTop += NewStackSize * NumberOfProcessors;
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//
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// The default exception handlers must have been initialized. Let's just skip
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// it in this method.
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//
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EssData.Ia32.Revision = CPU_EXCEPTION_INIT_DATA_REV;
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EssData.Ia32.InitDefaultHandlers = FALSE;
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EssData.Ia32.StackSwitchExceptions = FixedPcdGetPtr(PcdCpuStackSwitchExceptionList);
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EssData.Ia32.StackSwitchExceptionNumber = ExceptionNumber;
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EssData.Ia32.KnownGoodStackSize = FixedPcdGet32(PcdCpuKnownGoodStackSize);
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//
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// Initialize Gdtr to suppress incorrect compiler/analyzer warnings.
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//
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Gdtr.Base = 0;
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Gdtr.Limit = 0;
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for (Index = 0; Index < NumberOfProcessors; ++Index) {
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//
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// To support stack switch, we need to re-construct GDT but not IDT.
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//
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if (Index == Bsp) {
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GetGdtr(&Gdtr);
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} else {
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//
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// AP might have different size of GDT from BSP.
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//
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MpInitLibStartupThisAP (GetGdtr, Index, NULL, 0, (VOID *)&Gdtr, NULL);
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}
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//
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// X64 needs only one TSS of current task working for all exceptions
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// because of its IST feature. IA32 needs one TSS for each exception
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// in addition to current task. Since AP is not supposed to allocate
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// memory, we have to do it in BSP. To simplify the code, we allocate
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// memory for IA32 case to cover both IA32 and X64 exception stack
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// switch.
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//
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// Layout of memory to allocate for each processor:
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// --------------------------------
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// | Alignment | (just in case)
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// --------------------------------
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// | |
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// | Original GDT |
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// | |
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// --------------------------------
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// | Current task descriptor |
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// --------------------------------
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// | |
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// | Exception task descriptors | X ExceptionNumber
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// | |
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// --------------------------------
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// | Current task-state segment |
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// --------------------------------
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// | |
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// | Exception task-state segment | X ExceptionNumber
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// | |
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// --------------------------------
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//
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OldGdtSize = Gdtr.Limit + 1;
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EssData.Ia32.ExceptionTssDescSize = sizeof (IA32_TSS_DESCRIPTOR) *
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(ExceptionNumber + 1);
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EssData.Ia32.ExceptionTssSize = sizeof (IA32_TASK_STATE_SEGMENT) *
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(ExceptionNumber + 1);
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NewGdtSize = sizeof (IA32_TSS_DESCRIPTOR) +
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OldGdtSize +
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EssData.Ia32.ExceptionTssDescSize +
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EssData.Ia32.ExceptionTssSize;
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Status = PeiServicesAllocatePool (
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NewGdtSize,
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(VOID **)&GdtBuffer
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);
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ASSERT (GdtBuffer != NULL);
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if (EFI_ERROR (Status)) {
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ASSERT_EFI_ERROR (Status);
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return;
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}
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//
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// Make sure GDT table alignment
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//
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EssData.Ia32.GdtTable = ALIGN_POINTER(GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR));
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NewGdtSize -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer);
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EssData.Ia32.GdtTableSize = NewGdtSize;
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EssData.Ia32.ExceptionTssDesc = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize);
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EssData.Ia32.ExceptionTss = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize +
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EssData.Ia32.ExceptionTssDescSize);
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EssData.Ia32.KnownGoodStackTop = (UINTN)StackTop;
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DEBUG ((DEBUG_INFO,
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"Exception stack top[cpu%lu]: 0x%lX\n",
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(UINT64)(UINTN)Index,
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(UINT64)(UINTN)StackTop));
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if (Index == Bsp) {
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InitializeExceptionStackSwitchHandlers (&EssData);
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} else {
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MpInitLibStartupThisAP (
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InitializeExceptionStackSwitchHandlers,
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Index,
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NULL,
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0,
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(VOID *)&EssData,
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NULL
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);
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}
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StackTop -= NewStackSize;
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}
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}
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/**
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Initializes MP and exceptions handlers.
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@param PeiServices The pointer to the PEI Services Table.
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@retval EFI_SUCCESS MP was successfully initialized.
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@retval others Error occurred in MP initialization.
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**/
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EFI_STATUS
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InitializeCpuMpWorker (
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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EFI_STATUS Status;
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EFI_VECTOR_HANDOFF_INFO *VectorInfo;
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EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi;
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//
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// Get Vector Hand-off Info PPI
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//
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VectorInfo = NULL;
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Status = PeiServicesLocatePpi (
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&gEfiVectorHandoffInfoPpiGuid,
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0,
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NULL,
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(VOID **)&VectorHandoffInfoPpi
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);
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if (Status == EFI_SUCCESS) {
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VectorInfo = VectorHandoffInfoPpi->Info;
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}
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//
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// Initialize default handlers
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//
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Status = InitializeCpuExceptionHandlers (VectorInfo);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = MpInitLibInitialize ();
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if (EFI_ERROR (Status)) {
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return Status;
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}
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//
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// Special initialization for the sake of Stack Guard
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//
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InitializeMpExceptionStackSwitchHandlers ();
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//
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// Update and publish CPU BIST information
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//
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CollectBistDataFromPpi (PeiServices);
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//
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// Install CPU MP PPI
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//
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Status = PeiServicesInstallPpi(&mPeiCpuMpPpiDesc);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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/**
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The Entry point of the MP CPU PEIM.
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@ -428,40 +699,12 @@ CpuMpPeimInit (
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)
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{
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EFI_STATUS Status;
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EFI_VECTOR_HANDOFF_INFO *VectorInfo;
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EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi;
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//
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// Get Vector Hand-off Info PPI
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// For the sake of special initialization needing to be done right after
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// memory discovery.
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//
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VectorInfo = NULL;
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Status = PeiServicesLocatePpi (
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&gEfiVectorHandoffInfoPpiGuid,
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0,
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NULL,
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(VOID **)&VectorHandoffInfoPpi
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);
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if (Status == EFI_SUCCESS) {
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VectorInfo = VectorHandoffInfoPpi->Info;
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}
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Status = InitializeCpuExceptionHandlers (VectorInfo);
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ASSERT_EFI_ERROR (Status);
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//
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// Wakeup APs to do initialization
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//
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Status = MpInitLibInitialize ();
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ASSERT_EFI_ERROR (Status);
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//
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// Update and publish CPU BIST information
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//
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CollectBistDataFromPpi (PeiServices);
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//
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// Install CPU MP PPI
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//
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Status = PeiServicesInstallPpi(&mPeiCpuMpPpiDesc);
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Status = PeiServicesNotifyPpi (&mPostMemNotifyList[0]);
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ASSERT_EFI_ERROR (Status);
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return Status;
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@ -1,7 +1,7 @@
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/** @file
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Definitions to install Multiple Processor PPI.
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Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -402,4 +402,41 @@ SecPlatformInformation2 (
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OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2
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);
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/**
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Initializes MP and exceptions handlers.
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@param PeiServices The pointer to the PEI Services Table.
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@retval EFI_SUCCESS MP was successfully initialized.
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@retval others Error occurred in MP initialization.
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**/
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EFI_STATUS
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InitializeCpuMpWorker (
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IN CONST EFI_PEI_SERVICES **PeiServices
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);
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/**
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Enabl/setup stack guard for each processor if PcdCpuStackGuard is set to TRUE.
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Doing this in the memory-discovered callback is to make sure the Stack Guard
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feature to cover as most PEI code as possible.
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@param[in] PeiServices General purpose services available to every PEIM.
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@param[in] NotifyDescriptor The notification structure this PEIM registered on install.
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@param[in] Ppi The memory discovered PPI. Not used.
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@retval EFI_SUCCESS The function completed successfully.
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@retval others There's error in MP initialization.
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**/
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EFI_STATUS
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EFIAPI
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MemoryDiscoveredPpiNotifyCallback (
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IN EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
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IN VOID *Ppi
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);
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extern EFI_PEI_NOTIFY_DESCRIPTOR mPostMemNotifyList[];
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#endif
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@ -1,7 +1,7 @@
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## @file
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# CPU driver installs CPU PI Multi-processor PPI.
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#
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# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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@ -31,6 +31,7 @@
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CpuMpPei.h
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CpuMpPei.c
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CpuBist.c
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CpuPaging.c
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[Packages]
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MdePkg/MdePkg.dec
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@ -57,9 +58,17 @@
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## UNDEFINED # HOB
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gEfiSecPlatformInformation2PpiGuid
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gEfiVectorHandoffInfoPpiGuid ## SOMETIMES_CONSUMES
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gEfiPeiMemoryDiscoveredPpiGuid ## CONSUMES
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[Pcd]
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gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ## CONSUMES
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gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONSUMES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList ## SOMETIMES_CONSUMES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize ## SOMETIMES_CONSUMES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize ## SOMETIMES_CONSUMES
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[Depex]
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gEfiPeiMemoryDiscoveredPpiGuid
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TRUE
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[UserExtensions.TianoCore."ExtraFiles"]
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CpuMpPeiExtra.uni
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|
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@ -0,0 +1,631 @@
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/** @file
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Basic paging support for the CPU to enable Stack Guard.
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Register/Cpuid.h>
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#include <Register/Msr.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/CpuLib.h>
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#include <Library/BaseLib.h>
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#include "CpuMpPei.h"
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#define IA32_PG_P BIT0
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#define IA32_PG_RW BIT1
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#define IA32_PG_U BIT2
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#define IA32_PG_A BIT5
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#define IA32_PG_D BIT6
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#define IA32_PG_PS BIT7
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#define IA32_PG_NX BIT63
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#define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P)
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#define PAGE_PROGATE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_NX | IA32_PG_U |\
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PAGE_ATTRIBUTE_BITS)
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#define PAGING_PAE_INDEX_MASK 0x1FF
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#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
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#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
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#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
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#define PAGING_512G_ADDRESS_MASK_64 0x000FFF8000000000ull
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typedef enum {
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PageNone = 0,
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PageMin = 1,
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Page4K = PageMin,
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Page2M = 2,
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Page1G = 3,
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Page512G = 4,
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PageMax = Page512G
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} PAGE_ATTRIBUTE;
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typedef struct {
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PAGE_ATTRIBUTE Attribute;
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UINT64 Length;
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UINT64 AddressMask;
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UINTN AddressBitOffset;
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UINTN AddressBitLength;
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} PAGE_ATTRIBUTE_TABLE;
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PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
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{PageNone, 0, 0, 0, 0},
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{Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64, 12, 9},
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{Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64, 21, 9},
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{Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64, 30, 9},
|
||||
{Page512G, SIZE_512GB, PAGING_512G_ADDRESS_MASK_64, 39, 9},
|
||||
};
|
||||
|
||||
EFI_PEI_NOTIFY_DESCRIPTOR mPostMemNotifyList[] = {
|
||||
{
|
||||
(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
|
||||
&gEfiPeiMemoryDiscoveredPpiGuid,
|
||||
MemoryDiscoveredPpiNotifyCallback
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
The function will check if IA32 PAE is supported.
|
||||
|
||||
@retval TRUE IA32 PAE is supported.
|
||||
@retval FALSE IA32 PAE is not supported.
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
IsIa32PaeSupported (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 RegEax;
|
||||
CPUID_VERSION_INFO_EDX RegEdx;
|
||||
|
||||
AsmCpuid (CPUID_SIGNATURE, &RegEax, NULL, NULL, NULL);
|
||||
if (RegEax >= CPUID_VERSION_INFO) {
|
||||
AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx.Uint32);
|
||||
if (RegEdx.Bits.PAE != 0) {
|
||||
return TRUE;
|
||||
}
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/**
|
||||
This API provides a way to allocate memory for page table.
|
||||
|
||||
@param Pages The number of 4 KB pages to allocate.
|
||||
|
||||
@return A pointer to the allocated buffer or NULL if allocation fails.
|
||||
|
||||
**/
|
||||
VOID *
|
||||
AllocatePageTableMemory (
|
||||
IN UINTN Pages
|
||||
)
|
||||
{
|
||||
VOID *Address;
|
||||
|
||||
Address = AllocatePages(Pages);
|
||||
if (Address != NULL) {
|
||||
ZeroMem(Address, EFI_PAGES_TO_SIZE (Pages));
|
||||
}
|
||||
|
||||
return Address;
|
||||
}
|
||||
|
||||
/**
|
||||
Get the address width supported by current processor.
|
||||
|
||||
@retval 32 If processor is in 32-bit mode.
|
||||
@retval 36-48 If processor is in 64-bit mode.
|
||||
|
||||
**/
|
||||
UINTN
|
||||
GetPhysicalAddressWidth (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 RegEax;
|
||||
|
||||
if (sizeof(UINTN) == 4) {
|
||||
return 32;
|
||||
}
|
||||
|
||||
AsmCpuid(CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
|
||||
if (RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) {
|
||||
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &RegEax, NULL, NULL, NULL);
|
||||
RegEax &= 0xFF;
|
||||
if (RegEax > 48) {
|
||||
return 48;
|
||||
}
|
||||
|
||||
return (UINTN)RegEax;
|
||||
}
|
||||
|
||||
return 36;
|
||||
}
|
||||
|
||||
/**
|
||||
Get the type of top level page table.
|
||||
|
||||
@retval Page512G PML4 paging.
|
||||
@retval Page1G PAE paing.
|
||||
|
||||
**/
|
||||
PAGE_ATTRIBUTE
|
||||
GetPageTableTopLevelType (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
MSR_IA32_EFER_REGISTER MsrEfer;
|
||||
|
||||
MsrEfer.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
|
||||
|
||||
return (MsrEfer.Bits.LMA == 1) ? Page512G : Page1G;
|
||||
}
|
||||
|
||||
/**
|
||||
Return page table entry matching the address.
|
||||
|
||||
@param[in] Address The address to be checked.
|
||||
@param[out] PageAttributes The page attribute of the page entry.
|
||||
|
||||
@return The page entry.
|
||||
**/
|
||||
VOID *
|
||||
GetPageTableEntry (
|
||||
IN PHYSICAL_ADDRESS Address,
|
||||
OUT PAGE_ATTRIBUTE *PageAttribute
|
||||
)
|
||||
{
|
||||
INTN Level;
|
||||
UINTN Index;
|
||||
UINT64 *PageTable;
|
||||
UINT64 AddressEncMask;
|
||||
|
||||
AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask);
|
||||
PageTable = (UINT64 *)(UINTN)(AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);
|
||||
for (Level = (INTN)GetPageTableTopLevelType (); Level > 0; --Level) {
|
||||
Index = (UINTN)RShiftU64 (Address, mPageAttributeTable[Level].AddressBitOffset);
|
||||
Index &= PAGING_PAE_INDEX_MASK;
|
||||
|
||||
//
|
||||
// No mapping?
|
||||
//
|
||||
if (PageTable[Index] == 0) {
|
||||
*PageAttribute = PageNone;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
//
|
||||
// Page memory?
|
||||
//
|
||||
if ((PageTable[Index] & IA32_PG_PS) != 0 || Level == PageMin) {
|
||||
*PageAttribute = (PAGE_ATTRIBUTE)Level;
|
||||
return &PageTable[Index];
|
||||
}
|
||||
|
||||
//
|
||||
// Page directory or table
|
||||
//
|
||||
PageTable = (UINT64 *)(UINTN)(PageTable[Index] &
|
||||
~AddressEncMask &
|
||||
PAGING_4K_ADDRESS_MASK_64);
|
||||
}
|
||||
|
||||
*PageAttribute = PageNone;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
This function splits one page entry to smaller page entries.
|
||||
|
||||
@param[in] PageEntry The page entry to be splitted.
|
||||
@param[in] PageAttribute The page attribute of the page entry.
|
||||
@param[in] SplitAttribute How to split the page entry.
|
||||
@param[in] Recursively Do the split recursively or not.
|
||||
|
||||
@retval RETURN_SUCCESS The page entry is splitted.
|
||||
@retval RETURN_INVALID_PARAMETER If target page attribute is invalid
|
||||
@retval RETURN_OUT_OF_RESOURCES No resource to split page entry.
|
||||
**/
|
||||
RETURN_STATUS
|
||||
SplitPage (
|
||||
IN UINT64 *PageEntry,
|
||||
IN PAGE_ATTRIBUTE PageAttribute,
|
||||
IN PAGE_ATTRIBUTE SplitAttribute,
|
||||
IN BOOLEAN Recursively
|
||||
)
|
||||
{
|
||||
UINT64 BaseAddress;
|
||||
UINT64 *NewPageEntry;
|
||||
UINTN Index;
|
||||
UINT64 AddressEncMask;
|
||||
PAGE_ATTRIBUTE SplitTo;
|
||||
|
||||
if (SplitAttribute == PageNone || SplitAttribute >= PageAttribute) {
|
||||
ASSERT (SplitAttribute != PageNone);
|
||||
ASSERT (SplitAttribute < PageAttribute);
|
||||
return RETURN_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
NewPageEntry = AllocatePageTableMemory (1);
|
||||
if (NewPageEntry == NULL) {
|
||||
ASSERT (NewPageEntry != NULL);
|
||||
return RETURN_OUT_OF_RESOURCES;
|
||||
}
|
||||
|
||||
//
|
||||
// One level down each step to achieve more compact page table.
|
||||
//
|
||||
SplitTo = PageAttribute - 1;
|
||||
AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &
|
||||
mPageAttributeTable[SplitTo].AddressMask;
|
||||
BaseAddress = *PageEntry &
|
||||
~PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &
|
||||
mPageAttributeTable[PageAttribute].AddressMask;
|
||||
for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {
|
||||
NewPageEntry[Index] = BaseAddress | AddressEncMask |
|
||||
((*PageEntry) & PAGE_PROGATE_BITS);
|
||||
|
||||
if (SplitTo != PageMin) {
|
||||
NewPageEntry[Index] |= IA32_PG_PS;
|
||||
}
|
||||
|
||||
if (Recursively && SplitTo > SplitAttribute) {
|
||||
SplitPage (&NewPageEntry[Index], SplitTo, SplitAttribute, Recursively);
|
||||
}
|
||||
|
||||
BaseAddress += mPageAttributeTable[SplitTo].Length;
|
||||
}
|
||||
|
||||
(*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | PAGE_ATTRIBUTE_BITS;
|
||||
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
This function modifies the page attributes for the memory region specified
|
||||
by BaseAddress and Length from their current attributes to the attributes
|
||||
specified by Attributes.
|
||||
|
||||
Caller should make sure BaseAddress and Length is at page boundary.
|
||||
|
||||
@param[in] BaseAddress Start address of a memory region.
|
||||
@param[in] Length Size in bytes of the memory region.
|
||||
@param[in] Attributes Bit mask of attributes to modify.
|
||||
|
||||
@retval RETURN_SUCCESS The attributes were modified for the memory
|
||||
region.
|
||||
@retval RETURN_INVALID_PARAMETER Length is zero; or,
|
||||
Attributes specified an illegal combination
|
||||
of attributes that cannot be set together; or
|
||||
Addressis not 4KB aligned.
|
||||
@retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify
|
||||
the attributes.
|
||||
@retval RETURN_UNSUPPORTED Cannot modify the attributes of given memory.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
EFIAPI
|
||||
ConvertMemoryPageAttributes (
|
||||
IN PHYSICAL_ADDRESS BaseAddress,
|
||||
IN UINT64 Length,
|
||||
IN UINT64 Attributes
|
||||
)
|
||||
{
|
||||
UINT64 *PageEntry;
|
||||
PAGE_ATTRIBUTE PageAttribute;
|
||||
RETURN_STATUS Status;
|
||||
EFI_PHYSICAL_ADDRESS MaximumAddress;
|
||||
|
||||
if (Length == 0 ||
|
||||
(BaseAddress & (SIZE_4KB - 1)) != 0 ||
|
||||
(Length & (SIZE_4KB - 1)) != 0) {
|
||||
|
||||
ASSERT (Length > 0);
|
||||
ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
|
||||
ASSERT ((Length & (SIZE_4KB - 1)) == 0);
|
||||
|
||||
return RETURN_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
MaximumAddress = (EFI_PHYSICAL_ADDRESS)MAX_UINT32;
|
||||
if (BaseAddress > MaximumAddress ||
|
||||
Length > MaximumAddress ||
|
||||
(BaseAddress > MaximumAddress - (Length - 1))) {
|
||||
return RETURN_UNSUPPORTED;
|
||||
}
|
||||
|
||||
//
|
||||
// Below logic is to check 2M/4K page to make sure we do not waste memory.
|
||||
//
|
||||
while (Length != 0) {
|
||||
PageEntry = GetPageTableEntry (BaseAddress, &PageAttribute);
|
||||
if (PageEntry == NULL) {
|
||||
return RETURN_UNSUPPORTED;
|
||||
}
|
||||
|
||||
if (PageAttribute != Page4K) {
|
||||
Status = SplitPage (PageEntry, PageAttribute, Page4K, FALSE);
|
||||
if (RETURN_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
//
|
||||
// Do it again until the page is 4K.
|
||||
//
|
||||
continue;
|
||||
}
|
||||
|
||||
//
|
||||
// Just take care of 'present' bit for Stack Guard.
|
||||
//
|
||||
if ((Attributes & IA32_PG_P) != 0) {
|
||||
*PageEntry |= (UINT64)IA32_PG_P;
|
||||
} else {
|
||||
*PageEntry &= ~((UINT64)IA32_PG_P);
|
||||
}
|
||||
|
||||
//
|
||||
// Convert success, move to next
|
||||
//
|
||||
BaseAddress += SIZE_4KB;
|
||||
Length -= SIZE_4KB;
|
||||
}
|
||||
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Get maximum size of page memory supported by current processor.
|
||||
|
||||
@param[in] TopLevelType The type of top level page entry.
|
||||
|
||||
@retval Page1G If processor supports 1G page and PML4.
|
||||
@retval Page2M For all other situations.
|
||||
|
||||
**/
|
||||
PAGE_ATTRIBUTE
|
||||
GetMaxMemoryPage (
|
||||
IN PAGE_ATTRIBUTE TopLevelType
|
||||
)
|
||||
{
|
||||
UINT32 RegEax;
|
||||
UINT32 RegEdx;
|
||||
|
||||
if (TopLevelType == Page512G) {
|
||||
AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
|
||||
if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
|
||||
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
|
||||
if ((RegEdx & BIT26) != 0) {
|
||||
return Page1G;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return Page2M;
|
||||
}
|
||||
|
||||
/**
|
||||
Create PML4 or PAE page table.
|
||||
|
||||
@return The address of page table.
|
||||
|
||||
**/
|
||||
UINTN
|
||||
CreatePageTable (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
RETURN_STATUS Status;
|
||||
UINTN PhysicalAddressBits;
|
||||
UINTN NumberOfEntries;
|
||||
PAGE_ATTRIBUTE TopLevelPageAttr;
|
||||
UINTN PageTable;
|
||||
PAGE_ATTRIBUTE MaxMemoryPage;
|
||||
UINTN Index;
|
||||
UINT64 AddressEncMask;
|
||||
UINT64 *PageEntry;
|
||||
EFI_PHYSICAL_ADDRESS PhysicalAddress;
|
||||
|
||||
TopLevelPageAttr = (PAGE_ATTRIBUTE)GetPageTableTopLevelType ();
|
||||
PhysicalAddressBits = GetPhysicalAddressWidth ();
|
||||
NumberOfEntries = (UINTN)1 << (PhysicalAddressBits -
|
||||
mPageAttributeTable[TopLevelPageAttr].AddressBitOffset);
|
||||
|
||||
PageTable = (UINTN) AllocatePageTableMemory (1);
|
||||
if (PageTable == 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask);
|
||||
AddressEncMask &= mPageAttributeTable[TopLevelPageAttr].AddressMask;
|
||||
MaxMemoryPage = GetMaxMemoryPage (TopLevelPageAttr);
|
||||
PageEntry = (UINT64 *)PageTable;
|
||||
|
||||
PhysicalAddress = 0;
|
||||
for (Index = 0; Index < NumberOfEntries; ++Index) {
|
||||
*PageEntry = PhysicalAddress | AddressEncMask | PAGE_ATTRIBUTE_BITS;
|
||||
|
||||
//
|
||||
// Split the top page table down to the maximum page size supported
|
||||
//
|
||||
if (MaxMemoryPage < TopLevelPageAttr) {
|
||||
Status = SplitPage(PageEntry, TopLevelPageAttr, MaxMemoryPage, TRUE);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
}
|
||||
|
||||
if (TopLevelPageAttr == Page1G) {
|
||||
//
|
||||
// PDPTE[2:1] (PAE Paging) must be 0. SplitPage() might change them to 1.
|
||||
//
|
||||
*PageEntry &= ~(UINT64)(IA32_PG_RW | IA32_PG_U);
|
||||
}
|
||||
|
||||
PageEntry += 1;
|
||||
PhysicalAddress += mPageAttributeTable[TopLevelPageAttr].Length;
|
||||
}
|
||||
|
||||
|
||||
return PageTable;
|
||||
}
|
||||
|
||||
/**
|
||||
Setup page tables and make them work.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EnablePaging (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN PageTable;
|
||||
|
||||
PageTable = CreatePageTable ();
|
||||
ASSERT (PageTable != 0);
|
||||
if (PageTable != 0) {
|
||||
AsmWriteCr3(PageTable);
|
||||
AsmWriteCr4 (AsmReadCr4 () | BIT5); // CR4.PAE
|
||||
AsmWriteCr0 (AsmReadCr0 () | BIT31); // CR0.PG
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
Get the base address of current AP's stack.
|
||||
|
||||
This function is called in AP's context and assumes that whole calling stacks
|
||||
(till this function) consumed by AP's wakeup procedure will not exceed 4KB.
|
||||
|
||||
PcdCpuApStackSize must be configured with value taking the Guard page into
|
||||
account.
|
||||
|
||||
@param[in,out] Buffer The pointer to private data buffer.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
GetStackBase (
|
||||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
EFI_PHYSICAL_ADDRESS StackBase;
|
||||
|
||||
StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)&StackBase;
|
||||
StackBase += BASE_4KB;
|
||||
StackBase &= ~((EFI_PHYSICAL_ADDRESS)BASE_4KB - 1);
|
||||
StackBase -= PcdGet32(PcdCpuApStackSize);
|
||||
|
||||
*(EFI_PHYSICAL_ADDRESS *)Buffer = StackBase;
|
||||
}
|
||||
|
||||
/**
|
||||
Setup stack Guard page at the stack base of each processor. BSP and APs have
|
||||
different way to get stack base address.
|
||||
|
||||
**/
|
||||
VOID
|
||||
SetupStackGuardPage (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
EFI_PEI_HOB_POINTERS Hob;
|
||||
EFI_PHYSICAL_ADDRESS StackBase;
|
||||
UINTN NumberOfProcessors;
|
||||
UINTN Bsp;
|
||||
UINTN Index;
|
||||
|
||||
//
|
||||
// One extra page at the bottom of the stack is needed for Guard page.
|
||||
//
|
||||
if (PcdGet32(PcdCpuApStackSize) <= EFI_PAGE_SIZE) {
|
||||
DEBUG ((DEBUG_ERROR, "PcdCpuApStackSize is not big enough for Stack Guard!\n"));
|
||||
ASSERT (FALSE);
|
||||
}
|
||||
|
||||
MpInitLibGetNumberOfProcessors(&NumberOfProcessors, NULL);
|
||||
MpInitLibWhoAmI (&Bsp);
|
||||
for (Index = 0; Index < NumberOfProcessors; ++Index) {
|
||||
if (Index == Bsp) {
|
||||
Hob.Raw = GetHobList ();
|
||||
while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, Hob.Raw)) != NULL) {
|
||||
if (CompareGuid (&gEfiHobMemoryAllocStackGuid,
|
||||
&(Hob.MemoryAllocationStack->AllocDescriptor.Name))) {
|
||||
StackBase = Hob.MemoryAllocationStack->AllocDescriptor.MemoryBaseAddress;
|
||||
break;
|
||||
}
|
||||
Hob.Raw = GET_NEXT_HOB (Hob);
|
||||
}
|
||||
} else {
|
||||
//
|
||||
// Ask AP to return is stack base address.
|
||||
//
|
||||
MpInitLibStartupThisAP(GetStackBase, Index, NULL, 0, (VOID *)&StackBase, NULL);
|
||||
}
|
||||
//
|
||||
// Set Guard page at stack base address.
|
||||
//
|
||||
ConvertMemoryPageAttributes(StackBase, EFI_PAGE_SIZE, 0);
|
||||
DEBUG ((DEBUG_INFO, "Stack Guard set at %lx [cpu%lu]!\n",
|
||||
(UINT64)StackBase, (UINT64)Index));
|
||||
}
|
||||
|
||||
//
|
||||
// Publish the changes of page table.
|
||||
//
|
||||
CpuFlushTlb ();
|
||||
}
|
||||
|
||||
/**
|
||||
Enabl/setup stack guard for each processor if PcdCpuStackGuard is set to TRUE.
|
||||
|
||||
Doing this in the memory-discovered callback is to make sure the Stack Guard
|
||||
feature to cover as most PEI code as possible.
|
||||
|
||||
@param[in] PeiServices General purpose services available to every PEIM.
|
||||
@param[in] NotifyDescriptor The notification structure this PEIM registered on install.
|
||||
@param[in] Ppi The memory discovered PPI. Not used.
|
||||
|
||||
@retval EFI_SUCCESS The function completed successfully.
|
||||
@retval others There's error in MP initialization.
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
MemoryDiscoveredPpiNotifyCallback (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
|
||||
IN VOID *Ppi
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
BOOLEAN InitStackGuard;
|
||||
|
||||
//
|
||||
// Paging must be setup first. Otherwise the exception TSS setup during MP
|
||||
// initialization later will not contain paging information and then fail
|
||||
// the task switch (for the sake of stack switch).
|
||||
//
|
||||
InitStackGuard = FALSE;
|
||||
if (IsIa32PaeSupported () && PcdGetBool (PcdCpuStackGuard)) {
|
||||
EnablePaging ();
|
||||
InitStackGuard = TRUE;
|
||||
}
|
||||
|
||||
Status = InitializeCpuMpWorker ((CONST EFI_PEI_SERVICES **)PeiServices);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
if (InitStackGuard) {
|
||||
SetupStackGuardPage ();
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue