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UefiCpuPkg/MtrrLib: MtrrValidBitsMask and MtrrValidAddressMask wrong 

Per IA32 SDM, if CPUID.80000008H is not available, software may assume that the
processor supports a 36-bit physical address size.
However, for such old processors (For example, Quark processor),
MtrrValidBitsMask and MtrrValidAddressMask values are reverted and wrong in
MtrrLib. MtrrValidBitsMask should be 0xFFFFFFFFFULL and MtrrValidAddressMask
should be 0xFFFFFF000ULL.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18396 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Jeff Fan 2015-09-05 02:07:02 +00:00 committed by vanjeff
parent 5fe9871620
commit 0a4f7aa056
1 changed files with 3 additions and 3 deletions
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6
UefiCpuPkg/Library/MtrrLib/MtrrLib.c
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@ -1,7 +1,7 @@
/** @file /** @file
MTRR setting library MTRR setting library
Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR> Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -840,8 +840,8 @@ MtrrLibInitializeMtrrMask (
*MtrrValidBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1; *MtrrValidBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
*MtrrValidAddressMask = *MtrrValidBitsMask & 0xfffffffffffff000ULL; *MtrrValidAddressMask = *MtrrValidBitsMask & 0xfffffffffffff000ULL;
} else { } else {
*MtrrValidBitsMask = MTRR_LIB_CACHE_VALID_ADDRESS; *MtrrValidBitsMask = MTRR_LIB_MSR_VALID_MASK;
*MtrrValidAddressMask = 0xFFFFFFFF; *MtrrValidAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
} }
} }