mirror of https://github.com/acidanthera/audk.git
BaseTools/GenFw AARCH64: add support for relative data relocations
This adds support to the ELF to PE/COFF conversion performed by GenFw for the AArch64 ELF relocation types R_AARCH64_PREL64, R_AARCH64_PREL32 and R_AARCH64_PREL16. Since we already require the ELF and PE/COFF section layouts to be identical in order to support other relative relocation types, this is simply a matter of whitelisting these new relocation types in the same way. While we're at it, clean up the code a bit, and add a comment explaining why these relocations are ignored in WriteRelocations64 (). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
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@ -767,6 +767,9 @@ WriteSections64 (
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case R_AARCH64_LD_PREL_LO19:
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case R_AARCH64_CALL26:
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case R_AARCH64_JUMP26:
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case R_AARCH64_PREL64:
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case R_AARCH64_PREL32:
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case R_AARCH64_PREL16:
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//
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// The GCC toolchains (i.e., binutils) may corrupt section relative
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// relocations when emitting relocation sections into fully linked
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@ -855,20 +858,13 @@ WriteRelocations64 (
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switch (ELF_R_TYPE(Rel->r_info)) {
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case R_AARCH64_ADR_PREL_LO21:
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break;
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case R_AARCH64_CONDBR19:
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break;
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case R_AARCH64_LD_PREL_LO19:
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break;
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case R_AARCH64_CALL26:
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break;
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case R_AARCH64_JUMP26:
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break;
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case R_AARCH64_PREL64:
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case R_AARCH64_PREL32:
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case R_AARCH64_PREL16:
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case R_AARCH64_ADR_PREL_PG_HI21:
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case R_AARCH64_ADD_ABS_LO12_NC:
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case R_AARCH64_LDST8_ABS_LO12_NC:
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@ -876,6 +872,12 @@ WriteRelocations64 (
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case R_AARCH64_LDST32_ABS_LO12_NC:
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case R_AARCH64_LDST64_ABS_LO12_NC:
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case R_AARCH64_LDST128_ABS_LO12_NC:
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//
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// No fixups are required for relative relocations, provided that
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// the relative offsets between sections have been preserved in
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// the ELF to PE/COFF conversion. We have already asserted that
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// this is the case in WriteSections64 ().
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//
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break;
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case R_AARCH64_ABS64:
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