mirror of https://github.com/acidanthera/audk.git
ArmPkg/ArmLib: Update Arm11 port
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12454 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
parent
bd6b97994a
commit
0c0e7ef451
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@ -0,0 +1,67 @@
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <Library/ArmCpuLib.h>
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.text
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.align 3
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GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
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GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
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// VOID
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// ArmCpuSynchronizeWait (
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// IN ARM_CPU_SYNCHRONIZE_EVENT Event
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// );
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ASM_PFX(ArmCpuSynchronizeWait):
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cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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// The SCU enabled is the event to tell us the Init Boot Memory is initialized
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bx lr
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b CArmCpuSynchronizeWait
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#if 0
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GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
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GCC_ASM_EXPORT(ArmGetScuBaseAddress)
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GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
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// VOID
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// ArmCpuSynchronizeWait (
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// IN ARM_CPU_SYNCHRONIZE_EVENT Event
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// );
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ASM_PFX(ArmCpuSynchronizeWait):
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cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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// The SCU enabled is the event to tell us the Init Boot Memory is initialized
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beq ArmWaitScuEnabled
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b CArmCpuSynchronizeWait
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// IN None
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// OUT r0 = SCU Base Address
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ASM_PFX(ArmGetScuBaseAddress):
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// Read Configuration Base Address Register. ArmCBar cannot be called to get
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// the Configuration BAR as a stack is not necessary setup. The SCU is at the
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// offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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bx lr
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ASM_PFX(ArmWaitScuEnabled):
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// Read Configuration Base Address Register. ArmCBar cannot be called to get
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// the Configuration BAR as a stack is not necessary setup. The SCU is at the
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// offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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add r0, r0, #A9_SCU_CONTROL_OFFSET
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ldr r0, [r0]
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cmp r0, #1
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bne ArmWaitScuEnabled
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bx lr
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#endif
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@ -0,0 +1,54 @@
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <Library/ArmCpuLib.h>
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#include <Chipset/ArmCortexA9.h>
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EXPORT ArmCpuSynchronizeWait
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EXPORT ArmGetScuBaseAddress
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IMPORT CArmCpuSynchronizeWait
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PRESERVE8
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AREA ArmCortexA9Helper, CODE, READONLY
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// VOID
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// ArmCpuSynchronizeWait (
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// IN ARM_CPU_SYNCHRONIZE_EVENT Event
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// );
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ArmCpuSynchronizeWait
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cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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// The SCU enabled is the event to tell us the Init Boot Memory is initialized
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beq ArmWaitScuEnabled
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b CArmCpuSynchronizeWait
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// IN None
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// OUT r0 = SCU Base Address
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ArmGetScuBaseAddress
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// Read Configuration Base Address Register. ArmCBar cannot be called to get
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// the Configuration BAR as a stack is not necessary setup. The SCU is at the
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// offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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bx lr
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ArmWaitScuEnabled
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// Read Configuration Base Address Register. ArmCBar cannot be called to get
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// the Configuration BAR as a stack is not necessary setup. The SCU is at the
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// offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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add r0, r0, #A9_SCU_CONTROL_OFFSET
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ldr r0, [r0]
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cmp r0, #1
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bne ArmWaitScuEnabled
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bx lr
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END
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@ -0,0 +1,112 @@
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/** @file
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Copyright (c) 2011, ARM Limited. All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmCpuLib.h>
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#include <Library/ArmGicLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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VOID
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ArmCpuSynchronizeSignal (
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IN ARM_CPU_SYNCHRONIZE_EVENT Event
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)
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{
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if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {
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// Do nothing, Cortex A9 secondary cores are waiting for the SCU to be
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// enabled (done by ArmCpuSetup()) as a way to know when the Init Boot
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// Mem as been initialized
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} else {
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// Send SGI to all Secondary core to wake them up from WFI state.
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ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
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}
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}
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VOID
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CArmCpuSynchronizeWait (
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IN ARM_CPU_SYNCHRONIZE_EVENT Event
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)
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{
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// Waiting for the SGI from the primary core
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ArmCallWFI ();
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// Acknowledge the interrupt and send End of Interrupt signal.
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ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
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}
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#if 0
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VOID
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ArmEnableScu (
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VOID
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)
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{
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INTN ScuBase;
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ScuBase = ArmGetScuBaseAddress();
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// Invalidate all: write -1 to SCU Invalidate All register
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MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);
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// Enable SCU
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MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);
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}
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#endif
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VOID
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ArmCpuSetup (
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IN UINTN MpId
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)
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{
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/*AMP mode and SMP mode
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By default, the processor is in AMP mode (bit 5 reset to 0). To prevent coherent data corruption the sequence to turn on MP11 CPUs in SMP mode is:
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1.Write the SCU register to change CPU mode.
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2.Disable interrupts.
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3.Clean and invalidate all the D-cache.
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4.Write SMP/nAMP bit as 1.
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5.Enable interrupts.
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Source: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/BIHHFGEC.html
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*/
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// If MPCore then Enable the SCU
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if (ArmIsMpCore()) {
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//ArmEnableScu ();
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}
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}
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VOID
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ArmCpuSetupSmpNonSecure (
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IN UINTN MpId
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)
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{
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#if 0
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INTN ScuBase;
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ArmSetAuxCrBit (A9_FEATURE_SMP);
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// Make the SCU accessible in Non Secure world
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if (IS_PRIMARY_CORE(MpId)) {
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ScuBase = ArmGetScuBaseAddress();
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// Allow NS access to SCU register
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MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
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// Allow NS access to Private Peripherals
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MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
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}
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#endif
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}
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@ -0,0 +1,42 @@
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#/* @file
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#*/
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = Arm11MpCoreLib
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FILE_GUID = dc8a69e0-6be0-469c-94d3-5e6d71aa9808
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MODULE_TYPE = BASE
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VERSION_STRING = 1.0
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LIBRARY_CLASS = ArmCpuLib
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[Packages]
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MdePkg/MdePkg.dec
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ArmPkg/ArmPkg.dec
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[LibraryClasses]
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ArmLib
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ArmGicSecLib
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IoLib
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PcdLib
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[Sources.common]
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Arm11Lib.c
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Arm11Helper.asm | RVCT
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Arm11Helper.S | GCC
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
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gArmTokenSpaceGuid.PcdArmPrimaryCore
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gArmTokenSpaceGuid.PcdGicDistributorBase
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
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@ -108,4 +108,20 @@
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TT_DESCRIPTOR_SECTION_AP_RW_RW | \
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TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
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#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
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// NSACR - Non-Secure Access Control Register definitions
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#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
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#define NSACR_PLE 0
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#define NSACR_TL 0
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#define NSACR_NS_SMP 0
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// SCR - Secure Configuration Register definitions
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#define SCR_NS (1 << 0)
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#define SCR_IRQ (1 << 1)
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#define SCR_FIQ (1 << 2)
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#define SCR_EA (1 << 3)
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#define SCR_FW (1 << 4)
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#define SCR_AW (1 << 5)
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#endif // __ARM1176JZ_S_H__
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@ -1,6 +1,7 @@
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/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011, ARM Limited. All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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@ -13,121 +14,36 @@
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**/
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#include <Chipset/ARM1176JZ-S.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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VOID
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FillTranslationTable (
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IN UINT32 *TranslationTable,
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
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)
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{
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UINT32 *Entry;
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UINTN Sections;
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UINTN Index;
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UINT32 Attributes;
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UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
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switch (MemoryRegion->Attributes) {
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
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break;
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default:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
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break;
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}
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Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
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Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
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for (Index = 0; Index < Sections; Index++)
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{
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*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
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PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
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}
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}
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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VOID
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EFIAPI
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ArmConfigureMmu (
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
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OUT VOID **TranslationTableBase OPTIONAL,
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OUT UINTN *TranslationTableSize OPTIONAL
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ArmWriteVBar (
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IN UINT32 VectorBase
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)
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{
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VOID *TranslationTable;
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ASSERT(FeaturePcdGet (PcdRelocateVectorTable) == TRUE);
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// Allocate pages for translation table.
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TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
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TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
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if (TranslationTableBase != NULL) {
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*TranslationTableBase = TranslationTable;
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if (VectorBase == 0x0) {
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ArmSetLowVectors ();
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} else if (VectorBase == 0xFFFF0000) {
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ArmSetHighVectors ();
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} else {
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// Feature not supported by ARM11. The Vector Table is either at 0x0 or 0xFFFF0000
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ASSERT(0);
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}
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if (TranslationTableBase != NULL) {
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*TranslationTableSize = TRANSLATION_TABLE_SIZE;
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}
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ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
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ArmCleanInvalidateDataCache();
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ArmInvalidateInstructionCache();
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ArmInvalidateTlb();
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ArmDisableDataCache();
|
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ArmDisableInstructionCache();
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ArmDisableMmu();
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// Make sure nothing sneaked into the cache
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ArmCleanInvalidateDataCache();
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ArmInvalidateInstructionCache();
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while (MemoryTable->Length != 0) {
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FillTranslationTable(TranslationTable, MemoryTable);
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MemoryTable++;
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}
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|
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ArmSetTTBR0(TranslationTable);
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|
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ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
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DOMAIN_ACCESS_CONTROL_NONE(14) |
|
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DOMAIN_ACCESS_CONTROL_NONE(13) |
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DOMAIN_ACCESS_CONTROL_NONE(12) |
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DOMAIN_ACCESS_CONTROL_NONE(11) |
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DOMAIN_ACCESS_CONTROL_NONE(10) |
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DOMAIN_ACCESS_CONTROL_NONE( 9) |
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DOMAIN_ACCESS_CONTROL_NONE( 8) |
|
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DOMAIN_ACCESS_CONTROL_NONE( 7) |
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DOMAIN_ACCESS_CONTROL_NONE( 6) |
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DOMAIN_ACCESS_CONTROL_NONE( 5) |
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DOMAIN_ACCESS_CONTROL_NONE( 4) |
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DOMAIN_ACCESS_CONTROL_NONE( 3) |
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DOMAIN_ACCESS_CONTROL_NONE( 2) |
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DOMAIN_ACCESS_CONTROL_NONE( 1) |
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DOMAIN_ACCESS_CONTROL_MANAGER(0));
|
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|
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ArmEnableInstructionCache();
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ArmEnableDataCache();
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||||
ArmEnableMmu();
|
||||
}
|
||||
|
||||
|
||||
|
||||
UINT32
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||||
EFIAPI
|
||||
ArmReadVBar (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ASSERT((FeaturePcdGet (PcdRelocateVectorTable) == TRUE) && ((PcdGet32 (PcdCpuVectorBaseAddress) == 0x0) || (PcdGet32 (PcdCpuVectorBaseAddress) == 0xFFFF0000)));
|
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return PcdGet32 (PcdCpuVectorBaseAddress);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@
|
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Arm11Support.asm | RVCT
|
||||
|
||||
Arm11Lib.c
|
||||
Arm11LibMem.c
|
||||
../Arm9/Arm9CacheInformation.c
|
||||
|
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[Packages]
|
||||
|
|
@ -42,5 +43,9 @@
|
|||
[Protocols]
|
||||
gEfiCpuArchProtocolGuid
|
||||
|
||||
[FeaturePcd]
|
||||
gArmTokenSpaceGuid.PcdRelocateVectorTable
|
||||
|
||||
[FixedPcd]
|
||||
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
|
||||
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Chipset/ARM1176JZ-S.h>
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
|
||||
VOID
|
||||
FillTranslationTable (
|
||||
IN UINT32 *TranslationTable,
|
||||
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
|
||||
)
|
||||
{
|
||||
UINT32 *Entry;
|
||||
UINTN Sections;
|
||||
UINTN Index;
|
||||
UINT32 Attributes;
|
||||
UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
|
||||
|
||||
switch (MemoryRegion->Attributes) {
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
|
||||
break;
|
||||
default:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
|
||||
break;
|
||||
}
|
||||
|
||||
Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
|
||||
Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
|
||||
|
||||
for (Index = 0; Index < Sections; Index++)
|
||||
{
|
||||
*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
|
||||
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmConfigureMmu (
|
||||
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
|
||||
OUT VOID **TranslationTableBase OPTIONAL,
|
||||
OUT UINTN *TranslationTableSize OPTIONAL
|
||||
)
|
||||
{
|
||||
VOID *TranslationTable;
|
||||
|
||||
// Allocate pages for translation table.
|
||||
TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
|
||||
TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
|
||||
|
||||
if (TranslationTableBase != NULL) {
|
||||
*TranslationTableBase = TranslationTable;
|
||||
}
|
||||
|
||||
if (TranslationTableBase != NULL) {
|
||||
*TranslationTableSize = TRANSLATION_TABLE_SIZE;
|
||||
}
|
||||
|
||||
ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
|
||||
|
||||
ArmCleanInvalidateDataCache();
|
||||
ArmInvalidateInstructionCache();
|
||||
ArmInvalidateTlb();
|
||||
|
||||
ArmDisableDataCache();
|
||||
ArmDisableInstructionCache();
|
||||
ArmDisableMmu();
|
||||
|
||||
// Make sure nothing sneaked into the cache
|
||||
ArmCleanInvalidateDataCache();
|
||||
ArmInvalidateInstructionCache();
|
||||
|
||||
while (MemoryTable->Length != 0) {
|
||||
FillTranslationTable(TranslationTable, MemoryTable);
|
||||
MemoryTable++;
|
||||
}
|
||||
|
||||
ArmSetTTBR0(TranslationTable);
|
||||
|
||||
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(14) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(13) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(12) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(11) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(10) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 9) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 8) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 7) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 6) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 5) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 4) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 3) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 2) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 1) |
|
||||
DOMAIN_ACCESS_CONTROL_MANAGER(0));
|
||||
|
||||
ArmEnableInstructionCache();
|
||||
ArmEnableDataCache();
|
||||
ArmEnableMmu();
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -30,6 +30,7 @@
|
|||
Arm11Support.asm | RVCT
|
||||
|
||||
Arm11Lib.c
|
||||
Arm11LibMem.c
|
||||
../Arm9/Arm9CacheInformation.c
|
||||
|
||||
[Packages]
|
||||
|
|
@ -42,5 +43,9 @@
|
|||
[Protocols]
|
||||
gEfiCpuArchProtocolGuid
|
||||
|
||||
[FeaturePcd]
|
||||
gArmTokenSpaceGuid.PcdRelocateVectorTable
|
||||
|
||||
[FixedPcd]
|
||||
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
|
||||
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
#/** @file
|
||||
# Semihosting serail port lib
|
||||
#
|
||||
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = Arm11LibSec
|
||||
FILE_GUID = bfecdbc7-a860-4993-bc09-8e3ea762a758
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = ArmLib
|
||||
|
||||
[Sources.common]
|
||||
../Common/ArmLibSupport.S | GCC
|
||||
../Common/ArmLibSupport.asm | RVCT
|
||||
../Common/ArmLib.c
|
||||
|
||||
Arm11Support.S | GCC
|
||||
Arm11Support.asm | RVCT
|
||||
|
||||
Arm11Lib.c
|
||||
../Arm9/Arm9CacheInformation.c
|
||||
|
||||
[Packages]
|
||||
ArmPkg/ArmPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
|
||||
[Protocols]
|
||||
gEfiCpuArchProtocolGuid
|
||||
|
||||
[FeaturePcd]
|
||||
gArmTokenSpaceGuid.PcdRelocateVectorTable
|
||||
|
||||
[FixedPcd]
|
||||
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
|
||||
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress
|
||||
|
|
@ -1,6 +1,7 @@
|
|||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
# Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
|
|
@ -16,6 +17,8 @@
|
|||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(ArmDisableCachesAndMmu)
|
||||
GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)
|
||||
GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
|
||||
GCC_ASM_EXPORT(ArmCleanDataCache)
|
||||
GCC_ASM_EXPORT(ArmInvalidateDataCache)
|
||||
|
|
@ -35,11 +38,39 @@ GCC_ASM_EXPORT(ArmDisableBranchPrediction)
|
|||
GCC_ASM_EXPORT(ArmDataMemoryBarrier)
|
||||
GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
|
||||
GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
|
||||
GCC_ASM_EXPORT(ArmSetLowVectors)
|
||||
GCC_ASM_EXPORT(ArmSetHighVectors)
|
||||
GCC_ASM_EXPORT(ArmIsMpCore)
|
||||
GCC_ASM_EXPORT(ArmCallWFI)
|
||||
GCC_ASM_EXPORT(ArmReadMpidr)
|
||||
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
|
||||
GCC_ASM_EXPORT(ArmEnableFiq)
|
||||
GCC_ASM_EXPORT(ArmDisableFiq)
|
||||
GCC_ASM_EXPORT(ArmEnableInterrupts)
|
||||
GCC_ASM_EXPORT(ArmDisableInterrupts)
|
||||
GCC_ASM_EXPORT (ArmEnableVFP)
|
||||
|
||||
Arm11PartNumberMask: .word 0xFFF0
|
||||
Arm11PartNumber: .word 0xB020
|
||||
|
||||
.set DC_ON, (0x1<<2)
|
||||
.set IC_ON, (0x1<<12)
|
||||
.set XP_ON, (0x1<<23)
|
||||
.set CTRL_M_BIT, (1 << 0)
|
||||
.set CTRL_C_BIT, (1 << 2)
|
||||
.set CTRL_I_BIT, (1 << 12)
|
||||
|
||||
ASM_PFX(ArmDisableCachesAndMmu):
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Get control register
|
||||
bic r0, r0, #CTRL_M_BIT @ Disable MMU
|
||||
bic r0, r0, #CTRL_C_BIT @ Disable D Cache
|
||||
bic r0, r0, #CTRL_I_BIT @ Disable I Cache
|
||||
mcr p15, 0, r0, c1, c0, 0 @ Write control register
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInvalidateInstructionAndDataTlb):
|
||||
mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
|
||||
|
|
@ -153,5 +184,79 @@ ASM_PFX(ArmInstructionSynchronizationBarrier):
|
|||
mcr P15, #0, R0, C7, C5, #4
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmSetLowVectors):
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
||||
bic r0, r0, #0x00002000 @ clear V bit
|
||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmSetHighVectors):
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
||||
orr r0, r0, #0x00002000 @ clear V bit
|
||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmIsMpCore):
|
||||
push { r1 }
|
||||
mrc p15, 0, r0, c0, c0, 0
|
||||
# Extract Part Number to check it is an ARM11MP core (0xB02)
|
||||
LoadConstantToReg (Arm11PartNumberMask, r1)
|
||||
and r0, r0, r1
|
||||
LoadConstantToReg (Arm11PartNumber, r1)
|
||||
cmp r0, r1
|
||||
movne r0, #0
|
||||
pop { r1 }
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmCallWFI):
|
||||
wfi
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmReadMpidr):
|
||||
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmEnableFiq):
|
||||
mrs R0,CPSR
|
||||
bic R0,R0,#0x40 @Enable FIQ interrupts
|
||||
msr CPSR_c,R0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableFiq):
|
||||
mrs R0,CPSR
|
||||
orr R1,R0,#0x40 @Disable FIQ interrupts
|
||||
msr CPSR_c,R1
|
||||
tst R0,#0x80
|
||||
moveq R0,#1
|
||||
movne R0,#0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableInterrupts):
|
||||
mrs R0,CPSR
|
||||
bic R0,R0,#0x80 @Enable IRQ interrupts
|
||||
msr CPSR_c,R0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableInterrupts):
|
||||
mrs R0,CPSR
|
||||
orr R1,R0,#0x80 @Disable IRQ interrupts
|
||||
msr CPSR_c,R1
|
||||
tst R0,#0x80
|
||||
moveq R0,#1
|
||||
movne R0,#0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableVFP):
|
||||
# Read CPACR (Coprocessor Access Control Register)
|
||||
mrc p15, 0, r0, c1, c0, 2
|
||||
# Enable VPF access (Full Access to CP10, CP11) (V* instructions)
|
||||
orr r0, r0, #0x00f00000
|
||||
# Write back CPACR (Coprocessor Access Control Register)
|
||||
mcr p15, 0, r0, c1, c0, 2
|
||||
# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
|
||||
mov r0, #0x40000000
|
||||
#TODO: Fixme - need compilation flag
|
||||
#fmxr FPEXC, r0
|
||||
bx lr
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||
|
|
|
|||
Loading…
Reference in New Issue