mirror of https://github.com/acidanthera/audk.git
ShellPkg/pci: Use PCI definitions defined in MdePkg
https://bugzilla.tianocore.org/show_bug.cgi?id=354 The patch removes the local PCI definitions and uses the definitions defined in MdePkg/Include/IndustryStandard folder. There is no functionality impact. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jaben Carsey <jarben.carsey@intel.com>
This commit is contained in:
Ruiyu Ni
parent
9d77acf156
commit
0c84a69fbe
File diff suppressed because it is too large
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@ -2,7 +2,7 @@
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Header file for Pci shell Debug1 function.
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Copyright (c) 2013 Hewlett-Packard Development Company, L.P.
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Copyright (c) 2005 - 2010, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2005 - 2017, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -23,399 +23,18 @@ typedef enum {
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PciUndefined
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} PCI_HEADER_TYPE;
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#define HEADER_TYPE_MULTI_FUNCTION 0x80
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#define MAX_BUS_NUMBER 255
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#define MAX_DEVICE_NUMBER 31
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#define MAX_FUNCTION_NUMBER 7
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#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10
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#define EFI_PCI_CAPABILITY_ID_PCIX 0x07
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#define CALC_EFI_PCI_ADDRESS(Bus, Dev, Func, Reg) \
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((UINT64) ((((UINTN) Bus) << 24) + (((UINTN) Dev) << 16) + (((UINTN) Func) << 8) + ((UINTN) Reg)))
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#define CALC_EFI_PCIEX_ADDRESS(Bus, Dev, Func, ExReg) ( \
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(UINT64) ((((UINTN) Bus) << 24) + (((UINTN) Dev) << 16) + (((UINTN) Func) << 8) + (LShiftU64 ((UINT64) ExReg, 32))) \
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);
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#define INDEX_OF(Field) ((UINT8 *) (Field) - (UINT8 *) mConfigSpace)
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#define PCI_BIT_0 0x00000001
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#define PCI_BIT_1 0x00000002
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#define PCI_BIT_2 0x00000004
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#define PCI_BIT_3 0x00000008
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#define PCI_BIT_4 0x00000010
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#define PCI_BIT_5 0x00000020
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#define PCI_BIT_6 0x00000040
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#define PCI_BIT_7 0x00000080
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#define PCI_BIT_8 0x00000100
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#define PCI_BIT_9 0x00000200
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#define PCI_BIT_10 0x00000400
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#define PCI_BIT_11 0x00000800
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#define PCI_BIT_12 0x00001000
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#define PCI_BIT_13 0x00002000
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#define PCI_BIT_14 0x00004000
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#define PCI_BIT_15 0x00008000
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//
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// PCIE device/port types
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//
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#define PCIE_PCIE_ENDPOINT 0
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#define PCIE_LEGACY_PCIE_ENDPOINT 1
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#define PCIE_ROOT_COMPLEX_ROOT_PORT 4
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#define PCIE_SWITCH_UPSTREAM_PORT 5
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#define PCIE_SWITCH_DOWNSTREAM_PORT 6
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#define PCIE_PCIE_TO_PCIX_BRIDGE 7
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#define PCIE_PCIX_TO_PCIE_BRIDGE 8
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#define PCIE_ROOT_COMPLEX_INTEGRATED_PORT 9
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#define PCIE_ROOT_COMPLEX_EVENT_COLLECTOR 10
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#define PCIE_DEVICE_PORT_TYPE_MAX 11
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#define IS_PCIE_ENDPOINT(DevicePortType) \
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((DevicePortType) == PCIE_PCIE_ENDPOINT || \
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(DevicePortType) == PCIE_LEGACY_PCIE_ENDPOINT || \
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(DevicePortType) == PCIE_ROOT_COMPLEX_INTEGRATED_PORT)
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((DevicePortType) == PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT || \
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(DevicePortType) == PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT || \
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(DevicePortType) == PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT)
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#define IS_PCIE_SWITCH(DevicePortType) \
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((DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) || \
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(DevicePortType == PCIE_SWITCH_DOWNSTREAM_PORT))
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//
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// Capabilities Register
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//
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#define PCIE_CAP_VERSION(PcieCapReg) \
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((PcieCapReg) & 0x0f)
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#define PCIE_CAP_DEVICEPORT_TYPE(PcieCapReg) \
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(((PcieCapReg) >> 4) & 0x0f)
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#define PCIE_CAP_SLOT_IMPLEMENTED(PcieCapReg) \
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(((PcieCapReg) >> 8) & 0x1)
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#define PCIE_CAP_INT_MSG_NUM(PcieCapReg) \
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(((PcieCapReg) >> 9) & 0x1f)
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//
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// Device Capabilities Register
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//
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#define PCIE_CAP_MAX_PAYLOAD(PcieDeviceCap) \
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((PcieDeviceCap) & 0x7)
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#define PCIE_CAP_PHANTOM_FUNC(PcieDeviceCap) \
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(((PcieDeviceCap) >> 3) & 0x3)
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#define PCIE_CAP_EXTENDED_TAG(PcieDeviceCap) \
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(((PcieDeviceCap) >> 5) & 0x1)
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#define PCIE_CAP_L0SLATENCY(PcieDeviceCap) \
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(((PcieDeviceCap) >> 6) & 0x7)
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#define PCIE_CAP_L1LATENCY(PcieDeviceCap) \
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(((PcieDeviceCap) >> 9) & 0x7)
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#define PCIE_CAP_ERR_REPORTING(PcieDeviceCap) \
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(((PcieDeviceCap) >> 15) & 0x1)
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#define PCIE_CAP_SLOT_POWER_VALUE(PcieDeviceCap) \
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(((PcieDeviceCap) >> 18) & 0x0ff)
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#define PCIE_CAP_SLOT_POWER_SCALE(PcieDeviceCap) \
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(((PcieDeviceCap) >> 26) & 0x3)
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#define PCIE_CAP_FUNC_LEVEL_RESET(PcieDeviceCap) \
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(((PcieDeviceCap) >> 28) & 0x1)
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//
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// Device Control Register
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//
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#define PCIE_CAP_COR_ERR_REPORTING_ENABLE(PcieDeviceControl) \
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((PcieDeviceControl) & 0x1)
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#define PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE(PcieDeviceControl) \
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(((PcieDeviceControl) >> 1) & 0x1)
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#define PCIE_CAP_FATAL_ERR_REPORTING_ENABLE(PcieDeviceControl) \
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(((PcieDeviceControl) >> 2) & 0x1)
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#define PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE(PcieDeviceControl) \
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(((PcieDeviceControl) >> 3) & 0x1)
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#define PCIE_CAP_RELAXED_ORDERING_ENABLE(PcieDeviceControl) \
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(((PcieDeviceControl) >> 4) & 0x1)
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#define PCIE_CAP_MAX_PAYLOAD_SIZE(PcieDeviceControl) \
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(((PcieDeviceControl) >> 5) & 0x7)
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#define PCIE_CAP_EXTENDED_TAG_ENABLE(PcieDeviceControl) \
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(((PcieDeviceControl) >> 8) & 0x1)
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#define PCIE_CAP_PHANTOM_FUNC_ENABLE(PcieDeviceControl) \
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(((PcieDeviceControl) >> 9) & 0x1)
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#define PCIE_CAP_AUX_PM_ENABLE(PcieDeviceControl) \
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(((PcieDeviceControl) >> 10) & 0x1)
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#define PCIE_CAP_NO_SNOOP_ENABLE(PcieDeviceControl) \
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(((PcieDeviceControl) >> 11) & 0x1)
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#define PCIE_CAP_MAX_READ_REQ_SIZE(PcieDeviceControl) \
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(((PcieDeviceControl) >> 12) & 0x7)
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#define PCIE_CAP_BRG_CONF_RETRY(PcieDeviceControl) \
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(((PcieDeviceControl) >> 15) & 0x1)
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//
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// Device Status Register
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//
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#define PCIE_CAP_COR_ERR_DETECTED(PcieDeviceStatus) \
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((PcieDeviceStatus) & 0x1)
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#define PCIE_CAP_NONFAT_ERR_DETECTED(PcieDeviceStatus) \
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(((PcieDeviceStatus) >> 1) & 0x1)
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#define PCIE_CAP_FATAL_ERR_DETECTED(PcieDeviceStatus) \
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(((PcieDeviceStatus) >> 2) & 0x1)
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#define PCIE_CAP_UNSUP_REQ_DETECTED(PcieDeviceStatus) \
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(((PcieDeviceStatus) >> 3) & 0x1)
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#define PCIE_CAP_AUX_POWER_DETECTED(PcieDeviceStatus) \
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(((PcieDeviceStatus) >> 4) & 0x1)
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#define PCIE_CAP_TRANSACTION_PENDING(PcieDeviceStatus) \
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(((PcieDeviceStatus) >> 5) & 0x1)
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//
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// Link Capabilities Register
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//
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#define PCIE_CAP_MAX_LINK_SPEED(PcieLinkCap) \
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((PcieLinkCap) & 0x0f)
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#define PCIE_CAP_MAX_LINK_WIDTH(PcieLinkCap) \
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(((PcieLinkCap) >> 4) & 0x3f)
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#define PCIE_CAP_ASPM_SUPPORT(PcieLinkCap) \
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(((PcieLinkCap) >> 10) & 0x3)
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#define PCIE_CAP_L0S_LATENCY(PcieLinkCap) \
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(((PcieLinkCap) >> 12) & 0x7)
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#define PCIE_CAP_L1_LATENCY(PcieLinkCap) \
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(((PcieLinkCap) >> 15) & 0x7)
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#define PCIE_CAP_CLOCK_PM(PcieLinkCap) \
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(((PcieLinkCap) >> 18) & 0x1)
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#define PCIE_CAP_SUP_DOWN_ERR_REPORTING(PcieLinkCap) \
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(((PcieLinkCap) >> 19) & 0x1)
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#define PCIE_CAP_LINK_ACTIVE_REPORTING(PcieLinkCap) \
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(((PcieLinkCap) >> 20) & 0x1)
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#define PCIE_CAP_LINK_BWD_NOTIF_CAP(PcieLinkCap) \
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(((PcieLinkCap) >> 21) & 0x1)
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#define PCIE_CAP_PORT_NUMBER(PcieLinkCap) \
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(((PcieLinkCap) >> 24) & 0x0ff)
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//
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// Link Control Register
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//
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#define PCIE_CAP_ASPM_CONTROL(PcieLinkControl) \
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((PcieLinkControl) & 0x3)
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#define PCIE_CAP_RCB(PcieLinkControl) \
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(((PcieLinkControl) >> 3) & 0x1)
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#define PCIE_CAP_LINK_DISABLE(PcieLinkControl) \
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(((PcieLinkControl) >> 4) & 0x1)
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#define PCIE_CAP_COMMON_CLK_CONF(PcieLinkControl) \
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(((PcieLinkControl) >> 6) & 0x1)
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#define PCIE_CAP_EXT_SYNC(PcieLinkControl) \
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(((PcieLinkControl) >> 7) & 0x1)
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#define PCIE_CAP_CLK_PWR_MNG(PcieLinkControl) \
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(((PcieLinkControl) >> 8) & 0x1)
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#define PCIE_CAP_HW_AUTO_WIDTH_DISABLE(PcieLinkControl) \
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(((PcieLinkControl) >> 9) & 0x1)
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#define PCIE_CAP_LINK_BDW_MNG_INT_EN(PcieLinkControl) \
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(((PcieLinkControl) >> 10) & 0x1)
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#define PCIE_CAP_LINK_AUTO_BDW_INT_EN(PcieLinkControl) \
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(((PcieLinkControl) >> 11) & 0x1)
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//
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// Link Status Register
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//
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#define PCIE_CAP_CUR_LINK_SPEED(PcieLinkStatus) \
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((PcieLinkStatus) & 0x0f)
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#define PCIE_CAP_NEGO_LINK_WIDTH(PcieLinkStatus) \
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(((PcieLinkStatus) >> 4) & 0x3f)
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#define PCIE_CAP_LINK_TRAINING(PcieLinkStatus) \
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(((PcieLinkStatus) >> 11) & 0x1)
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#define PCIE_CAP_SLOT_CLK_CONF(PcieLinkStatus) \
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(((PcieLinkStatus) >> 12) & 0x1)
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#define PCIE_CAP_DATA_LINK_ACTIVE(PcieLinkStatus) \
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(((PcieLinkStatus) >> 13) & 0x1)
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#define PCIE_CAP_LINK_BDW_MNG_STAT(PcieLinkStatus) \
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(((PcieLinkStatus) >> 14) & 0x1)
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#define PCIE_CAP_LINK_AUTO_BDW_STAT(PcieLinkStatus) \
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(((PcieLinkStatus) >> 15) & 0x1)
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//
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// Slot Capabilities Register
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//
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#define PCIE_CAP_ATT_BUT_PRESENT(PcieSlotCap) \
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((PcieSlotCap) & 0x1)
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#define PCIE_CAP_PWR_CTRLLER_PRESENT(PcieSlotCap) \
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(((PcieSlotCap) >> 1) & 0x1)
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#define PCIE_CAP_MRL_SENSOR_PRESENT(PcieSlotCap) \
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(((PcieSlotCap) >> 2) & 0x1)
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#define PCIE_CAP_ATT_IND_PRESENT(PcieSlotCap) \
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(((PcieSlotCap) >> 3) & 0x1)
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#define PCIE_CAP_PWD_IND_PRESENT(PcieSlotCap) \
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(((PcieSlotCap) >> 4) & 0x1)
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#define PCIE_CAP_HOTPLUG_SUPPRISE(PcieSlotCap) \
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(((PcieSlotCap) >> 5) & 0x1)
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#define PCIE_CAP_HOTPLUG_CAPABLE(PcieSlotCap) \
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(((PcieSlotCap) >> 6) & 0x1)
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#define PCIE_CAP_SLOT_PWR_LIMIT_VALUE(PcieSlotCap) \
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(((PcieSlotCap) >> 7) & 0x0ff)
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#define PCIE_CAP_SLOT_PWR_LIMIT_SCALE(PcieSlotCap) \
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(((PcieSlotCap) >> 15) & 0x3)
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#define PCIE_CAP_ELEC_INTERLOCK_PRESENT(PcieSlotCap) \
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(((PcieSlotCap) >> 17) & 0x1)
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#define PCIE_CAP_NO_COMM_COMPLETED_SUP(PcieSlotCap) \
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(((PcieSlotCap) >> 18) & 0x1)
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#define PCIE_CAP_PHY_SLOT_NUM(PcieSlotCap) \
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(((PcieSlotCap) >> 19) & 0x1fff)
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//
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// Slot Control Register
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//
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#define PCIE_CAP_ATT_BUT_ENABLE(PcieSlotControl) \
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((PcieSlotControl) & 0x1)
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#define PCIE_CAP_PWR_FLT_DETECT_ENABLE(PcieSlotControl) \
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(((PcieSlotControl) >> 1) & 0x1)
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#define PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE(PcieSlotControl) \
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(((PcieSlotControl) >> 2) & 0x1)
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#define PCIE_CAP_PRES_DETECT_CHANGE_ENABLE(PcieSlotControl) \
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(((PcieSlotControl) >> 3) & 0x1)
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#define PCIE_CAP_COMM_CMPL_INT_ENABLE(PcieSlotControl) \
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(((PcieSlotControl) >> 4) & 0x1)
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#define PCIE_CAP_HOTPLUG_INT_ENABLE(PcieSlotControl) \
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(((PcieSlotControl) >> 5) & 0x1)
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#define PCIE_CAP_ATT_IND_CTRL(PcieSlotControl) \
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(((PcieSlotControl) >> 6) & 0x3)
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#define PCIE_CAP_PWR_IND_CTRL(PcieSlotControl) \
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(((PcieSlotControl) >> 8) & 0x3)
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#define PCIE_CAP_PWR_CTRLLER_CTRL(PcieSlotControl) \
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(((PcieSlotControl) >> 10) & 0x1)
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#define PCIE_CAP_ELEC_INTERLOCK_CTRL(PcieSlotControl) \
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(((PcieSlotControl) >> 11) & 0x1)
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#define PCIE_CAP_DLINK_STAT_CHANGE_ENABLE(PcieSlotControl) \
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(((PcieSlotControl) >> 12) & 0x1)
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//
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// Slot Status Register
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//
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#define PCIE_CAP_ATT_BUT_PRESSED(PcieSlotStatus) \
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((PcieSlotStatus) & 0x1)
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#define PCIE_CAP_PWR_FLT_DETECTED(PcieSlotStatus) \
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(((PcieSlotStatus) >> 1) & 0x1)
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#define PCIE_CAP_MRL_SENSOR_CHANGED(PcieSlotStatus) \
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(((PcieSlotStatus) >> 2) & 0x1)
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#define PCIE_CAP_PRES_DETECT_CHANGED(PcieSlotStatus) \
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(((PcieSlotStatus) >> 3) & 0x1)
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#define PCIE_CAP_COMM_COMPLETED(PcieSlotStatus) \
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(((PcieSlotStatus) >> 4) & 0x1)
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#define PCIE_CAP_MRL_SENSOR_STATE(PcieSlotStatus) \
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(((PcieSlotStatus) >> 5) & 0x1)
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#define PCIE_CAP_PRES_DETECT_STATE(PcieSlotStatus) \
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(((PcieSlotStatus) >> 6) & 0x1)
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#define PCIE_CAP_ELEC_INTERLOCK_STATE(PcieSlotStatus) \
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(((PcieSlotStatus) >> 7) & 0x1)
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#define PCIE_CAP_DLINK_STAT_CHANGED(PcieSlotStatus) \
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(((PcieSlotStatus) >> 8) & 0x1)
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//
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// Root Control Register
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//
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#define PCIE_CAP_SYSERR_ON_CORERR_EN(PcieRootControl) \
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((PcieRootControl) & 0x1)
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#define PCIE_CAP_SYSERR_ON_NONFATERR_EN(PcieRootControl) \
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(((PcieRootControl) >> 1) & 0x1)
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#define PCIE_CAP_SYSERR_ON_FATERR_EN(PcieRootControl) \
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(((PcieRootControl) >> 2) & 0x1)
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#define PCIE_CAP_PME_INT_ENABLE(PcieRootControl) \
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(((PcieRootControl) >> 3) & 0x1)
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#define PCIE_CAP_CRS_SW_VIS_ENABLE(PcieRootControl) \
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(((PcieRootControl) >> 4) & 0x1)
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//
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// Root Capabilities Register
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//
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#define PCIE_CAP_CRS_SW_VIS(PcieRootCap) \
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((PcieRootCap) & 0x1)
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//
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// Root Status Register
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//
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#define PCIE_CAP_PME_REQ_ID(PcieRootStatus) \
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((PcieRootStatus) & 0x0ffff)
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#define PCIE_CAP_PME_STATUS(PcieRootStatus) \
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(((PcieRootStatus) >> 16) & 0x1)
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#define PCIE_CAP_PME_PENDING(PcieRootStatus) \
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(((PcieRootStatus) >> 17) & 0x1)
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((DevicePortType == PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT) || \
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(DevicePortType == PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT))
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#pragma pack(1)
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//
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// Common part of the PCI configuration space header for devices, P2P bridges,
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// and cardbus bridges
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//
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typedef struct {
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UINT16 VendorId;
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UINT16 DeviceId;
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UINT16 Command;
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UINT16 Status;
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UINT8 RevisionId;
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UINT8 ClassCode[3];
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UINT8 CacheLineSize;
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UINT8 PrimaryLatencyTimer;
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UINT8 HeaderType;
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UINT8 Bist;
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} PCI_COMMON_HEADER;
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//
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// PCI configuration space header for devices(after the common part)
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//
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typedef struct {
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UINT32 Bar[6]; // Base Address Registers
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UINT32 CardBusCISPtr; // CardBus CIS Pointer
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UINT16 SubVendorId; // Subsystem Vendor ID
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UINT16 SubSystemId; // Subsystem ID
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UINT32 ROMBar; // Expansion ROM Base Address
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UINT8 CapabilitiesPtr; // Capabilities Pointer
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UINT8 Reserved[3];
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UINT32 Reserved1;
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UINT8 InterruptLine; // Interrupt Line
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UINT8 InterruptPin; // Interrupt Pin
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UINT8 MinGnt; // Min_Gnt
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UINT8 MaxLat; // Max_Lat
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} PCI_DEVICE_HEADER;
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//
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// PCI configuration space header for pci-to-pci bridges(after the common part)
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//
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typedef struct {
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UINT32 Bar[2]; // Base Address Registers
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UINT8 PrimaryBus; // Primary Bus Number
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UINT8 SecondaryBus; // Secondary Bus Number
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UINT8 SubordinateBus; // Subordinate Bus Number
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UINT8 SecondaryLatencyTimer; // Secondary Latency Timer
|
||||
UINT8 IoBase; // I/O Base
|
||||
UINT8 IoLimit; // I/O Limit
|
||||
UINT16 SecondaryStatus; // Secondary Status
|
||||
UINT16 MemoryBase; // Memory Base
|
||||
UINT16 MemoryLimit; // Memory Limit
|
||||
UINT16 PrefetchableMemBase; // Pre-fetchable Memory Base
|
||||
UINT16 PrefetchableMemLimit; // Pre-fetchable Memory Limit
|
||||
UINT32 PrefetchableBaseUpper; // Pre-fetchable Base Upper 32 bits
|
||||
UINT32 PrefetchableLimitUpper; // Pre-fetchable Limit Upper 32 bits
|
||||
UINT16 IoBaseUpper; // I/O Base Upper 16 bits
|
||||
UINT16 IoLimitUpper; // I/O Limit Upper 16 bits
|
||||
UINT8 CapabilitiesPtr; // Capabilities Pointer
|
||||
UINT8 Reserved[3];
|
||||
|
||||
UINT32 ROMBar; // Expansion ROM Base Address
|
||||
UINT8 InterruptLine; // Interrupt Line
|
||||
UINT8 InterruptPin; // Interrupt Pin
|
||||
UINT16 BridgeControl; // Bridge Control
|
||||
} PCI_BRIDGE_HEADER;
|
||||
|
||||
//
|
||||
// PCI configuration space header for cardbus bridges(after the common part)
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base
|
||||
// Address Register
|
||||
//
|
||||
UINT8 CapabilitiesPtr; // 14h in pci-cardbus bridge.
|
||||
UINT8 Reserved;
|
||||
UINT16 SecondaryStatus; // Secondary Status
|
||||
UINT8 PciBusNumber; // PCI Bus Number
|
||||
UINT8 CardBusBusNumber; // CardBus Bus Number
|
||||
UINT8 SubordinateBusNumber; // Subordinate Bus Number
|
||||
UINT8 CardBusLatencyTimer; // CardBus Latency Timer
|
||||
UINT32 MemoryBase0; // Memory Base Register 0
|
||||
UINT32 MemoryLimit0; // Memory Limit Register 0
|
||||
UINT32 MemoryBase1;
|
||||
UINT32 MemoryLimit1;
|
||||
UINT32 IoBase0;
|
||||
UINT32 IoLimit0; // I/O Base Register 0
|
||||
UINT32 IoBase1; // I/O Limit Register 0
|
||||
UINT32 IoLimit1;
|
||||
|
||||
UINT8 InterruptLine; // Interrupt Line
|
||||
UINT8 InterruptPin; // Interrupt Pin
|
||||
UINT16 BridgeControl; // Bridge Control
|
||||
} PCI_CARDBUS_HEADER;
|
||||
|
||||
//
|
||||
// Data region after PCI configuration header(for cardbus bridge)
|
||||
//
|
||||
|
|
@ -429,35 +48,17 @@ typedef struct {
|
|||
} PCI_CARDBUS_DATA;
|
||||
|
||||
typedef union {
|
||||
PCI_DEVICE_HEADER Device;
|
||||
PCI_BRIDGE_HEADER Bridge;
|
||||
PCI_CARDBUS_HEADER CardBus;
|
||||
PCI_DEVICE_HEADER_TYPE_REGION Device;
|
||||
PCI_BRIDGE_CONTROL_REGISTER Bridge;
|
||||
PCI_CARDBUS_CONTROL_REGISTER CardBus;
|
||||
} NON_COMMON_UNION;
|
||||
|
||||
typedef struct {
|
||||
PCI_COMMON_HEADER Common;
|
||||
NON_COMMON_UNION NonCommon;
|
||||
UINT32 Data[48];
|
||||
PCI_DEVICE_INDEPENDENT_REGION Common;
|
||||
NON_COMMON_UNION NonCommon;
|
||||
UINT32 Data[48];
|
||||
} PCI_CONFIG_SPACE;
|
||||
|
||||
typedef struct {
|
||||
UINT8 PcieCapId;
|
||||
UINT8 NextCapPtr;
|
||||
UINT16 PcieCapReg;
|
||||
UINT32 PcieDeviceCap;
|
||||
UINT16 DeviceControl;
|
||||
UINT16 DeviceStatus;
|
||||
UINT32 LinkCap;
|
||||
UINT16 LinkControl;
|
||||
UINT16 LinkStatus;
|
||||
UINT32 SlotCap;
|
||||
UINT16 SlotControl;
|
||||
UINT16 SlotStatus;
|
||||
UINT16 RootControl;
|
||||
UINT16 RsvdP;
|
||||
UINT32 RootStatus;
|
||||
} PCIE_CAP_STRUCTURE;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif // _PCI_H_
|
||||
|
|
|
|||
Loading…
Reference in New Issue