UefiCpuPkg: Rename AsmRelocateApLoopStart.

Rename AsmRelocateApLoopStart to AsmRelocateApLoopStartAmdSev

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Sean Rhodes <sean@starlabs.systems>
Cc: James Lu <james.lu@intel.com>
Cc: Gua Guo <gua.guo@intel.com>
Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Yuanhao Xie 2023-03-01 14:09:53 +08:00 committed by mergify[bot]
parent facf52aeb8
commit 0d1ad06c27
4 changed files with 29 additions and 29 deletions

View File

@ -547,8 +547,8 @@ InitMpGlobalData (
// 64-bit AMD processors with SEV-ES
//
Address = BASE_4GB - 1;
ApLoopFunc = AddressMap->RelocateApLoopFuncAddress;
ApLoopFuncSize = AddressMap->RelocateApLoopFuncSize;
ApLoopFunc = AddressMap->RelocateApLoopFuncAddressAmdSev;
ApLoopFuncSize = AddressMap->RelocateApLoopFuncSizeAmdSev;
} else {
//
// Intel processors (32-bit or 64-bit), 32-bit AMD processors, or 64-bit AMD processors without SEV-ES

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@ -26,8 +26,8 @@ struc MP_ASSEMBLY_ADDRESS_MAP
.RendezvousFunnelSize CTYPE_UINTN 1
.RelocateApLoopFuncAddressGeneric CTYPE_UINTN 1
.RelocateApLoopFuncSizeGeneric CTYPE_UINTN 1
.RelocateApLoopFuncAddress CTYPE_UINTN 1
.RelocateApLoopFuncSize CTYPE_UINTN 1
.RelocateApLoopFuncAddressAmdSev CTYPE_UINTN 1
.RelocateApLoopFuncSizeAmdSev CTYPE_UINTN 1
.ModeTransitionOffset CTYPE_UINTN 1
.SwitchToRealNoNxOffset CTYPE_UINTN 1
.SwitchToRealPM16ModeOffset CTYPE_UINTN 1

View File

@ -179,8 +179,8 @@ typedef struct {
UINTN RendezvousFunnelSize;
UINT8 *RelocateApLoopFuncAddressGeneric;
UINTN RelocateApLoopFuncSizeGeneric;
UINT8 *RelocateApLoopFuncAddress;
UINTN RelocateApLoopFuncSize;
UINT8 *RelocateApLoopFuncAddressAmdSev;
UINTN RelocateApLoopFuncSizeAmdSev;
UINTN ModeTransitionOffset;
UINTN SwitchToRealNoNxOffset;
UINTN SwitchToRealPM16ModeOffset;
@ -388,7 +388,7 @@ typedef
**/
typedef
VOID
(EFIAPI *ASM_RELOCATE_AP_LOOP)(
(EFIAPI *ASM_RELOCATE_AP_LOOP_AMDSEV)(
IN BOOLEAN MwaitSupport,
IN UINTN ApTargetCState,
IN UINTN PmCodeSegment,
@ -429,7 +429,7 @@ AsmExchangeRole (
typedef union {
VOID *Data;
ASM_RELOCATE_AP_LOOP AmdSevEntry; // 64-bit AMD Sev processors
ASM_RELOCATE_AP_LOOP_AMDSEV AmdSevEntry; // 64-bit AMD Sev processors
ASM_RELOCATE_AP_LOOP_GENERIC GenericEntry; // Intel processors (32-bit or 64-bit), 32-bit AMD processors, or AMD non-Sev processors
} RELOCATE_AP_LOOP_ENTRY;

View File

@ -277,14 +277,14 @@ CProcedureInvoke:
%include "AmdSev.nasm"
RendezvousFunnelProcEnd:
;-------------------------------------------------------------------------------------
; AsmRelocateApLoopAmdSev (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfApStack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer);
;-------------------------------------------------------------------------------------
;-------------------------------------------------------------------------------------
; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfApStack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer);
;-------------------------------------------------------------------------------------
AsmRelocateApLoopStart:
AsmRelocateApLoopAmdSevStart:
BITS 64
cmp qword [rsp + 56], 0 ; SevEsAPJumpTable
je NoSevEs
je NoSevEsAmdSev
;
; Perform some SEV-ES related setup before leaving 64-bit mode
@ -329,7 +329,7 @@ BITS 64
pop rdx
pop rcx
NoSevEs:
NoSevEsAmdSev:
cli ; Disable interrupt before switching to 32-bit mode
mov rax, [rsp + 40] ; CountTofinish
lock dec dword [rax] ; (*CountTofinish)--
@ -345,7 +345,7 @@ NoSevEs:
push rcx ; Save MwaitSupport
push rdx ; Save ApTargetCState
lea rax, [PmEntry] ; rax <- The start address of transition code
lea rax, [PmEntryAmdSev] ; rax <- The start address of transition code
push r8
push rax
@ -365,10 +365,10 @@ NoSevEs:
;
; Far return into 32-bit mode
;
retfq
o64 retf
BITS 32
PmEntry:
PmEntryAmdSev:
mov eax, cr0
btr eax, 31 ; Clear CR0.PG
mov cr0, eax ; Disable paging and caches
@ -386,11 +386,11 @@ PmEntry:
pop ecx,
add esp, 4
MwaitCheck:
MwaitCheckAmdSev:
cmp cl, 1 ; Check mwait-monitor support
jnz HltLoop
jnz HltLoopAmdSev
mov ebx, edx ; Save C-State to ebx
MwaitLoop:
MwaitLoopAmdSev:
cli
mov eax, esp ; Set Monitor Address
xor ecx, ecx ; ecx = 0
@ -399,9 +399,9 @@ MwaitLoop:
mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4]
shl eax, 4
mwait
jmp MwaitLoop
jmp MwaitLoopAmdSev
HltLoop:
HltLoopAmdSev:
pop edx ; PM16CodeSegment
add esp, 4
pop ebx ; WakeupBuffer
@ -409,7 +409,7 @@ HltLoop:
pop eax ; SevEsAPJumpTable
add esp, 4
cmp eax, 0 ; Check for SEV-ES
je DoHlt
je DoHltAmdSev
cli
;
@ -439,13 +439,13 @@ BITS 32
retf
DoHlt:
DoHltAmdSev:
cli
hlt
jmp DoHlt
jmp DoHltAmdSev
BITS 64
AsmRelocateApLoopEnd:
AsmRelocateApLoopAmdSevEnd:
;-------------------------------------------------------------------------------------
; AsmRelocateApLoop (MwaitSupport, ApTargetCState, TopOfApStack, CountTofinish, Cr3);
@ -511,9 +511,9 @@ ASM_PFX(AsmGetAddressMap):
lea rax, [AsmRelocateApLoopGenericStart]
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddressGeneric], rax
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSizeGeneric], AsmRelocateApLoopGenericEnd - AsmRelocateApLoopGenericStart
lea rax, [AsmRelocateApLoopStart]
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddress], rax
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize], AsmRelocateApLoopEnd - AsmRelocateApLoopStart
lea rax, [AsmRelocateApLoopAmdSevStart]
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddressAmdSev], rax
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSizeAmdSev], AsmRelocateApLoopAmdSevEnd - AsmRelocateApLoopAmdSevStart
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset], Flat32Start - RendezvousFunnelProcStart
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset], SwitchToRealProcStart - Flat32Start
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOffset], PM16Mode - RendezvousFunnelProcStart