mirror of https://github.com/acidanthera/audk.git
ArmPkg/ArmExceptionLib: fold exception handler prologue into vector table
Unlike the AArch32 vector table, which has room for a single instruction for each exception type, the AArch64 exception table has 128 byte slots, which can easily hold the shared prologues that are emitted out of line. So refactor this code into a single macro, and expand it into each vector table slot. Since the address of the command handler entry point is no longer patched in by the C code, we can just emit the literal into each vector entry directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
This commit is contained in:
Ard Biesheuvel
parent
a34608ca96
commit
0dbbaa5573
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@ -99,8 +99,6 @@
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*/
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GCC_ASM_EXPORT(ExceptionHandlersEnd)
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GCC_ASM_EXPORT(CommonExceptionEntry)
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GCC_ASM_EXPORT(AsmCommonExceptionEntry)
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GCC_ASM_EXPORT(CommonCExceptionHandler)
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.text
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@ -172,90 +170,12 @@ ASM_PFX(ExceptionHandlersStart):
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VECTOR_BASE(ExceptionHandlersStart)
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#endif
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//
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// Current EL with SP0 : 0x0 - 0x180
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//
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_SYNC)
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ASM_PFX(SynchronousExceptionSP0):
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b ASM_PFX(SynchronousExceptionEntry)
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_IRQ)
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ASM_PFX(IrqSP0):
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b ASM_PFX(IrqEntry)
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_FIQ)
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ASM_PFX(FiqSP0):
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b ASM_PFX(FiqEntry)
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_SERR)
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ASM_PFX(SErrorSP0):
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b ASM_PFX(SErrorEntry)
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//
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// Current EL with SPx: 0x200 - 0x380
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//
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SYNC)
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ASM_PFX(SynchronousExceptionSPx):
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b ASM_PFX(SynchronousExceptionEntry)
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_IRQ)
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ASM_PFX(IrqSPx):
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b ASM_PFX(IrqEntry)
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_FIQ)
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ASM_PFX(FiqSPx):
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b ASM_PFX(FiqEntry)
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SERR)
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ASM_PFX(SErrorSPx):
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b ASM_PFX(SErrorEntry)
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//
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// Lower EL using AArch64 : 0x400 - 0x580
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//
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_SYNC)
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ASM_PFX(SynchronousExceptionA64):
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b ASM_PFX(SynchronousExceptionEntry)
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_IRQ)
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ASM_PFX(IrqA64):
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b ASM_PFX(IrqEntry)
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_FIQ)
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ASM_PFX(FiqA64):
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b ASM_PFX(FiqEntry)
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_SERR)
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ASM_PFX(SErrorA64):
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b ASM_PFX(SErrorEntry)
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//
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// Lower EL using AArch32 : 0x600 - 0x780
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//
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_SYNC)
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ASM_PFX(SynchronousExceptionA32):
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b ASM_PFX(SynchronousExceptionEntry)
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_IRQ)
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ASM_PFX(IrqA32):
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b ASM_PFX(IrqEntry)
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_FIQ)
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ASM_PFX(FiqA32):
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b ASM_PFX(FiqEntry)
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_SERR)
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ASM_PFX(SErrorA32):
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b ASM_PFX(SErrorEntry)
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VECTOR_END(ExceptionHandlersStart)
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#undef REG_PAIR
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#undef REG_ONE
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#define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE) stp REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)]
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#define REG_ONE(REG1, OFFSET, CONTEXT_SIZE) stur REG1, [sp, #(OFFSET-CONTEXT_SIZE)]
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ASM_PFX(SynchronousExceptionEntry):
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.macro ExceptionEntry, val
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// Move the stackpointer so we can reach our structure with the str instruction.
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sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)
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@ -264,50 +184,96 @@ ASM_PFX(SynchronousExceptionEntry):
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ALL_GP_REGS
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// Record the type of exception that occurred.
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mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
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mov x0, #\val
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// Jump to our general handler to deal with all the common parts and process the exception.
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ldr x1, ASM_PFX(CommonExceptionEntry)
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ldr x1, =ASM_PFX(CommonExceptionEntry)
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br x1
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ASM_PFX(IrqEntry):
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sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)
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ALL_GP_REGS
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mov x0, #EXCEPT_AARCH64_IRQ
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ldr x1, ASM_PFX(CommonExceptionEntry)
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br x1
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ASM_PFX(FiqEntry):
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sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)
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ALL_GP_REGS
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mov x0, #EXCEPT_AARCH64_FIQ
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ldr x1, ASM_PFX(CommonExceptionEntry)
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br x1
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ASM_PFX(SErrorEntry):
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sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)
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ALL_GP_REGS
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mov x0, #EXCEPT_AARCH64_SERROR
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ldr x1, ASM_PFX(CommonExceptionEntry)
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br x1
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.ltorg
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.endm
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//
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// This gets patched by the C code that patches in the vector table
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// Current EL with SP0 : 0x0 - 0x180
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//
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.align 3
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ASM_PFX(CommonExceptionEntry):
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.8byte ASM_PFX(AsmCommonExceptionEntry)
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_SYNC)
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ASM_PFX(SynchronousExceptionSP0):
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ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_IRQ)
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ASM_PFX(IrqSP0):
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ExceptionEntry EXCEPT_AARCH64_IRQ
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_FIQ)
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ASM_PFX(FiqSP0):
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ExceptionEntry EXCEPT_AARCH64_FIQ
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_SERR)
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ASM_PFX(SErrorSP0):
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ExceptionEntry EXCEPT_AARCH64_SERROR
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//
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// Current EL with SPx: 0x200 - 0x380
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//
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SYNC)
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ASM_PFX(SynchronousExceptionSPx):
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ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_IRQ)
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ASM_PFX(IrqSPx):
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ExceptionEntry EXCEPT_AARCH64_IRQ
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_FIQ)
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ASM_PFX(FiqSPx):
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ExceptionEntry EXCEPT_AARCH64_FIQ
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SERR)
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ASM_PFX(SErrorSPx):
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ExceptionEntry EXCEPT_AARCH64_SERROR
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//
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// Lower EL using AArch64 : 0x400 - 0x580
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//
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_SYNC)
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ASM_PFX(SynchronousExceptionA64):
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ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_IRQ)
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ASM_PFX(IrqA64):
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ExceptionEntry EXCEPT_AARCH64_IRQ
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_FIQ)
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ASM_PFX(FiqA64):
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ExceptionEntry EXCEPT_AARCH64_FIQ
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_SERR)
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ASM_PFX(SErrorA64):
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ExceptionEntry EXCEPT_AARCH64_SERROR
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//
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// Lower EL using AArch32 : 0x600 - 0x780
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//
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_SYNC)
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ASM_PFX(SynchronousExceptionA32):
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ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_IRQ)
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ASM_PFX(IrqA32):
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ExceptionEntry EXCEPT_AARCH64_IRQ
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_FIQ)
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ASM_PFX(FiqA32):
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ExceptionEntry EXCEPT_AARCH64_FIQ
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VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_SERR)
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ASM_PFX(SErrorA32):
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ExceptionEntry EXCEPT_AARCH64_SERROR
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VECTOR_END(ExceptionHandlersStart)
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ASM_PFX(ExceptionHandlersEnd):
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//
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// This code runs from CpuDxe driver loaded address. It is patched into
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// CommonExceptionEntry.
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//
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ASM_PFX(AsmCommonExceptionEntry):
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ASM_PFX(CommonExceptionEntry):
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/* NOTE:
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We have to break up the save code because the immediate value to be used
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with the SP is too big to do it all in one step so we need to shuffle the SP
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