From 0e07733023ea26901eec5c51d17e8f38d10d0dea Mon Sep 17 00:00:00 2001 From: Sami Mujawar Date: Tue, 16 May 2017 11:10:45 +0100 Subject: [PATCH] ArmPlatformPkg: Timer access for non-secure EL1/0 According to Section 2.3.6 of the "UEFI Specification 2.6 Errata A"; the primary CPU must be configured such that 'Timer access must be provided to non-secure EL1 and EL0 by setting bits EL1PCTEN and EL1PCEN in register CNTHCTL_EL2.' This commit adds this missing set-up to the PrePi and PrePeiCore modules. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- ArmPlatformPkg/PrePeiCore/AArch64/Helper.S | 9 ++++++++- ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c | 9 ++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S b/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S index 5f35484b12..b4f35b7ff5 100644 --- a/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S +++ b/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S @@ -1,5 +1,5 @@ #======================================================================================== -# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# Copyright (c) 2011-2017, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -36,6 +36,13 @@ ASM_FUNC(SetupExceptionLevel2) msr cptr_el2, xzr // Disable copro traps to EL2 + // Enable Timer access for non-secure EL1 and EL0 + // The cnthctl_el2 register bits are architecturally + // UNKNOWN on reset. + // Disable event stream as it is not in use at this stage + mov x0, #(CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN) + msr cnthctl_el2, x0 + ret ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c b/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c index 217986107e..4da590805a 100644 --- a/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c +++ b/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2011-2013, ARM Limited. All rights reserved. +* Copyright (c) 2011-2017, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -29,5 +29,12 @@ ArchInitialize ( if (ArmReadCurrentEL () == AARCH64_EL2) { // Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2 ArmWriteHcr (ARM_HCR_TGE); + + /* Enable Timer access for non-secure EL1 and EL0 + The cnthctl_el2 register bits are architecturally + UNKNOWN on reset. + Disable event stream as it is not in use at this stage + */ + ArmWriteCntHctl (CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN); } }