From 0e8768b65a10e96b5a044181b3bdd8b1c5cdcefd Mon Sep 17 00:00:00 2001
From: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@hp.com>
Date: Wed, 1 Jul 2015 15:21:35 +0000
Subject: [PATCH] MdePkg: Add P2P Bridge Secondary Latency Timer register
definition
Add P2P Bridge Secondary Latency Timer register definition to Pci22.h
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@hp.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17793 6f19259b-4bc3-4df7-8a09-765794883524
---
MdePkg/Include/IndustryStandard/Pci22.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MdePkg/Include/IndustryStandard/Pci22.h b/MdePkg/Include/IndustryStandard/Pci22.h
index 4a191403e3..78ec6b3166 100644
--- a/MdePkg/Include/IndustryStandard/Pci22.h
+++ b/MdePkg/Include/IndustryStandard/Pci22.h
@@ -9,7 +9,7 @@
Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
- Copyright (c) 2014, Hewlett-Packard Development Company, L.P.<BR>
+ Copyright (c) 2014 - 2105, Hewlett-Packard Development Company, L.P.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -552,6 +552,7 @@ typedef struct {
#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
+#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b
#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E