diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimerSupport.S b/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimerSupport.S index 3944d8bcb4..59e0bc9a07 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimerSupport.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimerSupport.S @@ -1,6 +1,7 @@ #------------------------------------------------------------------------------ # # Copyright (c) 2011 - 2013, ARM Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -12,127 +13,105 @@ # #------------------------------------------------------------------------------ -.text -.align 2 +#include -GCC_ASM_EXPORT(ArmReadCntFrq) -GCC_ASM_EXPORT(ArmWriteCntFrq) -GCC_ASM_EXPORT(ArmReadCntPct) -GCC_ASM_EXPORT(ArmReadCntkCtl) -GCC_ASM_EXPORT(ArmWriteCntkCtl) -GCC_ASM_EXPORT(ArmReadCntpTval) -GCC_ASM_EXPORT(ArmWriteCntpTval) -GCC_ASM_EXPORT(ArmReadCntpCtl) -GCC_ASM_EXPORT(ArmWriteCntpCtl) -GCC_ASM_EXPORT(ArmReadCntvTval) -GCC_ASM_EXPORT(ArmWriteCntvTval) -GCC_ASM_EXPORT(ArmReadCntvCtl) -GCC_ASM_EXPORT(ArmWriteCntvCtl) -GCC_ASM_EXPORT(ArmReadCntvCt) -GCC_ASM_EXPORT(ArmReadCntpCval) -GCC_ASM_EXPORT(ArmWriteCntpCval) -GCC_ASM_EXPORT(ArmReadCntvCval) -GCC_ASM_EXPORT(ArmWriteCntvCval) -GCC_ASM_EXPORT(ArmReadCntvOff) -GCC_ASM_EXPORT(ArmWriteCntvOff) - -ASM_PFX(ArmReadCntFrq): +ASM_FUNC(ArmReadCntFrq) mrs x0, cntfrq_el0 // Read CNTFRQ ret # NOTE - Can only write while at highest implemented EL level (EL3 on model). Else ReadOnly (EL2, EL1, EL0) -ASM_PFX(ArmWriteCntFrq): +ASM_FUNC(ArmWriteCntFrq) msr cntfrq_el0, x0 // Write to CNTFRQ ret -ASM_PFX(ArmReadCntPct): +ASM_FUNC(ArmReadCntPct) mrs x0, cntpct_el0 // Read CNTPCT (Physical counter register) ret -ASM_PFX(ArmReadCntkCtl): +ASM_FUNC(ArmReadCntkCtl) mrs x0, cntkctl_el1 // Read CNTK_CTL (Timer PL1 Control Register) ret -ASM_PFX(ArmWriteCntkCtl): +ASM_FUNC(ArmWriteCntkCtl) msr cntkctl_el1, x0 // Write to CNTK_CTL (Timer PL1 Control Register) ret -ASM_PFX(ArmReadCntpTval): +ASM_FUNC(ArmReadCntpTval) mrs x0, cntp_tval_el0 // Read CNTP_TVAL (PL1 physical timer value register) ret -ASM_PFX(ArmWriteCntpTval): +ASM_FUNC(ArmWriteCntpTval) msr cntp_tval_el0, x0 // Write to CNTP_TVAL (PL1 physical timer value register) ret -ASM_PFX(ArmReadCntpCtl): +ASM_FUNC(ArmReadCntpCtl) mrs x0, cntp_ctl_el0 // Read CNTP_CTL (PL1 Physical Timer Control Register) ret -ASM_PFX(ArmWriteCntpCtl): +ASM_FUNC(ArmWriteCntpCtl) msr cntp_ctl_el0, x0 // Write to CNTP_CTL (PL1 Physical Timer Control Register) ret -ASM_PFX(ArmReadCntvTval): +ASM_FUNC(ArmReadCntvTval) mrs x0, cntv_tval_el0 // Read CNTV_TVAL (Virtual Timer Value register) ret -ASM_PFX(ArmWriteCntvTval): +ASM_FUNC(ArmWriteCntvTval) msr cntv_tval_el0, x0 // Write to CNTV_TVAL (Virtual Timer Value register) ret -ASM_PFX(ArmReadCntvCtl): +ASM_FUNC(ArmReadCntvCtl) mrs x0, cntv_ctl_el0 // Read CNTV_CTL (Virtual Timer Control Register) ret -ASM_PFX(ArmWriteCntvCtl): +ASM_FUNC(ArmWriteCntvCtl) msr cntv_ctl_el0, x0 // Write to CNTV_CTL (Virtual Timer Control Register) ret -ASM_PFX(ArmReadCntvCt): +ASM_FUNC(ArmReadCntvCt) mrs x0, cntvct_el0 // Read CNTVCT (Virtual Count Register) ret -ASM_PFX(ArmReadCntpCval): +ASM_FUNC(ArmReadCntpCval) mrs x0, cntp_cval_el0 // Read CNTP_CTVAL (Physical Timer Compare Value Register) ret -ASM_PFX(ArmWriteCntpCval): +ASM_FUNC(ArmWriteCntpCval) msr cntp_cval_el0, x0 // Write to CNTP_CTVAL (Physical Timer Compare Value Register) ret -ASM_PFX(ArmReadCntvCval): +ASM_FUNC(ArmReadCntvCval) mrs x0, cntv_cval_el0 // Read CNTV_CTVAL (Virtual Timer Compare Value Register) ret -ASM_PFX(ArmWriteCntvCval): +ASM_FUNC(ArmWriteCntvCval) msr cntv_cval_el0, x0 // write to CNTV_CTVAL (Virtual Timer Compare Value Register) ret -ASM_PFX(ArmReadCntvOff): +ASM_FUNC(ArmReadCntvOff) mrs x0, cntvoff_el2 // Read CNTVOFF (virtual Offset register) ret -ASM_PFX(ArmWriteCntvOff): +ASM_FUNC(ArmWriteCntvOff) msr cntvoff_el2, x0 // Write to CNTVOFF (Virtual Offset register) ret diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S index 5cef98fd42..5cee7c1519 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S @@ -2,6 +2,7 @@ # # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -16,50 +17,6 @@ #include #include -.text -.align 3 - -GCC_ASM_EXPORT (ArmInvalidateInstructionCache) -GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA) -GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA) -GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA) -GCC_ASM_EXPORT (ArmInvalidateInstructionCacheEntryToPoUByMVA) -GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA) -GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay) -GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay) -GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay) -GCC_ASM_EXPORT (ArmEnableMmu) -GCC_ASM_EXPORT (ArmDisableMmu) -GCC_ASM_EXPORT (ArmDisableCachesAndMmu) -GCC_ASM_EXPORT (ArmMmuEnabled) -GCC_ASM_EXPORT (ArmEnableDataCache) -GCC_ASM_EXPORT (ArmDisableDataCache) -GCC_ASM_EXPORT (ArmEnableInstructionCache) -GCC_ASM_EXPORT (ArmDisableInstructionCache) -GCC_ASM_EXPORT (ArmDisableAlignmentCheck) -GCC_ASM_EXPORT (ArmEnableAlignmentCheck) -GCC_ASM_EXPORT (ArmEnableBranchPrediction) -GCC_ASM_EXPORT (ArmDisableBranchPrediction) -GCC_ASM_EXPORT (AArch64AllDataCachesOperation) -GCC_ASM_EXPORT (ArmDataMemoryBarrier) -GCC_ASM_EXPORT (ArmDataSynchronizationBarrier) -GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier) -GCC_ASM_EXPORT (ArmWriteVBar) -GCC_ASM_EXPORT (ArmReadVBar) -GCC_ASM_EXPORT (ArmEnableVFP) -GCC_ASM_EXPORT (ArmCallWFI) -GCC_ASM_EXPORT (ArmReadMpidr) -GCC_ASM_EXPORT (ArmReadTpidrurw) -GCC_ASM_EXPORT (ArmWriteTpidrurw) -GCC_ASM_EXPORT (ArmIsArchTimerImplemented) -GCC_ASM_EXPORT (ArmReadIdPfr0) -GCC_ASM_EXPORT (ArmReadIdPfr1) -GCC_ASM_EXPORT (ArmWriteHcr) -GCC_ASM_EXPORT (ArmReadHcr) -GCC_ASM_EXPORT (ArmReadCurrentEL) -GCC_ASM_EXPORT (ArmReplaceLiveTranslationEntry) -GCC_ASM_EXPORT (ArmReplaceLiveTranslationEntrySize) - .set CTRL_M_BIT, (1 << 0) .set CTRL_A_BIT, (1 << 1) .set CTRL_C_BIT, (1 << 2) @@ -67,53 +24,53 @@ GCC_ASM_EXPORT (ArmReplaceLiveTranslationEntrySize) .set CTRL_V_BIT, (1 << 12) .set CPACR_VFP_BITS, (3 << 20) -ASM_PFX(ArmInvalidateDataCacheEntryByMVA): +ASM_FUNC(ArmInvalidateDataCacheEntryByMVA) dc ivac, x0 // Invalidate single data cache line ret -ASM_PFX(ArmCleanDataCacheEntryByMVA): +ASM_FUNC(ArmCleanDataCacheEntryByMVA) dc cvac, x0 // Clean single data cache line ret -ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA): +ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA) dc cvau, x0 // Clean single data cache line to PoU ret -ASM_PFX(ArmInvalidateInstructionCacheEntryToPoUByMVA): +ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA) ic ivau, x0 // Invalidate single instruction cache line to PoU ret -ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): +ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA) dc civac, x0 // Clean and invalidate single data cache line ret -ASM_PFX(ArmInvalidateDataCacheEntryBySetWay): +ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay) dc isw, x0 // Invalidate this line ret -ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay): +ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay) dc cisw, x0 // Clean and Invalidate this line ret -ASM_PFX(ArmCleanDataCacheEntryBySetWay): +ASM_FUNC(ArmCleanDataCacheEntryBySetWay) dc csw, x0 // Clean this line ret -ASM_PFX(ArmInvalidateInstructionCache): +ASM_FUNC(ArmInvalidateInstructionCache) ic iallu // Invalidate entire instruction cache dsb sy isb ret -ASM_PFX(ArmEnableMmu): +ASM_FUNC(ArmEnableMmu) EL1_OR_EL2_OR_EL3(x1) 1: mrs x0, sctlr_el1 // Read System control register EL1 b 4f @@ -140,7 +97,7 @@ ASM_PFX(ArmEnableMmu): ret -ASM_PFX(ArmDisableMmu): +ASM_FUNC(ArmDisableMmu) EL1_OR_EL2_OR_EL3(x1) 1: mrs x0, sctlr_el1 // Read System Control Register EL1 b 4f @@ -162,7 +119,7 @@ ASM_PFX(ArmDisableMmu): ret -ASM_PFX(ArmDisableCachesAndMmu): +ASM_FUNC(ArmDisableCachesAndMmu) EL1_OR_EL2_OR_EL3(x1) 1: mrs x0, sctlr_el1 // Get control register EL1 b 4f @@ -182,7 +139,7 @@ ASM_PFX(ArmDisableCachesAndMmu): ret -ASM_PFX(ArmMmuEnabled): +ASM_FUNC(ArmMmuEnabled) EL1_OR_EL2_OR_EL3(x1) 1: mrs x0, sctlr_el1 // Get control register EL1 b 4f @@ -193,7 +150,7 @@ ASM_PFX(ArmMmuEnabled): ret -ASM_PFX(ArmEnableDataCache): +ASM_FUNC(ArmEnableDataCache) EL1_OR_EL2_OR_EL3(x1) 1: mrs x0, sctlr_el1 // Get control register EL1 b 4f @@ -212,7 +169,7 @@ ASM_PFX(ArmEnableDataCache): ret -ASM_PFX(ArmDisableDataCache): +ASM_FUNC(ArmDisableDataCache) EL1_OR_EL2_OR_EL3(x1) 1: mrs x0, sctlr_el1 // Get control register EL1 b 4f @@ -231,7 +188,7 @@ ASM_PFX(ArmDisableDataCache): ret -ASM_PFX(ArmEnableInstructionCache): +ASM_FUNC(ArmEnableInstructionCache) EL1_OR_EL2_OR_EL3(x1) 1: mrs x0, sctlr_el1 // Get control register EL1 b 4f @@ -250,7 +207,7 @@ ASM_PFX(ArmEnableInstructionCache): ret -ASM_PFX(ArmDisableInstructionCache): +ASM_FUNC(ArmDisableInstructionCache) EL1_OR_EL2_OR_EL3(x1) 1: mrs x0, sctlr_el1 // Get control register EL1 b 4f @@ -269,7 +226,7 @@ ASM_PFX(ArmDisableInstructionCache): ret -ASM_PFX(ArmEnableAlignmentCheck): +ASM_FUNC(ArmEnableAlignmentCheck) EL1_OR_EL2(x1) 1: mrs x0, sctlr_el1 // Get control register EL1 b 3f @@ -284,7 +241,7 @@ ASM_PFX(ArmEnableAlignmentCheck): ret -ASM_PFX(ArmDisableAlignmentCheck): +ASM_FUNC(ArmDisableAlignmentCheck) EL1_OR_EL2_OR_EL3(x1) 1: mrs x0, sctlr_el1 // Get control register EL1 b 4f @@ -304,16 +261,16 @@ ASM_PFX(ArmDisableAlignmentCheck): // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now -ASM_PFX(ArmEnableBranchPrediction): +ASM_FUNC(ArmEnableBranchPrediction) ret // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now. -ASM_PFX(ArmDisableBranchPrediction): +ASM_FUNC(ArmDisableBranchPrediction) ret -ASM_PFX(AArch64AllDataCachesOperation): +ASM_FUNC(AArch64AllDataCachesOperation) // We can use regs 0-7 and 9-15 without having to save/restore. // Save our link register on the stack. - The stack must always be quad-word aligned str x30, [sp, #-16]! @@ -371,22 +328,22 @@ L_Finished: ret -ASM_PFX(ArmDataMemoryBarrier): +ASM_FUNC(ArmDataMemoryBarrier) dmb sy ret -ASM_PFX(ArmDataSynchronizationBarrier): +ASM_FUNC(ArmDataSynchronizationBarrier) dsb sy ret -ASM_PFX(ArmInstructionSynchronizationBarrier): +ASM_FUNC(ArmInstructionSynchronizationBarrier) isb ret -ASM_PFX(ArmWriteVBar): +ASM_FUNC(ArmWriteVBar) EL1_OR_EL2_OR_EL3(x1) 1: msr vbar_el1, x0 // Set the Address of the EL1 Vector Table in the VBAR register b 4f @@ -396,7 +353,7 @@ ASM_PFX(ArmWriteVBar): 4: isb ret -ASM_PFX(ArmReadVBar): +ASM_FUNC(ArmReadVBar) EL1_OR_EL2_OR_EL3(x1) 1: mrs x0, vbar_el1 // Set the Address of the EL1 Vector Table in the VBAR register ret @@ -406,7 +363,7 @@ ASM_PFX(ArmReadVBar): ret -ASM_PFX(ArmEnableVFP): +ASM_FUNC(ArmEnableVFP) // Check whether floating-point is implemented in the processor. mov x1, x30 // Save LR bl ArmReadIdPfr0 // Read EL1 Processor Feature Register (PFR0) @@ -432,35 +389,35 @@ ASM_PFX(ArmEnableVFP): 4:ret -ASM_PFX(ArmCallWFI): +ASM_FUNC(ArmCallWFI) wfi ret -ASM_PFX(ArmReadMpidr): +ASM_FUNC(ArmReadMpidr) mrs x0, mpidr_el1 // read EL1 MPIDR ret // Keep old function names for C compatibilty for now. Change later? -ASM_PFX(ArmReadTpidrurw): +ASM_FUNC(ArmReadTpidrurw) mrs x0, tpidr_el0 // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0) ret // Keep old function names for C compatibilty for now. Change later? -ASM_PFX(ArmWriteTpidrurw): +ASM_FUNC(ArmWriteTpidrurw) msr tpidr_el0, x0 // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0) ret // Arch timers are mandatory on AArch64 -ASM_PFX(ArmIsArchTimerImplemented): +ASM_FUNC(ArmIsArchTimerImplemented) mov x0, #1 ret -ASM_PFX(ArmReadIdPfr0): +ASM_FUNC(ArmReadIdPfr0) mrs x0, id_aa64pfr0_el1 // Read ID_AA64PFR0 Register ret @@ -469,22 +426,22 @@ ASM_PFX(ArmReadIdPfr0): // A: used to setup arch timer. Check if we have security extensions, permissions to set stuff. // See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c // Not defined yet, but stick in here for now, should read all zeros. -ASM_PFX(ArmReadIdPfr1): +ASM_FUNC(ArmReadIdPfr1) mrs x0, id_aa64pfr1_el1 // Read ID_PFR1 Register ret // VOID ArmWriteHcr(UINTN Hcr) -ASM_PFX(ArmWriteHcr): +ASM_FUNC(ArmWriteHcr) msr hcr_el2, x0 // Write the passed HCR value ret // UINTN ArmReadHcr(VOID) -ASM_PFX(ArmReadHcr): +ASM_FUNC(ArmReadHcr) mrs x0, hcr_el2 ret // UINTN ArmReadCurrentEL(VOID) -ASM_PFX(ArmReadCurrentEL): +ASM_FUNC(ArmReadCurrentEL) mrs x0, CurrentEL ret diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S index 341bbce76c..221dfc499a 100644 --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S @@ -2,6 +2,7 @@ # # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -15,24 +16,6 @@ #include -.text -.align 3 - -GCC_ASM_EXPORT (ArmIsMpCore) -GCC_ASM_EXPORT (ArmEnableAsynchronousAbort) -GCC_ASM_EXPORT (ArmDisableAsynchronousAbort) -GCC_ASM_EXPORT (ArmEnableIrq) -GCC_ASM_EXPORT (ArmDisableIrq) -GCC_ASM_EXPORT (ArmEnableFiq) -GCC_ASM_EXPORT (ArmDisableFiq) -GCC_ASM_EXPORT (ArmEnableInterrupts) -GCC_ASM_EXPORT (ArmDisableInterrupts) -GCC_ASM_EXPORT (ArmDisableAllExceptions) -GCC_ASM_EXPORT (ReadCCSIDR) -GCC_ASM_EXPORT (ReadCLIDR) - -#------------------------------------------------------------------------------ - .set MPIDR_U_BIT, (30) .set MPIDR_U_MASK, (1 << MPIDR_U_BIT) @@ -45,7 +28,7 @@ GCC_ASM_EXPORT (ReadCLIDR) .set DAIF_WR_ALL, (DAIF_WR_DEBUG_BIT | DAIF_WR_ABORT_BIT | DAIF_WR_INT_BITS) -ASM_PFX(ArmIsMpCore): +ASM_FUNC(ArmIsMpCore) mrs x0, mpidr_el1 // Read EL1 Mutliprocessor Affinty Reg (MPIDR) and x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system lsr x0, x0, #MPIDR_U_BIT @@ -53,55 +36,55 @@ ASM_PFX(ArmIsMpCore): ret -ASM_PFX(ArmEnableAsynchronousAbort): +ASM_FUNC(ArmEnableAsynchronousAbort) msr daifclr, #DAIF_WR_ABORT_BIT isb ret -ASM_PFX(ArmDisableAsynchronousAbort): +ASM_FUNC(ArmDisableAsynchronousAbort) msr daifset, #DAIF_WR_ABORT_BIT isb ret -ASM_PFX(ArmEnableIrq): +ASM_FUNC(ArmEnableIrq) msr daifclr, #DAIF_WR_IRQ_BIT isb ret -ASM_PFX(ArmDisableIrq): +ASM_FUNC(ArmDisableIrq) msr daifset, #DAIF_WR_IRQ_BIT isb ret -ASM_PFX(ArmEnableFiq): +ASM_FUNC(ArmEnableFiq) msr daifclr, #DAIF_WR_FIQ_BIT isb ret -ASM_PFX(ArmDisableFiq): +ASM_FUNC(ArmDisableFiq) msr daifset, #DAIF_WR_FIQ_BIT isb ret -ASM_PFX(ArmEnableInterrupts): +ASM_FUNC(ArmEnableInterrupts) msr daifclr, #DAIF_WR_INT_BITS isb ret -ASM_PFX(ArmDisableInterrupts): +ASM_FUNC(ArmDisableInterrupts) msr daifset, #DAIF_WR_INT_BITS isb ret -ASM_PFX(ArmDisableAllExceptions): +ASM_FUNC(ArmDisableAllExceptions) msr daifset, #DAIF_WR_ALL isb ret @@ -111,7 +94,7 @@ ASM_PFX(ArmDisableAllExceptions): // ReadCCSIDR ( // IN UINT32 CSSELR // ) -ASM_PFX(ReadCCSIDR): +ASM_FUNC(ReadCCSIDR) msr csselr_el1, x0 // Write Cache Size Selection Register (CSSELR) isb mrs x0, ccsidr_el1 // Read current Cache Size ID Register (CCSIDR) @@ -122,7 +105,7 @@ ASM_PFX(ReadCCSIDR): // ReadCLIDR ( // IN UINT32 CSSELR // ) -ASM_PFX(ReadCLIDR): +ASM_FUNC(ReadCLIDR) mrs x0, clidr_el1 // Read Cache Level ID Register ret diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S index 1bd00d1b99..3939bbc6b6 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S @@ -2,6 +2,7 @@ # # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -15,27 +16,7 @@ #include -.text -.align 2 - -GCC_ASM_EXPORT(ArmIsMpCore) -GCC_ASM_EXPORT(ArmHasMpExtensions) -GCC_ASM_EXPORT(ArmEnableAsynchronousAbort) -GCC_ASM_EXPORT(ArmDisableAsynchronousAbort) -GCC_ASM_EXPORT(ArmEnableIrq) -GCC_ASM_EXPORT(ArmDisableIrq) -GCC_ASM_EXPORT(ArmEnableFiq) -GCC_ASM_EXPORT(ArmDisableFiq) -GCC_ASM_EXPORT(ArmEnableInterrupts) -GCC_ASM_EXPORT(ArmDisableInterrupts) -GCC_ASM_EXPORT(ReadCCSIDR) -GCC_ASM_EXPORT(ReadCLIDR) -GCC_ASM_EXPORT(ArmReadNsacr) -GCC_ASM_EXPORT(ArmWriteNsacr) - -#------------------------------------------------------------------------------ - -ASM_PFX(ArmIsMpCore): +ASM_FUNC(ArmIsMpCore) mrc p15,0,R0,c0,c0,5 // Get Multiprocessing extension (bit31) & U bit (bit30) and R0, R0, #0xC0000000 @@ -45,42 +26,42 @@ ASM_PFX(ArmIsMpCore): movne R0, #0 bx LR -ASM_PFX(ArmEnableAsynchronousAbort): +ASM_FUNC(ArmEnableAsynchronousAbort) cpsie a isb bx LR -ASM_PFX(ArmDisableAsynchronousAbort): +ASM_FUNC(ArmDisableAsynchronousAbort) cpsid a isb bx LR -ASM_PFX(ArmEnableIrq): +ASM_FUNC(ArmEnableIrq) cpsie i isb bx LR -ASM_PFX(ArmDisableIrq): +ASM_FUNC(ArmDisableIrq) cpsid i isb bx LR -ASM_PFX(ArmEnableFiq): +ASM_FUNC(ArmEnableFiq) cpsie f isb bx LR -ASM_PFX(ArmDisableFiq): +ASM_FUNC(ArmDisableFiq) cpsid f isb bx LR -ASM_PFX(ArmEnableInterrupts): +ASM_FUNC(ArmEnableInterrupts) cpsie if isb bx LR -ASM_PFX(ArmDisableInterrupts): +ASM_FUNC(ArmDisableInterrupts) cpsid if isb bx LR @@ -89,7 +70,7 @@ ASM_PFX(ArmDisableInterrupts): // ReadCCSIDR ( // IN UINT32 CSSELR // ) -ASM_PFX(ReadCCSIDR): +ASM_FUNC(ReadCCSIDR) mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR) isb mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR) @@ -99,15 +80,15 @@ ASM_PFX(ReadCCSIDR): // ReadCLIDR ( // IN UINT32 CSSELR // ) -ASM_PFX(ReadCLIDR): +ASM_FUNC(ReadCLIDR) mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register bx lr -ASM_PFX(ArmReadNsacr): +ASM_FUNC(ArmReadNsacr) mrc p15, 0, r0, c1, c1, 2 bx lr -ASM_PFX(ArmWriteNsacr): +ASM_FUNC(ArmWriteNsacr) mcr p15, 0, r0, c1, c1, 2 bx lr diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S index ec4ede5250..9a7794f0ad 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S @@ -1,6 +1,7 @@ #------------------------------------------------------------------------------ # # Copyright (c) 2011, ARM Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -12,107 +13,85 @@ # #------------------------------------------------------------------------------ -.text -.align 2 +#include -GCC_ASM_EXPORT (ArmReadCntFrq) -GCC_ASM_EXPORT (ArmWriteCntFrq) -GCC_ASM_EXPORT (ArmReadCntPct) -GCC_ASM_EXPORT (ArmReadCntkCtl) -GCC_ASM_EXPORT (ArmWriteCntkCtl) -GCC_ASM_EXPORT (ArmReadCntpTval) -GCC_ASM_EXPORT (ArmWriteCntpTval) -GCC_ASM_EXPORT (ArmReadCntpCtl) -GCC_ASM_EXPORT (ArmWriteCntpCtl) -GCC_ASM_EXPORT (ArmReadCntvTval) -GCC_ASM_EXPORT (ArmWriteCntvTval) -GCC_ASM_EXPORT (ArmReadCntvCtl) -GCC_ASM_EXPORT (ArmWriteCntvCtl) -GCC_ASM_EXPORT (ArmReadCntvCt) -GCC_ASM_EXPORT (ArmReadCntpCval) -GCC_ASM_EXPORT (ArmWriteCntpCval) -GCC_ASM_EXPORT (ArmReadCntvCval) -GCC_ASM_EXPORT (ArmWriteCntvCval) -GCC_ASM_EXPORT (ArmReadCntvOff) -GCC_ASM_EXPORT (ArmWriteCntvOff) - -ASM_PFX(ArmReadCntFrq): +ASM_FUNC(ArmReadCntFrq) mrc p15, 0, r0, c14, c0, 0 @ Read CNTFRQ bx lr -ASM_PFX(ArmWriteCntFrq): +ASM_FUNC(ArmWriteCntFrq) mcr p15, 0, r0, c14, c0, 0 @ Write to CNTFRQ bx lr -ASM_PFX(ArmReadCntPct): +ASM_FUNC(ArmReadCntPct) mrrc p15, 0, r0, r1, c14 @ Read CNTPT (Physical counter register) bx lr -ASM_PFX(ArmReadCntkCtl): +ASM_FUNC(ArmReadCntkCtl) mrc p15, 0, r0, c14, c1, 0 @ Read CNTK_CTL (Timer PL1 Control Register) bx lr -ASM_PFX(ArmWriteCntkCtl): +ASM_FUNC(ArmWriteCntkCtl) mcr p15, 0, r0, c14, c1, 0 @ Write to CNTK_CTL (Timer PL1 Control Register) bx lr -ASM_PFX(ArmReadCntpTval): +ASM_FUNC(ArmReadCntpTval) mrc p15, 0, r0, c14, c2, 0 @ Read CNTP_TVAL (PL1 physical timer value register) bx lr -ASM_PFX(ArmWriteCntpTval): +ASM_FUNC(ArmWriteCntpTval) mcr p15, 0, r0, c14, c2, 0 @ Write to CNTP_TVAL (PL1 physical timer value register) bx lr -ASM_PFX(ArmReadCntpCtl): +ASM_FUNC(ArmReadCntpCtl) mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register) bx lr -ASM_PFX(ArmWriteCntpCtl): +ASM_FUNC(ArmWriteCntpCtl) mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register) bx lr -ASM_PFX(ArmReadCntvTval): +ASM_FUNC(ArmReadCntvTval) mrc p15, 0, r0, c14, c3, 0 @ Read CNTV_TVAL (Virtual Timer Value register) bx lr -ASM_PFX(ArmWriteCntvTval): +ASM_FUNC(ArmWriteCntvTval) mcr p15, 0, r0, c14, c3, 0 @ Write to CNTV_TVAL (Virtual Timer Value register) bx lr -ASM_PFX(ArmReadCntvCtl): +ASM_FUNC(ArmReadCntvCtl) mrc p15, 0, r0, c14, c3, 1 @ Read CNTV_CTL (Virtual Timer Control Register) bx lr -ASM_PFX(ArmWriteCntvCtl): +ASM_FUNC(ArmWriteCntvCtl) mcr p15, 0, r0, c14, c3, 1 @ Write to CNTV_CTL (Virtual Timer Control Register) bx lr -ASM_PFX(ArmReadCntvCt): +ASM_FUNC(ArmReadCntvCt) mrrc p15, 1, r0, r1, c14 @ Read CNTVCT (Virtual Count Register) bx lr -ASM_PFX(ArmReadCntpCval): +ASM_FUNC(ArmReadCntpCval) mrrc p15, 2, r0, r1, c14 @ Read CNTP_CTVAL (Physical Timer Compare Value Register) bx lr -ASM_PFX(ArmWriteCntpCval): +ASM_FUNC(ArmWriteCntpCval) mcrr p15, 2, r0, r1, c14 @ Write to CNTP_CTVAL (Physical Timer Compare Value Register) bx lr -ASM_PFX(ArmReadCntvCval): +ASM_FUNC(ArmReadCntvCval) mrrc p15, 3, r0, r1, c14 @ Read CNTV_CTVAL (Virtual Timer Compare Value Register) bx lr -ASM_PFX(ArmWriteCntvCval): +ASM_FUNC(ArmWriteCntvCval) mcrr p15, 3, r0, r1, c14 @ write to CNTV_CTVAL (Virtual Timer Compare Value Register) bx lr -ASM_PFX(ArmReadCntvOff): +ASM_FUNC(ArmReadCntvOff) mrrc p15, 4, r0, r1, c14 @ Read CNTVOFF (virtual Offset register) bx lr -ASM_PFX(ArmWriteCntvOff): +ASM_FUNC(ArmWriteCntvOff) mcrr p15, 4, r0, r1, c14 @ Write to CNTVOFF (Virtual Offset register) bx lr diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S index 47a4aa5e0d..281499b46c 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S @@ -2,6 +2,7 @@ # # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -13,45 +14,7 @@ # #------------------------------------------------------------------------------ -.text -.align 2 - -GCC_ASM_EXPORT (ArmInvalidateInstructionCache) -GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA) -GCC_ASM_EXPORT (ArmInvalidateInstructionCacheEntryToPoUByMVA) -GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA) -GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA) -GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA) -GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay) -GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay) -GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay) -GCC_ASM_EXPORT (ArmEnableMmu) -GCC_ASM_EXPORT (ArmDisableMmu) -GCC_ASM_EXPORT (ArmDisableCachesAndMmu) -GCC_ASM_EXPORT (ArmMmuEnabled) -GCC_ASM_EXPORT (ArmEnableDataCache) -GCC_ASM_EXPORT (ArmDisableDataCache) -GCC_ASM_EXPORT (ArmEnableInstructionCache) -GCC_ASM_EXPORT (ArmDisableInstructionCache) -GCC_ASM_EXPORT (ArmEnableSWPInstruction) -GCC_ASM_EXPORT (ArmEnableBranchPrediction) -GCC_ASM_EXPORT (ArmDisableBranchPrediction) -GCC_ASM_EXPORT (ArmSetLowVectors) -GCC_ASM_EXPORT (ArmSetHighVectors) -GCC_ASM_EXPORT (ArmV7AllDataCachesOperation) -GCC_ASM_EXPORT (ArmDataMemoryBarrier) -GCC_ASM_EXPORT (ArmDataSynchronizationBarrier) -GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier) -GCC_ASM_EXPORT (ArmReadVBar) -GCC_ASM_EXPORT (ArmWriteVBar) -GCC_ASM_EXPORT (ArmEnableVFP) -GCC_ASM_EXPORT (ArmCallWFI) -GCC_ASM_EXPORT (ArmReadCbar) -GCC_ASM_EXPORT (ArmReadMpidr) -GCC_ASM_EXPORT (ArmReadTpidrurw) -GCC_ASM_EXPORT (ArmWriteTpidrurw) -GCC_ASM_EXPORT (ArmIsArchTimerImplemented) -GCC_ASM_EXPORT (ArmReadIdPfr1) +#include .set DC_ON, (0x1<<2) .set IC_ON, (0x1<<12) @@ -61,50 +24,50 @@ GCC_ASM_EXPORT (ArmReadIdPfr1) .set CTRL_I_BIT, (1 << 12) -ASM_PFX(ArmInvalidateDataCacheEntryByMVA): +ASM_FUNC(ArmInvalidateDataCacheEntryByMVA) mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line bx lr -ASM_PFX(ArmCleanDataCacheEntryByMVA): +ASM_FUNC(ArmCleanDataCacheEntryByMVA) mcr p15, 0, r0, c7, c10, 1 @clean single data cache line bx lr -ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA): +ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA) mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU bx lr -ASM_PFX(ArmInvalidateInstructionCacheEntryToPoUByMVA): +ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA) mcr p15, 0, r0, c7, c5, 1 @Invalidate single instruction cache line to PoU mcr p15, 0, r0, c7, c5, 7 @Invalidate branch predictor bx lr -ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): +ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA) mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line bx lr -ASM_PFX(ArmInvalidateDataCacheEntryBySetWay): +ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay) mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line bx lr -ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay): +ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay) mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line bx lr -ASM_PFX(ArmCleanDataCacheEntryBySetWay): +ASM_FUNC(ArmCleanDataCacheEntryBySetWay) mcr p15, 0, r0, c7, c10, 2 @ Clean this line bx lr -ASM_PFX(ArmInvalidateInstructionCache): +ASM_FUNC(ArmInvalidateInstructionCache) mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache dsb isb bx LR -ASM_PFX(ArmEnableMmu): +ASM_FUNC(ArmEnableMmu) mrc p15,0,R0,c1,c0,0 orr R0,R0,#1 mcr p15,0,R0,c1,c0,0 @@ -113,7 +76,7 @@ ASM_PFX(ArmEnableMmu): bx LR -ASM_PFX(ArmDisableMmu): +ASM_FUNC(ArmDisableMmu) mrc p15,0,R0,c1,c0,0 bic R0,R0,#1 mcr p15,0,R0,c1,c0,0 @Disable MMU @@ -124,7 +87,7 @@ ASM_PFX(ArmDisableMmu): isb bx LR -ASM_PFX(ArmDisableCachesAndMmu): +ASM_FUNC(ArmDisableCachesAndMmu) mrc p15, 0, r0, c1, c0, 0 @ Get control register bic r0, r0, #CTRL_M_BIT @ Disable MMU bic r0, r0, #CTRL_C_BIT @ Disable D Cache @@ -134,12 +97,12 @@ ASM_PFX(ArmDisableCachesAndMmu): isb bx LR -ASM_PFX(ArmMmuEnabled): +ASM_FUNC(ArmMmuEnabled) mrc p15,0,R0,c1,c0,0 and R0,R0,#1 bx LR -ASM_PFX(ArmEnableDataCache): +ASM_FUNC(ArmEnableDataCache) ldr R1,=DC_ON mrc p15,0,R0,c1,c0,0 @Read control register configuration data orr R0,R0,R1 @Set C bit @@ -148,7 +111,7 @@ ASM_PFX(ArmEnableDataCache): isb bx LR -ASM_PFX(ArmDisableDataCache): +ASM_FUNC(ArmDisableDataCache) ldr R1,=DC_ON mrc p15,0,R0,c1,c0,0 @Read control register configuration data bic R0,R0,R1 @Clear C bit @@ -157,7 +120,7 @@ ASM_PFX(ArmDisableDataCache): isb bx LR -ASM_PFX(ArmEnableInstructionCache): +ASM_FUNC(ArmEnableInstructionCache) ldr R1,=IC_ON mrc p15,0,R0,c1,c0,0 @Read control register configuration data orr R0,R0,R1 @Set I bit @@ -166,7 +129,7 @@ ASM_PFX(ArmEnableInstructionCache): isb bx LR -ASM_PFX(ArmDisableInstructionCache): +ASM_FUNC(ArmDisableInstructionCache) ldr R1,=IC_ON mrc p15,0,R0,c1,c0,0 @Read control register configuration data bic R0,R0,R1 @Clear I bit. @@ -175,14 +138,14 @@ ASM_PFX(ArmDisableInstructionCache): isb bx LR -ASM_PFX(ArmEnableSWPInstruction): +ASM_FUNC(ArmEnableSWPInstruction) mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #0x00000400 mcr p15, 0, r0, c1, c0, 0 isb bx LR -ASM_PFX(ArmEnableBranchPrediction): +ASM_FUNC(ArmEnableBranchPrediction) mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #0x00000800 mcr p15, 0, r0, c1, c0, 0 @@ -190,7 +153,7 @@ ASM_PFX(ArmEnableBranchPrediction): isb bx LR -ASM_PFX(ArmDisableBranchPrediction): +ASM_FUNC(ArmDisableBranchPrediction) mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00000800 mcr p15, 0, r0, c1, c0, 0 @@ -198,21 +161,21 @@ ASM_PFX(ArmDisableBranchPrediction): isb bx LR -ASM_PFX(ArmSetLowVectors): +ASM_FUNC(ArmSetLowVectors) mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) bic r0, r0, #0x00002000 @ clear V bit mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) isb bx LR -ASM_PFX(ArmSetHighVectors): +ASM_FUNC(ArmSetHighVectors) mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) orr r0, r0, #0x00002000 @ Set V bit mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) isb bx LR -ASM_PFX(ArmV7AllDataCachesOperation): +ASM_FUNC(ArmV7AllDataCachesOperation) stmfd SP!,{r4-r12, LR} mov R1, R0 @ Save Function call in R1 mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR @@ -265,24 +228,24 @@ L_Finished: ldmfd SP!, {r4-r12, lr} bx LR -ASM_PFX(ArmDataMemoryBarrier): +ASM_FUNC(ArmDataMemoryBarrier) dmb bx LR -ASM_PFX(ArmDataSynchronizationBarrier): +ASM_FUNC(ArmDataSynchronizationBarrier) dsb bx LR -ASM_PFX(ArmInstructionSynchronizationBarrier): +ASM_FUNC(ArmInstructionSynchronizationBarrier) isb bx LR -ASM_PFX(ArmReadVBar): +ASM_FUNC(ArmReadVBar) # Set the Address of the Vector Table in the VBAR register mrc p15, 0, r0, c12, c0, 0 bx lr -ASM_PFX(ArmWriteVBar): +ASM_FUNC(ArmWriteVBar) # Set the Address of the Vector Table in the VBAR register mcr p15, 0, r0, c12, c0, 0 # Ensure the SCTLR.V bit is clear @@ -292,7 +255,7 @@ ASM_PFX(ArmWriteVBar): isb bx lr -ASM_PFX(ArmEnableVFP): +ASM_FUNC(ArmEnableVFP) # Read CPACR (Coprocessor Access Control Register) mrc p15, 0, r0, c1, c0, 2 # Enable VPF access (Full Access to CP10, CP11) (V* instructions) @@ -309,33 +272,33 @@ ASM_PFX(ArmEnableVFP): #endif bx lr -ASM_PFX(ArmCallWFI): +ASM_FUNC(ArmCallWFI) wfi bx lr #Note: Return 0 in Uniprocessor implementation -ASM_PFX(ArmReadCbar): +ASM_FUNC(ArmReadCbar) mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register bx lr -ASM_PFX(ArmReadMpidr): +ASM_FUNC(ArmReadMpidr) mrc p15, 0, r0, c0, c0, 5 @ read MPIDR bx lr -ASM_PFX(ArmReadTpidrurw): +ASM_FUNC(ArmReadTpidrurw) mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW bx lr -ASM_PFX(ArmWriteTpidrurw): +ASM_FUNC(ArmWriteTpidrurw) mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW bx lr -ASM_PFX(ArmIsArchTimerImplemented): +ASM_FUNC(ArmIsArchTimerImplemented) mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 and r0, r0, #0x000F0000 bx lr -ASM_PFX(ArmReadIdPfr1): +ASM_FUNC(ArmReadIdPfr1) mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register bx lr diff --git a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S index c9f3bd1e88..9d3dd66b10 100644 --- a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S @@ -2,6 +2,7 @@ # # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -15,76 +16,48 @@ #include -.text -.align 3 -GCC_ASM_EXPORT (ArmReadMidr) -GCC_ASM_EXPORT (ArmCacheInfo) -GCC_ASM_EXPORT (ArmGetInterruptState) -GCC_ASM_EXPORT (ArmGetFiqState) -GCC_ASM_EXPORT (ArmGetTTBR0BaseAddress) -GCC_ASM_EXPORT (ArmSetTTBR0) -GCC_ASM_EXPORT (ArmGetTCR) -GCC_ASM_EXPORT (ArmSetTCR) -GCC_ASM_EXPORT (ArmGetMAIR) -GCC_ASM_EXPORT (ArmSetMAIR) -GCC_ASM_EXPORT (ArmWriteCpacr) -GCC_ASM_EXPORT (ArmWriteAuxCr) -GCC_ASM_EXPORT (ArmReadAuxCr) -GCC_ASM_EXPORT (ArmInvalidateTlb) -GCC_ASM_EXPORT (ArmUpdateTranslationTableEntry) -GCC_ASM_EXPORT (ArmWriteCptr) -GCC_ASM_EXPORT (ArmWriteScr) -GCC_ASM_EXPORT (ArmWriteMVBar) -GCC_ASM_EXPORT (ArmCallWFE) -GCC_ASM_EXPORT (ArmCallSEV) -GCC_ASM_EXPORT (ArmReadCpuActlr) -GCC_ASM_EXPORT (ArmWriteCpuActlr) -GCC_ASM_EXPORT (ArmReadSctlr) - -#------------------------------------------------------------------------------ - .set DAIF_RD_FIQ_BIT, (1 << 6) .set DAIF_RD_IRQ_BIT, (1 << 7) -ASM_PFX(ArmReadMidr): +ASM_FUNC(ArmReadMidr) mrs x0, midr_el1 // Read from Main ID Register (MIDR) ret -ASM_PFX(ArmCacheInfo): +ASM_FUNC(ArmCacheInfo) mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR) ret -ASM_PFX(ArmGetInterruptState): +ASM_FUNC(ArmGetInterruptState) mrs x0, daif tst w0, #DAIF_RD_IRQ_BIT // Check if IRQ is enabled. Enabled if 0 (Z=1) cset w0, eq // if Z=1 return 1, else 0 ret -ASM_PFX(ArmGetFiqState): +ASM_FUNC(ArmGetFiqState) mrs x0, daif tst w0, #DAIF_RD_FIQ_BIT // Check if FIQ is enabled. Enabled if 0 (Z=1) cset w0, eq // if Z=1 return 1, else 0 ret -ASM_PFX(ArmWriteCpacr): +ASM_FUNC(ArmWriteCpacr) msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR) ret -ASM_PFX(ArmWriteAuxCr): +ASM_FUNC(ArmWriteAuxCr) EL1_OR_EL2(x1) 1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3 ret 2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3 ret -ASM_PFX(ArmReadAuxCr): +ASM_FUNC(ArmReadAuxCr) EL1_OR_EL2(x1) 1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3 ret 2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3 ret -ASM_PFX(ArmSetTTBR0): +ASM_FUNC(ArmSetTTBR0) EL1_OR_EL2_OR_EL3(x1) 1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0) b 4f @@ -94,17 +67,16 @@ ASM_PFX(ArmSetTTBR0): 4:isb ret -ASM_PFX(ArmGetTTBR0BaseAddress): +ASM_FUNC(ArmGetTTBR0BaseAddress) EL1_OR_EL2(x1) 1:mrs x0, ttbr0_el1 b 3f 2:mrs x0, ttbr0_el2 -3:LoadConstantToReg(0xFFFFFFFFFFFF, x1) /* Look at bottom 48 bits */ - and x0, x0, x1 +3:and x0, x0, 0xFFFFFFFFFFFF /* Look at bottom 48 bits */ isb ret -ASM_PFX(ArmGetTCR): +ASM_FUNC(ArmGetTCR) EL1_OR_EL2_OR_EL3(x1) 1:mrs x0, tcr_el1 b 4f @@ -114,7 +86,7 @@ ASM_PFX(ArmGetTCR): 4:isb ret -ASM_PFX(ArmSetTCR): +ASM_FUNC(ArmSetTCR) EL1_OR_EL2_OR_EL3(x1) 1:msr tcr_el1, x0 b 4f @@ -124,7 +96,7 @@ ASM_PFX(ArmSetTCR): 4:isb ret -ASM_PFX(ArmGetMAIR): +ASM_FUNC(ArmGetMAIR) EL1_OR_EL2_OR_EL3(x1) 1:mrs x0, mair_el1 b 4f @@ -134,7 +106,7 @@ ASM_PFX(ArmGetMAIR): 4:isb ret -ASM_PFX(ArmSetMAIR): +ASM_FUNC(ArmSetMAIR) EL1_OR_EL2_OR_EL3(x1) 1:msr mair_el1, x0 b 4f @@ -151,7 +123,7 @@ ASM_PFX(ArmSetMAIR): // IN VOID *TranslationTableEntry // X0 // IN VOID *MVA // X1 // ); -ASM_PFX(ArmUpdateTranslationTableEntry): +ASM_FUNC(ArmUpdateTranslationTableEntry) dc civac, x0 // Clean and invalidate data line dsb sy EL1_OR_EL2_OR_EL3(x0) @@ -164,7 +136,7 @@ ASM_PFX(ArmUpdateTranslationTableEntry): isb ret -ASM_PFX(ArmInvalidateTlb): +ASM_FUNC(ArmInvalidateTlb) EL1_OR_EL2_OR_EL3(x0) 1: tlbi vmalle1 b 4f @@ -175,38 +147,38 @@ ASM_PFX(ArmInvalidateTlb): isb ret -ASM_PFX(ArmWriteCptr): +ASM_FUNC(ArmWriteCptr) msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR) ret -ASM_PFX(ArmWriteScr): +ASM_FUNC(ArmWriteScr) msr scr_el3, x0 // Secure configuration register EL3 isb ret -ASM_PFX(ArmWriteMVBar): +ASM_FUNC(ArmWriteMVBar) msr vbar_el3, x0 // Exception Vector Base address for Monitor on EL3 ret -ASM_PFX(ArmCallWFE): +ASM_FUNC(ArmCallWFE) wfe ret -ASM_PFX(ArmCallSEV): +ASM_FUNC(ArmCallSEV) sev ret -ASM_PFX(ArmReadCpuActlr): +ASM_FUNC(ArmReadCpuActlr) mrs x0, S3_1_c15_c2_0 ret -ASM_PFX(ArmWriteCpuActlr): +ASM_FUNC(ArmWriteCpuActlr) msr S3_1_c15_c2_0, x0 dsb sy isb ret -ASM_PFX(ArmReadSctlr): +ASM_FUNC(ArmReadSctlr) EL1_OR_EL2_OR_EL3(x1) 1:mrs x0, sctlr_el1 ret diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S index 5d1194e7e2..a0b5ed5002 100644 --- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S @@ -2,6 +2,7 @@ # # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -15,65 +16,33 @@ #include -.text -.align 2 -GCC_ASM_EXPORT(ArmReadMidr) -GCC_ASM_EXPORT(ArmCacheInfo) -GCC_ASM_EXPORT(ArmGetInterruptState) -GCC_ASM_EXPORT(ArmGetFiqState) -GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress) -GCC_ASM_EXPORT(ArmSetTTBR0) -GCC_ASM_EXPORT(ArmSetTTBCR) -GCC_ASM_EXPORT(ArmSetDomainAccessControl) -GCC_ASM_EXPORT(CPSRMaskInsert) -GCC_ASM_EXPORT(CPSRRead) -GCC_ASM_EXPORT(ArmReadCpacr) -GCC_ASM_EXPORT(ArmWriteCpacr) -GCC_ASM_EXPORT(ArmWriteAuxCr) -GCC_ASM_EXPORT(ArmReadAuxCr) -GCC_ASM_EXPORT(ArmInvalidateTlb) -GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry) -GCC_ASM_EXPORT(ArmReadScr) -GCC_ASM_EXPORT(ArmWriteScr) -GCC_ASM_EXPORT(ArmReadMVBar) -GCC_ASM_EXPORT(ArmWriteMVBar) -GCC_ASM_EXPORT(ArmReadHVBar) -GCC_ASM_EXPORT(ArmWriteHVBar) -GCC_ASM_EXPORT(ArmCallWFE) -GCC_ASM_EXPORT(ArmCallSEV) -GCC_ASM_EXPORT(ArmReadSctlr) -GCC_ASM_EXPORT(ArmReadCpuActlr) -GCC_ASM_EXPORT(ArmWriteCpuActlr) - -#------------------------------------------------------------------------------ - -ASM_PFX(ArmReadMidr): +ASM_FUNC(ArmReadMidr) mrc p15,0,R0,c0,c0,0 bx LR -ASM_PFX(ArmCacheInfo): +ASM_FUNC(ArmCacheInfo) mrc p15,0,R0,c0,c0,1 bx LR -ASM_PFX(ArmGetInterruptState): +ASM_FUNC(ArmGetInterruptState) mrs R0,CPSR tst R0,#0x80 @Check if IRQ is enabled. moveq R0,#1 movne R0,#0 bx LR -ASM_PFX(ArmGetFiqState): +ASM_FUNC(ArmGetFiqState) mrs R0,CPSR tst R0,#0x40 @Check if FIQ is enabled. moveq R0,#1 movne R0,#0 bx LR -ASM_PFX(ArmSetDomainAccessControl): +ASM_FUNC(ArmSetDomainAccessControl) mcr p15,0,r0,c3,c0,0 bx lr -ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert +ASM_FUNC(CPSRMaskInsert) @ on entry, r0 is the mask and r1 is the field to insert stmfd sp!, {r4-r12, lr} @ save all the banked registers mov r3, sp @ copy the stack pointer into a non-banked register mrs r2, cpsr @ read the cpsr @@ -86,40 +55,40 @@ ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to in ldmfd sp!, {r4-r12, lr} @ restore registers bx lr @ return (hopefully thumb-safe!) -ASM_PFX(CPSRRead): +ASM_FUNC(CPSRRead) mrs r0, cpsr bx lr -ASM_PFX(ArmReadCpacr): +ASM_FUNC(ArmReadCpacr) mrc p15, 0, r0, c1, c0, 2 bx lr -ASM_PFX(ArmWriteCpacr): +ASM_FUNC(ArmWriteCpacr) mcr p15, 0, r0, c1, c0, 2 isb bx lr -ASM_PFX(ArmWriteAuxCr): +ASM_FUNC(ArmWriteAuxCr) mcr p15, 0, r0, c1, c0, 1 bx lr -ASM_PFX(ArmReadAuxCr): +ASM_FUNC(ArmReadAuxCr) mrc p15, 0, r0, c1, c0, 1 bx lr -ASM_PFX(ArmSetTTBR0): +ASM_FUNC(ArmSetTTBR0) mcr p15,0,r0,c2,c0,0 isb bx lr -ASM_PFX(ArmSetTTBCR): +ASM_FUNC(ArmSetTTBCR) mcr p15, 0, r0, c2, c0, 2 isb bx lr -ASM_PFX(ArmGetTTBR0BaseAddress): +ASM_FUNC(ArmGetTTBR0BaseAddress) mrc p15,0,r0,c2,c0,0 - LoadConstantToReg(0xFFFFC000, r1) + MOV32 (r1, 0xFFFFC000) and r0, r0, r1 isb bx lr @@ -130,7 +99,7 @@ ASM_PFX(ArmGetTTBR0BaseAddress): // IN VOID *TranslationTableEntry // R0 // IN VOID *MVA // R1 // ); -ASM_PFX(ArmUpdateTranslationTableEntry): +ASM_FUNC(ArmUpdateTranslationTableEntry) mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA dsb mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA @@ -139,7 +108,7 @@ ASM_PFX(ArmUpdateTranslationTableEntry): isb bx lr -ASM_PFX(ArmInvalidateTlb): +ASM_FUNC(ArmInvalidateTlb) mov r0,#0 mcr p15,0,r0,c8,c7,0 mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp @@ -147,48 +116,48 @@ ASM_PFX(ArmInvalidateTlb): isb bx lr -ASM_PFX(ArmReadScr): +ASM_FUNC(ArmReadScr) mrc p15, 0, r0, c1, c1, 0 bx lr -ASM_PFX(ArmWriteScr): +ASM_FUNC(ArmWriteScr) mcr p15, 0, r0, c1, c1, 0 isb bx lr -ASM_PFX(ArmReadHVBar): +ASM_FUNC(ArmReadHVBar) mrc p15, 4, r0, c12, c0, 0 bx lr -ASM_PFX(ArmWriteHVBar): +ASM_FUNC(ArmWriteHVBar) mcr p15, 4, r0, c12, c0, 0 bx lr -ASM_PFX(ArmReadMVBar): +ASM_FUNC(ArmReadMVBar) mrc p15, 0, r0, c12, c0, 1 bx lr -ASM_PFX(ArmWriteMVBar): +ASM_FUNC(ArmWriteMVBar) mcr p15, 0, r0, c12, c0, 1 bx lr -ASM_PFX(ArmCallWFE): +ASM_FUNC(ArmCallWFE) wfe bx lr -ASM_PFX(ArmCallSEV): +ASM_FUNC(ArmCallSEV) sev bx lr -ASM_PFX(ArmReadSctlr): +ASM_FUNC(ArmReadSctlr) mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) bx lr -ASM_PFX(ArmReadCpuActlr): +ASM_FUNC(ArmReadCpuActlr) mrc p15, 0, r0, c1, c0, 1 bx lr -ASM_PFX(ArmWriteCpuActlr): +ASM_FUNC(ArmWriteCpuActlr) mcr p15, 0, r0, c1, c0, 1 dsb isb diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm index 9b87b7f257..85b0feee20 100644 --- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm +++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm @@ -13,8 +13,6 @@ // //------------------------------------------------------------------------------ -#include - INCLUDE AsmMacroIoLib.inc @@ -92,7 +90,7 @@ RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress mrc p15,0,r0,c2,c0,0 - LoadConstantToReg(0xFFFFC000, r1) + MOV32 r1, 0xFFFFC000 and r0, r0, r1 isb bx lr