IntelFsp2Pkg: Apply uncrustify changes

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the IntelFsp2Pkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

IntelFsp2Pkg/FspSecCore/SecFsp.c

@@ -156,6 +156,7 @@ FspGlobalDataInit (
   if (FspmUpdDataPtr == NULL) {
     FspmUpdDataPtr = (VOID *)(PeiFspData->FspInfoHeader->ImageBase + PeiFspData->FspInfoHeader->CfgRegionOffset);
   }
+
   SetFspUpdDataPointer (FspmUpdDataPtr);
   SetFspMemoryInitUpdDataPointer (FspmUpdDataPtr);
   SetFspSiliconInitUpdDataPointer (NULL);
@@ -186,9 +187,12 @@ FspGlobalDataInit (
   for (Idx = 0; Idx < 8; Idx++) {
     ImageId[Idx] = PeiFspData->FspInfoHeader->ImageId[Idx];
   }
+
   ImageId[Idx] = 0;
 
-  DEBUG ((DEBUG_INFO | DEBUG_INIT, "\n============= FSP Spec v%d.%d Header Revision v%x (%a v%x.%x.%x.%x) =============\n", \
+  DEBUG ((
+    DEBUG_INFO | DEBUG_INIT,
+    "\n============= FSP Spec v%d.%d Header Revision v%x (%a v%x.%x.%x.%x) =============\n", \
     (PeiFspData->FspInfoHeader->SpecVersion >> 4) & 0xF, \
     PeiFspData->FspInfoHeader->SpecVersion & 0xF, \
     PeiFspData->FspInfoHeader->HeaderRevision, \
@@ -196,7 +200,8 @@ FspGlobalDataInit (
     (PeiFspData->FspInfoHeader->ImageRevision >> 24) & 0xFF, \
     (PeiFspData->FspInfoHeader->ImageRevision >> 16) & 0xFF, \
     (PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xFF, \
-         PeiFspData->FspInfoHeader->ImageRevision & 0xFF));
+    PeiFspData->FspInfoHeader->ImageRevision & 0xFF
+    ));
 }
 
 /**

IntelFsp2Pkg/FspSecCore/SecFsp.h

@@ -52,7 +52,6 @@ FspGlobalDataInit (
   IN UINT8                 ApiIdx
   );
 
-
 /**
 
   Adjust the FSP data pointers after the stack is migrated to memory.
@@ -65,7 +64,6 @@ FspDataPointerFixUp (
   IN UINT32  OffsetGap
   );
 
-
 /**
   This interface returns the base address of FSP binary.
 

IntelFsp2Pkg/FspSecCore/SecFspApiChk.c

@@ -7,7 +7,6 @@
 
 #include "SecFsp.h"
 
-
 /**
   This function check the FSP API calling condition.
 

IntelFsp2Pkg/FspSecCore/SecMain.c

@@ -121,6 +121,7 @@ SecStartup (
     for (Index = 0; Index < FixedPcdGet8 (PcdFspMaxInterruptSupported); Index++) {
       CopyMem ((VOID *)&IdtTableInStack.IdtTable[Index], (VOID *)&ExceptionHandler, sizeof (UINT64));
     }
+
     IdtSize = sizeof (IdtTableInStack.IdtTable);
   } else {
     IdtSize = IdtDescriptor.Limit + 1;
@@ -133,6 +134,7 @@ SecStartup (
       CopyMem ((VOID *)(UINTN)&IdtTableInStack.IdtTable, (VOID *)IdtDescriptor.Base, IdtSize);
     }
   }
+
   IdtDescriptor.Base  = (UINTN)&IdtTableInStack.IdtTable;
   IdtDescriptor.Limit = (UINT16)(IdtSize - 1);
 
@@ -231,7 +233,6 @@ SecTemporaryRamSupport (
   GetFspGlobalDataPointer ()->OnSeparateStack = 1;
 
   if (PcdGet8 (PcdFspHeapSizePercentage) == 0) {
-
     CurrentStack = AsmReadEsp ();
     FspStackBase = (UINTN)GetFspEntryStack ();
 
@@ -246,7 +247,6 @@ SecTemporaryRamSupport (
     // The old stack is copied at the end of the stack region because stack grows down.
     //
     NewStack = (VOID *)((UINTN)PermanentMemoryBase - StackSize);
-
   } else {
     HeapSize  = CopySize * PcdGet8 (PcdFspHeapSizePercentage) / 100;
     StackSize = CopySize - HeapSize;
@@ -256,8 +256,8 @@ SecTemporaryRamSupport (
 
     OldStack = (VOID *)((UINTN)TemporaryMemoryBase + HeapSize);
     NewStack = (VOID *)(UINTN)PermanentMemoryBase;
-
   }
+
   //
   // Migrate Heap
   //
@@ -268,7 +268,6 @@ SecTemporaryRamSupport (
   //
   CopyMem (NewStack, OldStack, StackSize);
 
-
   //
   // We need *not* fix the return address because currently,
   // The PeiCore is executed in flash.

IntelFsp2Pkg/FspSecCore/SecMain.h

@@ -8,7 +8,6 @@
 #ifndef _SEC_CORE_H_
 #define _SEC_CORE_H_
 
-
 #include <PiPei.h>
 #include <Ppi/TemporaryRamSupport.h>
 
@@ -81,7 +80,6 @@ SecTemporaryRamSupport (
   IN UINTN                   CopySize
   );
 
-
 /**
 
   Entry point to the C language phase of SEC. After the SEC assembly

IntelFsp2Pkg/Include/FspEas/FspApi.h

@@ -412,7 +412,6 @@ EFI_STATUS
   OUT VOID    **HobListPtr
   );
 
-
 /**
   This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary
   memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure
@@ -437,7 +436,6 @@ EFI_STATUS
   IN  VOID    *TempRamExitParamPtr
   );
 
-
 /**
   This FSP API is called after TempRamExit API.
   FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the

IntelFsp2Pkg/Include/Library/CacheAsRamLib.h

@@ -21,4 +21,3 @@ DisableCacheAsRam (
   );
 
 #endif
-

IntelFsp2Pkg/Include/Library/CacheLib.h

@@ -53,4 +53,3 @@ SetCacheAttributes (
   );
 
 #endif
-

IntelFsp2Pkg/Include/Library/FspCommonLib.h

@@ -282,7 +282,6 @@ GetPhaseStatusCode (
   VOID
   );
 
-
 /**
   This function sets FSP Phase StatusCode.
 
@@ -305,4 +304,5 @@ EFIAPI
 FspApiReturnStatusReset (
   IN UINT32  FspResetType
   );
+
 #endif

IntelFsp2Pkg/Include/Library/FspPlatformLib.h

@@ -32,7 +32,6 @@ FspGetSystemMemorySize (
   IN OUT UINT64  *HighMemoryLength
   );
 
-
 /**
   Set a new stack frame for the continuation function.
 

IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c

@@ -305,13 +305,16 @@ ProgramFixedMtrr (
 
   for (MsrNum = 0; MsrNum < V_EFI_FIXED_MTRR_NUMBER; MsrNum++) {
     if ((*Base >= mFixedMtrrTable[MsrNum].BaseAddress) &&
-        (*Base < (mFixedMtrrTable[MsrNum].BaseAddress + 8 * mFixedMtrrTable[MsrNum].Length))) {
+        (*Base < (mFixedMtrrTable[MsrNum].BaseAddress + 8 * mFixedMtrrTable[MsrNum].Length)))
+    {
       break;
     }
   }
+
   if (MsrNum == V_EFI_FIXED_MTRR_NUMBER ) {
     return EFI_DEVICE_ERROR;
   }
+
   //
   // We found the fixed MTRR to be programmed
   //
@@ -320,15 +323,18 @@ ProgramFixedMtrr (
       break;
     }
   }
+
   if (ByteShift == 8 ) {
     return EFI_DEVICE_ERROR;
   }
+
   for ( ; ((ByteShift < 8) && (*Len >= mFixedMtrrTable[MsrNum].Length)); ByteShift++) {
     OrMask    |= LShiftU64 ((UINT64)MemoryCacheType, (UINT32)(ByteShift* 8));
     ClearMask |= LShiftU64 ((UINT64)0xFF, (UINT32)(ByteShift * 8));
     *Len      -= mFixedMtrrTable[MsrNum].Length;
     *Base     += mFixedMtrrTable[MsrNum].Length;
   }
+
   TempQword = (AsmReadMsr64 (mFixedMtrrTable[MsrNum].Msr) & (~ClearMask)) | OrMask;
   AsmWriteMsr64 (mFixedMtrrTable[MsrNum].Msr, TempQword);
 
@@ -395,7 +401,7 @@ SetCacheAttributes (
   //
   // Check for invalid parameter
   //
-  if ((MemoryAddress & ~ValidMtrrAddressMask) != 0 || (MemoryLength & ~ValidMtrrAddressMask) != 0) {
+  if (((MemoryAddress & ~ValidMtrrAddressMask) != 0) || ((MemoryLength & ~ValidMtrrAddressMask) != 0)) {
     return EFI_INVALID_PARAMETER;
   }
 
@@ -424,6 +430,7 @@ SetCacheAttributes (
     while ((MemoryLength > 0) && (Status == EFI_SUCCESS)) {
       Status = ProgramFixedMtrr (MemoryCacheType, &MemoryAddress, &MemoryLength);
     }
+
     EfiRecoverCacheMtrr (TRUE, OldMtrr);
     return Status;
   }
@@ -465,7 +472,8 @@ SetCacheAttributes (
         //
         // Modify the MTRR type
         //
-        EfiProgramMtrr(UsedMsrNum,
+        EfiProgramMtrr (
+          UsedMsrNum,
           MemoryAddress,
           MemoryLength,
           MemoryCacheType,
@@ -488,6 +496,7 @@ SetCacheAttributes (
       return EFI_SUCCESS;
     }
   }
+
  #endif
 
   //
@@ -521,13 +530,13 @@ SetCacheAttributes (
   TempQword = MemoryLength;
 
   if (TempQword == Power2MaxMemory (MemoryAddress, TempQword)) {
-    EfiProgramMtrr(MsrNum,
+    EfiProgramMtrr (
+      MsrNum,
       MemoryAddress,
       MemoryLength,
       MemoryCacheType,
       ValidMtrrAddressMask
       );
-
   } else {
     //
     // Fill in MTRRs with values.  Direction can not be checked for this method
@@ -546,7 +555,8 @@ SetCacheAttributes (
       // Set next power of 2 region
       //
       MemoryLength = Power2MaxMemory (MemoryAddress, TempQword);
-      EfiProgramMtrr(MsrNum,
+      EfiProgramMtrr (
+        MsrNum,
         MemoryAddress,
         MemoryLength,
         MemoryCacheType,
@@ -578,6 +588,7 @@ ResetCacheAttributes (
   UINT64   OldMtrr;
   UINT64   CacheType;
   BOOLEAN  DisableCar;
+
   Index      = 0;
   DisableCar = TRUE;
 
@@ -694,4 +705,3 @@ IsDefaultType (
 
   return TRUE;
 }
-

IntelFsp2Pkg/Library/BaseCacheLib/CacheLibInternal.h

@@ -50,4 +50,3 @@
 #define CPUID_EXTENDED_FUNCTION     0x80000000
 
 #endif
-

IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c

@@ -216,7 +216,6 @@ SetFspPlatformDataPointer (
   FspData->PlatformData.DataPtr = PlatformData;
 }
 
-
 /**
   This function gets the platform specific data pointer.
 
@@ -235,7 +234,6 @@ GetFspPlatformDataPointer (
   return FspData->PlatformData.DataPtr;
 }
 
-
 /**
   This function sets the UPD data pointer.
 
@@ -277,7 +275,6 @@ GetFspUpdDataPointer (
   return FspData->UpdDataPtr;
 }
 
-
 /**
   This function sets the FspMemoryInit UPD data pointer.
 
@@ -319,7 +316,6 @@ GetFspMemoryInitUpdDataPointer (
   return FspData->MemoryInitUpdPtr;
 }
 
-
 /**
   This function sets the FspSiliconInit UPD data pointer.
 
@@ -361,7 +357,6 @@ GetFspSiliconInitUpdDataPointer (
   return FspData->SiliconInitUpdPtr;
 }
 
-
 /**
   Set FSP measurement point timestamp.
 

IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c

@@ -39,7 +39,6 @@ GetStackFramePointer (
   VOID
   );
 
-
 /**
   Prints a debug message to the debug output device if the specified error level is enabled.
 
@@ -199,6 +198,7 @@ FillHex (
   )
 {
   INTN  Idx;
+
   for (Idx = 7; Idx >= 0; Idx--) {
     Buffer[Idx] = mHexTable[Value & 0x0F];
     Value     >>= 4;
@@ -291,7 +291,6 @@ DebugAssert (
   DebugAssertInternal ();
 }
 
-
 /**
   Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
 
@@ -317,7 +316,6 @@ DebugClearMemory (
   return Buffer;
 }
 
-
 /**
   Returns TRUE if ASSERT() macros are enabled.
 
@@ -337,7 +335,6 @@ DebugAssertEnabled (
   return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);
 }
 
-
 /**
   Returns TRUE if DEBUG() macros are enabled.
 
@@ -376,7 +373,6 @@ DebugCodeEnabled (
   return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);
 }
 
-
 /**
   Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.
 

IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformMemory.c

@@ -41,10 +41,12 @@ FspGetResourceDescriptorByOwner (
   while (!END_OF_HOB_LIST (Hob)) {
     if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
       if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) && \
-          (CompareGuid (&Hob.ResourceDescriptor->Owner, OwnerGuid))) {
+          (CompareGuid (&Hob.ResourceDescriptor->Owner, OwnerGuid)))
+      {
         return Hob.ResourceDescriptor;
       }
     }
+
     Hob.Raw = GET_NEXT_HOB (Hob);
   }
 
@@ -99,18 +101,21 @@ FspGetSystemMemorySize (
     if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
       if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||
           ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&
-           (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))) {
+           (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute)))
+      {
         //
         // Need memory above 1MB to be collected here
         //
-        if (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB &&
+        if ((Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB) &&
-            Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) BASE_4GB) {
+            (Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS)BASE_4GB))
+        {
           *LowMemoryLength += (UINT64)(Hob.ResourceDescriptor->ResourceLength);
         } else if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS)BASE_4GB) {
           *HighMemoryLength += (UINT64)(Hob.ResourceDescriptor->ResourceLength);
         }
       }
     }
+
     Hob.Raw = GET_NEXT_HOB (Hob);
   }
 }

IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c

@@ -128,6 +128,7 @@ FspSiliconInitDone2 (
       Status = EFI_DEVICE_ERROR;  // Force to known error.
       break;
   }
+
   //
   // This is the end of the FspSiliconInit API
   // Give control back to the boot loader
@@ -171,9 +172,11 @@ FspMemoryInitDone2 (
   if (HobListPtr == NULL) {
     HobListPtr = (VOID **)GetFspApiParameter2 ();
   }
+
   if (HobListPtr != NULL) {
     *HobListPtr = (VOID *)GetHobList ();
   }
+
   //
   // Convert to FSP EAS defined API return codes
   //
@@ -189,6 +192,7 @@ FspMemoryInitDone2 (
       Status = EFI_DEVICE_ERROR;  // Force to known error.
       break;
   }
+
   //
   // This is the end of the FspMemoryInit API
   // Give control back to the boot loader
@@ -258,6 +262,7 @@ FspTempRamExitDone2 (
       Status = EFI_DEVICE_ERROR;  // Force to known error.
       break;
   }
+
   //
   // This is the end of the TempRamExit API
   // Give control back to the boot loader
@@ -275,6 +280,7 @@ FspTempRamExitDone2 (
       }
     } while (FspStatus != EFI_SUCCESS);
   }
+
   SetPhaseStatusCode (FSP_STATUS_CODE_SILICON_INIT);
   SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY);
   PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);
@@ -302,7 +308,6 @@ FspWaitForNotify (
 
   NotificationCount = 0;
   while (NotificationCount < sizeof (mFspNotifySequence) / sizeof (UINT32)) {
-
     Count = (UINT8)((NotificationCount << 1) & 0x07);
     SetFspMeasurePoint (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + Count);
 
@@ -351,6 +356,7 @@ FspWaitForNotify (
       PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);
       REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);
     }
+
     if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) {
       FspStatus = Status;
       do {
@@ -362,6 +368,7 @@ FspWaitForNotify (
       } while (FspStatus != EFI_SUCCESS);
     }
   }
+
   //
   // Control goes back to the PEI Core and it dispatches further PEIMs.
   // DXEIPL is the final one to transfer control back to the boot loader.

IntelFsp2Pkg/Library/BaseFspSwitchStackLib/FspSwitchStackLib.c

@@ -33,4 +33,3 @@ SwapStack (
   FspData->CoreStack = NewStack;
   return OldStack;
 }
-

IntelFsp2Pkg/Tools/Tests/ExpectedFspmUpd.h

@@ -5,11 +5,9 @@
 
 #pragma pack(1)
 
-
 /** Fsp M Configuration
 **/
 typedef struct {
-
   /** Offset 0x00C8 - Debug Serial Port Base address
     Debug serial port base address. This option will be used only when the 'Serial Port
     Debug Device' option is set to 'External Device'. 0x00000000(Default).
@@ -48,7 +46,6 @@ typedef struct {
 /** Fsp M UPD Configuration
 **/
 typedef struct {
-
   /** Offset 0x0000
   **/
   FSP_UPD_HEADER    FspUpdHeader;

IntelFsp2Pkg/Tools/Tests/ExpectedFspsUpd.h

@@ -5,11 +5,9 @@
 
 #pragma pack(1)
 
-
 /** Fsp S Configuration
 **/
 typedef struct {
-
   /** Offset 0x0118 - BMP Logo Data Size
     BMP logo data buffer size. 0x00000000(Default).
   **/
@@ -42,7 +40,6 @@ typedef struct {
 /** Fsp S UPD Configuration
 **/
 typedef struct {
-
   /** Offset 0x0000
   **/
   FSP_UPD_HEADER    FspUpdHeader;

IntelFsp2Pkg/Tools/Tests/ExpectedFsptUpd.h

@@ -5,11 +5,9 @@
 
 #pragma pack(1)
 
-
 /** Fsp T Common UPD
 **/
 typedef struct {
-
   /** Offset 0x0040
   **/
   UINT8     Revision;
@@ -42,7 +40,6 @@ typedef struct {
 /** Fsp T Configuration
 **/
 typedef struct {
-
   /** Offset 0x0060 - Chicken bytes to test Hex config
     This option shows how to present option for 4 bytes data
   **/
@@ -56,7 +53,6 @@ typedef struct {
 /** Fsp T UPD Configuration
 **/
 typedef struct {
-
   /** Offset 0x0000
   **/
   FSP_UPD_HEADER     FspUpdHeader;