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IntelFsp2Pkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the IntelFsp2Pkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
This commit is contained in:
Michael Kubacki 2021-12-05 14:53:59 -08:00 committed by mergify[bot]
parent 45ce0a67bb
commit 111f2228dd
33 changed files with 877 additions and 882 deletions
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44
IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c
View File

@ -21,28 +21,28 @@
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
WaitForNotify ( WaitForNotify (
IN CONST EFI_DXE_IPL_PPI *This, IN CONST EFI_DXE_IPL_PPI *This,
IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_HOB_POINTERS HobList IN EFI_PEI_HOB_POINTERS HobList
); );
CONST EFI_DXE_IPL_PPI mDxeIplPpi = { CONST EFI_DXE_IPL_PPI mDxeIplPpi = {
WaitForNotify WaitForNotify
}; };
CONST EFI_PEI_PPI_DESCRIPTOR mInstallDxeIplPpi = { CONST EFI_PEI_PPI_DESCRIPTOR mInstallDxeIplPpi = {
EFI_PEI_PPI_DESCRIPTOR_PPI, EFI_PEI_PPI_DESCRIPTOR_PPI,
&gEfiDxeIplPpiGuid, &gEfiDxeIplPpiGuid,
(VOID *) &mDxeIplPpi (VOID *)&mDxeIplPpi
}; };
CONST EFI_PEI_PPI_DESCRIPTOR gEndOfPeiSignalPpi = { CONST EFI_PEI_PPI_DESCRIPTOR gEndOfPeiSignalPpi = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiEndOfPeiSignalPpiGuid, &gEfiEndOfPeiSignalPpiGuid,
NULL NULL
}; };
CONST EFI_PEI_PPI_DESCRIPTOR gFspReadyForNotifyPhasePpi = { CONST EFI_PEI_PPI_DESCRIPTOR gFspReadyForNotifyPhasePpi = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gFspReadyForNotifyPhasePpiGuid, &gFspReadyForNotifyPhasePpiGuid,
NULL NULL
@ -62,12 +62,12 @@ CONST EFI_PEI_PPI_DESCRIPTOR gFspReadyForNotifyPhasePpi = {
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
WaitForNotify ( WaitForNotify (
IN CONST EFI_DXE_IPL_PPI *This, IN CONST EFI_DXE_IPL_PPI *This,
IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_HOB_POINTERS HobList IN EFI_PEI_HOB_POINTERS HobList
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP HOB is located at 0x%08X\n", HobList)); DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP HOB is located at 0x%08X\n", HobList));
@ -113,13 +113,13 @@ WaitForNotify (
**/ **/
EFI_STATUS EFI_STATUS
FspNotifyPhasePeimEntryPoint ( FspNotifyPhasePeimEntryPoint (
IN EFI_PEI_FILE_HANDLE FileHandle, IN EFI_PEI_FILE_HANDLE FileHandle,
IN CONST EFI_PEI_SERVICES **PeiServices IN CONST EFI_PEI_SERVICES **PeiServices
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
VOID *OldDxeIplPpi; VOID *OldDxeIplPpi;
EFI_PEI_PPI_DESCRIPTOR *OldDescriptor; EFI_PEI_PPI_DESCRIPTOR *OldDescriptor;
DEBUG ((DEBUG_INFO | DEBUG_INIT, "The entry of FspNotificationPeim\n")); DEBUG ((DEBUG_INFO | DEBUG_INIT, "The entry of FspNotificationPeim\n"));
@ -128,11 +128,11 @@ FspNotifyPhasePeimEntryPoint (
// Locate old DXE IPL PPI // Locate old DXE IPL PPI
// //
Status = PeiServicesLocatePpi ( Status = PeiServicesLocatePpi (
&gEfiDxeIplPpiGuid, &gEfiDxeIplPpiGuid,
0, 0,
&OldDescriptor, &OldDescriptor,
&OldDxeIplPpi &OldDxeIplPpi
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// //

87
IntelFsp2Pkg/FspSecCore/SecFsp.c
View File

@ -17,20 +17,20 @@
**/ **/
UINT64 UINT64
FspGetExceptionHandler( FspGetExceptionHandler (
IN UINT64 IdtEntryTemplate IN UINT64 IdtEntryTemplate
) )
{ {
UINT32 Entry; UINT32 Entry;
UINT64 ExceptionHandler; UINT64 ExceptionHandler;
IA32_IDT_GATE_DESCRIPTOR *IdtGateDescriptor; IA32_IDT_GATE_DESCRIPTOR *IdtGateDescriptor;
FSP_INFO_HEADER *FspInfoHeader; FSP_INFO_HEADER *FspInfoHeader;
FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader(); FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader ();
ExceptionHandler = IdtEntryTemplate; ExceptionHandler = IdtEntryTemplate;
IdtGateDescriptor = (IA32_IDT_GATE_DESCRIPTOR *)&ExceptionHandler; IdtGateDescriptor = (IA32_IDT_GATE_DESCRIPTOR *)&ExceptionHandler;
Entry = (IdtGateDescriptor->Bits.OffsetHigh << 16) | IdtGateDescriptor->Bits.OffsetLow; Entry = (IdtGateDescriptor->Bits.OffsetHigh << 16) | IdtGateDescriptor->Bits.OffsetLow;
Entry = FspInfoHeader->ImageBase + FspInfoHeader->ImageSize - (~Entry + 1); Entry = FspInfoHeader->ImageBase + FspInfoHeader->ImageSize - (~Entry + 1);
IdtGateDescriptor->Bits.OffsetHigh = (UINT16)(Entry >> 16); IdtGateDescriptor->Bits.OffsetHigh = (UINT16)(Entry >> 16);
IdtGateDescriptor->Bits.OffsetLow = (UINT16)Entry; IdtGateDescriptor->Bits.OffsetLow = (UINT16)Entry;
@ -46,13 +46,13 @@ FspGetExceptionHandler(
VOID VOID
EFIAPI EFIAPI
SecGetPlatformData ( SecGetPlatformData (
IN OUT FSP_GLOBAL_DATA *FspData IN OUT FSP_GLOBAL_DATA *FspData
) )
{ {
FSP_PLAT_DATA *FspPlatformData; FSP_PLAT_DATA *FspPlatformData;
UINT32 TopOfCar; UINT32 TopOfCar;
UINT32 *StackPtr; UINT32 *StackPtr;
UINT32 DwordSize; UINT32 DwordSize;
FspPlatformData = &FspData->PlatformData; FspPlatformData = &FspData->PlatformData;
@ -61,7 +61,7 @@ SecGetPlatformData (
// reside in the bottom of stack, left untouched by normal stack operation. // reside in the bottom of stack, left untouched by normal stack operation.
// //
FspPlatformData->DataPtr = NULL; FspPlatformData->DataPtr = NULL;
FspPlatformData->MicrocodeRegionBase = 0; FspPlatformData->MicrocodeRegionBase = 0;
FspPlatformData->MicrocodeRegionSize = 0; FspPlatformData->MicrocodeRegionSize = 0;
FspPlatformData->CodeRegionBase = 0; FspPlatformData->CodeRegionBase = 0;
@ -70,7 +70,7 @@ SecGetPlatformData (
// //
// Pointer to the size field // Pointer to the size field
// //
TopOfCar = PcdGet32(PcdTemporaryRamBase) + PcdGet32(PcdTemporaryRamSize); TopOfCar = PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamSize);
StackPtr = (UINT32 *)(TopOfCar - sizeof (UINT32)); StackPtr = (UINT32 *)(TopOfCar - sizeof (UINT32));
if (*(StackPtr - 1) == FSP_MCUD_SIGNATURE) { if (*(StackPtr - 1) == FSP_MCUD_SIGNATURE) {
@ -114,26 +114,26 @@ SecGetPlatformData (
**/ **/
VOID VOID
FspGlobalDataInit ( FspGlobalDataInit (
IN OUT FSP_GLOBAL_DATA *PeiFspData, IN OUT FSP_GLOBAL_DATA *PeiFspData,
IN UINT32 BootLoaderStack, IN UINT32 BootLoaderStack,
IN UINT8 ApiIdx IN UINT8 ApiIdx
) )
{ {
VOID *FspmUpdDataPtr; VOID *FspmUpdDataPtr;
CHAR8 ImageId[9]; CHAR8 ImageId[9];
UINTN Idx; UINTN Idx;
// //
// Set FSP Global Data pointer // Set FSP Global Data pointer
// //
SetFspGlobalDataPointer (PeiFspData); SetFspGlobalDataPointer (PeiFspData);
ZeroMem ((VOID *)PeiFspData, sizeof(FSP_GLOBAL_DATA)); ZeroMem ((VOID *)PeiFspData, sizeof (FSP_GLOBAL_DATA));
PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE; PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE;
PeiFspData->Version = 0; PeiFspData->Version = 0;
PeiFspData->CoreStack = BootLoaderStack; PeiFspData->CoreStack = BootLoaderStack;
PeiFspData->PerfIdx = 2; PeiFspData->PerfIdx = 2;
PeiFspData->PerfSig = FSP_PERFORMANCE_DATA_SIGNATURE; PeiFspData->PerfSig = FSP_PERFORMANCE_DATA_SIGNATURE;
SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY); SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY);
@ -141,7 +141,7 @@ FspGlobalDataInit (
// Get FSP Header offset // Get FSP Header offset
// It may have multiple FVs, so look into the last one for FSP header // It may have multiple FVs, so look into the last one for FSP header
// //
PeiFspData->FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader(); PeiFspData->FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader ();
SecGetPlatformData (PeiFspData); SecGetPlatformData (PeiFspData);
// //
@ -152,10 +152,11 @@ FspGlobalDataInit (
// //
// Set UPD pointer // Set UPD pointer
// //
FspmUpdDataPtr = (VOID *) GetFspApiParameter (); FspmUpdDataPtr = (VOID *)GetFspApiParameter ();
if (FspmUpdDataPtr == NULL) { if (FspmUpdDataPtr == NULL) {
FspmUpdDataPtr = (VOID *)(PeiFspData->FspInfoHeader->ImageBase + PeiFspData->FspInfoHeader->CfgRegionOffset); FspmUpdDataPtr = (VOID *)(PeiFspData->FspInfoHeader->ImageBase + PeiFspData->FspInfoHeader->CfgRegionOffset);
} }
SetFspUpdDataPointer (FspmUpdDataPtr); SetFspUpdDataPointer (FspmUpdDataPtr);
SetFspMemoryInitUpdDataPointer (FspmUpdDataPtr); SetFspMemoryInitUpdDataPointer (FspmUpdDataPtr);
SetFspSiliconInitUpdDataPointer (NULL); SetFspSiliconInitUpdDataPointer (NULL);
@ -186,17 +187,21 @@ FspGlobalDataInit (
for (Idx = 0; Idx < 8; Idx++) { for (Idx = 0; Idx < 8; Idx++) {
ImageId[Idx] = PeiFspData->FspInfoHeader->ImageId[Idx]; ImageId[Idx] = PeiFspData->FspInfoHeader->ImageId[Idx];
} }
ImageId[Idx] = 0; ImageId[Idx] = 0;
DEBUG ((DEBUG_INFO | DEBUG_INIT, "\n============= FSP Spec v%d.%d Header Revision v%x (%a v%x.%x.%x.%x) =============\n", \ DEBUG ((
(PeiFspData->FspInfoHeader->SpecVersion >> 4) & 0xF, \ DEBUG_INFO | DEBUG_INIT,
PeiFspData->FspInfoHeader->SpecVersion & 0xF, \ "\n============= FSP Spec v%d.%d Header Revision v%x (%a v%x.%x.%x.%x) =============\n", \
PeiFspData->FspInfoHeader->HeaderRevision, \ (PeiFspData->FspInfoHeader->SpecVersion >> 4) & 0xF, \
ImageId, \ PeiFspData->FspInfoHeader->SpecVersion & 0xF, \
(PeiFspData->FspInfoHeader->ImageRevision >> 24) & 0xFF, \ PeiFspData->FspInfoHeader->HeaderRevision, \
(PeiFspData->FspInfoHeader->ImageRevision >> 16) & 0xFF, \ ImageId, \
(PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xFF, \ (PeiFspData->FspInfoHeader->ImageRevision >> 24) & 0xFF, \
PeiFspData->FspInfoHeader->ImageRevision & 0xFF)); (PeiFspData->FspInfoHeader->ImageRevision >> 16) & 0xFF, \
(PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xFF, \
PeiFspData->FspInfoHeader->ImageRevision & 0xFF
));
} }
/** /**
@ -208,11 +213,11 @@ FspGlobalDataInit (
**/ **/
VOID VOID
FspDataPointerFixUp ( FspDataPointerFixUp (
IN UINT32 OffsetGap IN UINT32 OffsetGap
) )
{ {
FSP_GLOBAL_DATA *NewFspData; FSP_GLOBAL_DATA *NewFspData;
NewFspData = (FSP_GLOBAL_DATA *)((UINTN)GetFspGlobalDataPointer() + (UINTN)OffsetGap); NewFspData = (FSP_GLOBAL_DATA *)((UINTN)GetFspGlobalDataPointer () + (UINTN)OffsetGap);
SetFspGlobalDataPointer (NewFspData); SetFspGlobalDataPointer (NewFspData);
} }

12
IntelFsp2Pkg/FspSecCore/SecFsp.h
View File

@ -31,7 +31,7 @@
**/ **/
UINT64 UINT64
FspGetExceptionHandler( FspGetExceptionHandler (
IN UINT64 IdtEntryTemplate IN UINT64 IdtEntryTemplate
); );
@ -47,12 +47,11 @@ FspGetExceptionHandler(
**/ **/
VOID VOID
FspGlobalDataInit ( FspGlobalDataInit (
IN OUT FSP_GLOBAL_DATA *PeiFspData, IN OUT FSP_GLOBAL_DATA *PeiFspData,
IN UINT32 BootLoaderStack, IN UINT32 BootLoaderStack,
IN UINT8 ApiIdx IN UINT8 ApiIdx
); );
/** /**
Adjust the FSP data pointers after the stack is migrated to memory. Adjust the FSP data pointers after the stack is migrated to memory.
@ -62,10 +61,9 @@ FspGlobalDataInit (
**/ **/
VOID VOID
FspDataPointerFixUp ( FspDataPointerFixUp (
IN UINT32 OffsetGap IN UINT32 OffsetGap
); );
/** /**
This interface returns the base address of FSP binary. This interface returns the base address of FSP binary.

11
IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
View File

@ -7,7 +7,6 @@
#include "SecFsp.h" #include "SecFsp.h"
/** /**
This function check the FSP API calling condition. This function check the FSP API calling condition.
@ -18,14 +17,14 @@
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FspApiCallingCheck ( FspApiCallingCheck (
IN UINT8 ApiIdx, IN UINT8 ApiIdx,
IN VOID *ApiParam IN VOID *ApiParam
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
if (ApiIdx == NotifyPhaseApiIndex) { if (ApiIdx == NotifyPhaseApiIndex) {

125
IntelFsp2Pkg/FspSecCore/SecMain.c
View File

@ -8,11 +8,11 @@
#include "SecMain.h" #include "SecMain.h"
#include "SecFsp.h" #include "SecFsp.h"
EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI gSecTemporaryRamSupportPpi = { EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI gSecTemporaryRamSupportPpi = {
SecTemporaryRamSupport SecTemporaryRamSupport
}; };
EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformationPpi[] = { EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformationPpi[] = {
{ {
EFI_PEI_PPI_DESCRIPTOR_PPI, EFI_PEI_PPI_DESCRIPTOR_PPI,
&gFspInApiModePpiGuid, &gFspInApiModePpiGuid,
@ -50,21 +50,21 @@ UINT64 mIdtEntryTemplate = 0xffff8e000008ffe4ULL;
VOID VOID
EFIAPI EFIAPI
SecStartup ( SecStartup (
IN UINT32 SizeOfRam, IN UINT32 SizeOfRam,
IN UINT32 TempRamBase, IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume, IN VOID *BootFirmwareVolume,
IN PEI_CORE_ENTRY PeiCore, IN PEI_CORE_ENTRY PeiCore,
IN UINT32 BootLoaderStack, IN UINT32 BootLoaderStack,
IN UINT32 ApiIdx IN UINT32 ApiIdx
) )
{ {
EFI_SEC_PEI_HAND_OFF SecCoreData; EFI_SEC_PEI_HAND_OFF SecCoreData;
IA32_DESCRIPTOR IdtDescriptor; IA32_DESCRIPTOR IdtDescriptor;
SEC_IDT_TABLE IdtTableInStack; SEC_IDT_TABLE IdtTableInStack;
UINT32 Index; UINT32 Index;
FSP_GLOBAL_DATA PeiFspData; FSP_GLOBAL_DATA PeiFspData;
UINT64 ExceptionHandler; UINT64 ExceptionHandler;
UINTN IdtSize; UINTN IdtSize;
// //
// Process all libraries constructor function linked to SecCore. // Process all libraries constructor function linked to SecCore.
@ -117,10 +117,11 @@ SecStartup (
IdtTableInStack.PeiService = 0; IdtTableInStack.PeiService = 0;
AsmReadIdtr (&IdtDescriptor); AsmReadIdtr (&IdtDescriptor);
if (IdtDescriptor.Base == 0) { if (IdtDescriptor.Base == 0) {
ExceptionHandler = FspGetExceptionHandler(mIdtEntryTemplate); ExceptionHandler = FspGetExceptionHandler (mIdtEntryTemplate);
for (Index = 0; Index < FixedPcdGet8(PcdFspMaxInterruptSupported); Index ++) { for (Index = 0; Index < FixedPcdGet8 (PcdFspMaxInterruptSupported); Index++) {
CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&ExceptionHandler, sizeof (UINT64)); CopyMem ((VOID *)&IdtTableInStack.IdtTable[Index], (VOID *)&ExceptionHandler, sizeof (UINT64));
} }
IdtSize = sizeof (IdtTableInStack.IdtTable); IdtSize = sizeof (IdtTableInStack.IdtTable);
} else { } else {
IdtSize = IdtDescriptor.Limit + 1; IdtSize = IdtDescriptor.Limit + 1;
@ -128,12 +129,13 @@ SecStartup (
// //
// ERROR: IDT table size from boot loader is larger than FSP can support, DeadLoop here! // ERROR: IDT table size from boot loader is larger than FSP can support, DeadLoop here!
// //
CpuDeadLoop(); CpuDeadLoop ();
} else { } else {
CopyMem ((VOID *) (UINTN) &IdtTableInStack.IdtTable, (VOID *) IdtDescriptor.Base, IdtSize); CopyMem ((VOID *)(UINTN)&IdtTableInStack.IdtTable, (VOID *)IdtDescriptor.Base, IdtSize);
} }
} }
IdtDescriptor.Base = (UINTN) &IdtTableInStack.IdtTable;
IdtDescriptor.Base = (UINTN)&IdtTableInStack.IdtTable;
IdtDescriptor.Limit = (UINT16)(IdtSize - 1); IdtDescriptor.Limit = (UINT16)(IdtSize - 1);
AsmWriteIdtr (&IdtDescriptor); AsmWriteIdtr (&IdtDescriptor);
@ -154,18 +156,18 @@ SecStartup (
// Support FSP reserved temporary memory from the whole temporary memory provided by bootloader. // Support FSP reserved temporary memory from the whole temporary memory provided by bootloader.
// FSP reserved temporary memory will not be given to PeiCore. // FSP reserved temporary memory will not be given to PeiCore.
// //
SecCoreData.TemporaryRamBase = (UINT8 *)(UINTN) TempRamBase + PcdGet32 (PcdFspPrivateTemporaryRamSize); SecCoreData.TemporaryRamBase = (UINT8 *)(UINTN)TempRamBase + PcdGet32 (PcdFspPrivateTemporaryRamSize);
SecCoreData.TemporaryRamSize = SizeOfRam - PcdGet32 (PcdFspPrivateTemporaryRamSize); SecCoreData.TemporaryRamSize = SizeOfRam - PcdGet32 (PcdFspPrivateTemporaryRamSize);
if (PcdGet8 (PcdFspHeapSizePercentage) == 0) { if (PcdGet8 (PcdFspHeapSizePercentage) == 0) {
SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase; SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize; SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize;
SecCoreData.StackBase = (VOID *)GetFspEntryStack(); // Share the same boot loader stack SecCoreData.StackBase = (VOID *)GetFspEntryStack (); // Share the same boot loader stack
SecCoreData.StackSize = 0; SecCoreData.StackSize = 0;
} else { } else {
SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase; SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize * PcdGet8 (PcdFspHeapSizePercentage) / 100; SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize * PcdGet8 (PcdFspHeapSizePercentage) / 100;
SecCoreData.StackBase = (VOID*)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize); SecCoreData.StackBase = (VOID *)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize; SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
} }
DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeBase - 0x%x\n", SecCoreData.BootFirmwareVolumeBase)); DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeBase - 0x%x\n", SecCoreData.BootFirmwareVolumeBase));
@ -207,22 +209,22 @@ SecStartup (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
SecTemporaryRamSupport ( SecTemporaryRamSupport (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
IN UINTN CopySize IN UINTN CopySize
) )
{ {
IA32_DESCRIPTOR IdtDescriptor; IA32_DESCRIPTOR IdtDescriptor;
VOID* OldHeap; VOID *OldHeap;
VOID* NewHeap; VOID *NewHeap;
VOID* OldStack; VOID *OldStack;
VOID* NewStack; VOID *NewStack;
UINTN HeapSize; UINTN HeapSize;
UINTN StackSize; UINTN StackSize;
UINTN CurrentStack; UINTN CurrentStack;
UINTN FspStackBase; UINTN FspStackBase;
// //
// Override OnSeparateStack to 1 because this function will switch stack to permanent memory // Override OnSeparateStack to 1 because this function will switch stack to permanent memory
@ -231,33 +233,31 @@ SecTemporaryRamSupport (
GetFspGlobalDataPointer ()->OnSeparateStack = 1; GetFspGlobalDataPointer ()->OnSeparateStack = 1;
if (PcdGet8 (PcdFspHeapSizePercentage) == 0) { if (PcdGet8 (PcdFspHeapSizePercentage) == 0) {
CurrentStack = AsmReadEsp ();
CurrentStack = AsmReadEsp(); FspStackBase = (UINTN)GetFspEntryStack ();
FspStackBase = (UINTN)GetFspEntryStack();
StackSize = FspStackBase - CurrentStack; StackSize = FspStackBase - CurrentStack;
HeapSize = CopySize; HeapSize = CopySize;
OldHeap = (VOID*)(UINTN)TemporaryMemoryBase; OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;
NewHeap = (VOID*)((UINTN)PermanentMemoryBase); NewHeap = (VOID *)((UINTN)PermanentMemoryBase);
OldStack = (VOID*)CurrentStack; OldStack = (VOID *)CurrentStack;
// //
//The old stack is copied at the end of the stack region because stack grows down. // The old stack is copied at the end of the stack region because stack grows down.
// //
NewStack = (VOID*)((UINTN)PermanentMemoryBase - StackSize); NewStack = (VOID *)((UINTN)PermanentMemoryBase - StackSize);
} else { } else {
HeapSize = CopySize * PcdGet8 (PcdFspHeapSizePercentage) / 100 ; HeapSize = CopySize * PcdGet8 (PcdFspHeapSizePercentage) / 100;
StackSize = CopySize - HeapSize; StackSize = CopySize - HeapSize;
OldHeap = (VOID*)(UINTN)TemporaryMemoryBase; OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;
NewHeap = (VOID*)((UINTN)PermanentMemoryBase + StackSize); NewHeap = (VOID *)((UINTN)PermanentMemoryBase + StackSize);
OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);
NewStack = (VOID*)(UINTN)PermanentMemoryBase;
OldStack = (VOID *)((UINTN)TemporaryMemoryBase + HeapSize);
NewStack = (VOID *)(UINTN)PermanentMemoryBase;
} }
// //
// Migrate Heap // Migrate Heap
// //
@ -268,7 +268,6 @@ SecTemporaryRamSupport (
// //
CopyMem (NewStack, OldStack, StackSize); CopyMem (NewStack, OldStack, StackSize);
// //
// We need *not* fix the return address because currently, // We need *not* fix the return address because currently,
// The PeiCore is executed in flash. // The PeiCore is executed in flash.
@ -293,8 +292,8 @@ SecTemporaryRamSupport (
// permanent memory. // permanent memory.
// //
SecSwitchStack ( SecSwitchStack (
(UINT32) (UINTN) OldStack, (UINT32)(UINTN)OldStack,
(UINT32) (UINTN) NewStack (UINT32)(UINTN)NewStack
); );
return EFI_SUCCESS; return EFI_SUCCESS;

32
IntelFsp2Pkg/FspSecCore/SecMain.h
View File

@ -8,7 +8,6 @@
#ifndef _SEC_CORE_H_ #ifndef _SEC_CORE_H_
#define _SEC_CORE_H_ #define _SEC_CORE_H_
#include <PiPei.h> #include <PiPei.h>
#include <Ppi/TemporaryRamSupport.h> #include <Ppi/TemporaryRamSupport.h>
@ -27,7 +26,7 @@
typedef VOID (*PEI_CORE_ENTRY) ( \ typedef VOID (*PEI_CORE_ENTRY) ( \
IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData, \ IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData, \
IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList \ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList \
); );
typedef struct _SEC_IDT_TABLE { typedef struct _SEC_IDT_TABLE {
// //
@ -36,8 +35,8 @@ typedef struct _SEC_IDT_TABLE {
// Note: For IA32, only the 4 bytes immediately preceding IDT is used to store // Note: For IA32, only the 4 bytes immediately preceding IDT is used to store
// EFI_PEI_SERVICES** // EFI_PEI_SERVICES**
// //
UINT64 PeiService; UINT64 PeiService;
UINT64 IdtTable[FixedPcdGet8 (PcdFspMaxInterruptSupported)]; UINT64 IdtTable[FixedPcdGet8 (PcdFspMaxInterruptSupported)];
} SEC_IDT_TABLE; } SEC_IDT_TABLE;
/** /**
@ -52,8 +51,8 @@ typedef struct _SEC_IDT_TABLE {
VOID VOID
EFIAPI EFIAPI
SecSwitchStack ( SecSwitchStack (
IN UINT32 TemporaryMemoryBase, IN UINT32 TemporaryMemoryBase,
IN UINT32 PermenentMemoryBase IN UINT32 PermenentMemoryBase
); );
/** /**
@ -75,13 +74,12 @@ SecSwitchStack (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
SecTemporaryRamSupport ( SecTemporaryRamSupport (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
IN UINTN CopySize IN UINTN CopySize
); );
/** /**
Entry point to the C language phase of SEC. After the SEC assembly Entry point to the C language phase of SEC. After the SEC assembly
@ -102,12 +100,12 @@ SecTemporaryRamSupport (
VOID VOID
EFIAPI EFIAPI
SecStartup ( SecStartup (
IN UINT32 SizeOfRam, IN UINT32 SizeOfRam,
IN UINT32 TempRamBase, IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume, IN VOID *BootFirmwareVolume,
IN PEI_CORE_ENTRY PeiCore, IN PEI_CORE_ENTRY PeiCore,
IN UINT32 BootLoaderStack, IN UINT32 BootLoaderStack,
IN UINT32 ApiIdx IN UINT32 ApiIdx
); );
/** /**

124
IntelFsp2Pkg/Include/FspEas/FspApi.h
View File

@ -16,21 +16,21 @@
/// FSP Reset Status code /// FSP Reset Status code
/// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code /// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code
/// @{ /// @{
#define FSP_STATUS_RESET_REQUIRED_COLD 0x40000001 #define FSP_STATUS_RESET_REQUIRED_COLD 0x40000001
#define FSP_STATUS_RESET_REQUIRED_WARM 0x40000002 #define FSP_STATUS_RESET_REQUIRED_WARM 0x40000002
#define FSP_STATUS_RESET_REQUIRED_3 0x40000003 #define FSP_STATUS_RESET_REQUIRED_3 0x40000003
#define FSP_STATUS_RESET_REQUIRED_4 0x40000004 #define FSP_STATUS_RESET_REQUIRED_4 0x40000004
#define FSP_STATUS_RESET_REQUIRED_5 0x40000005 #define FSP_STATUS_RESET_REQUIRED_5 0x40000005
#define FSP_STATUS_RESET_REQUIRED_6 0x40000006 #define FSP_STATUS_RESET_REQUIRED_6 0x40000006
#define FSP_STATUS_RESET_REQUIRED_7 0x40000007 #define FSP_STATUS_RESET_REQUIRED_7 0x40000007
#define FSP_STATUS_RESET_REQUIRED_8 0x40000008 #define FSP_STATUS_RESET_REQUIRED_8 0x40000008
/// @} /// @}
/// ///
/// FSP Event related definition. /// FSP Event related definition.
/// ///
#define FSP_EVENT_CODE 0xF5000000 #define FSP_EVENT_CODE 0xF5000000
#define FSP_POST_CODE (FSP_EVENT_CODE | 0x00F80000) #define FSP_POST_CODE (FSP_EVENT_CODE | 0x00F80000)
/* /*
FSP may optionally include the capability of generating events messages to aid in the debugging of firmware issues. FSP may optionally include the capability of generating events messages to aid in the debugging of firmware issues.
@ -60,7 +60,7 @@
*/ */
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *FSP_EVENT_HANDLER) ( (EFIAPI *FSP_EVENT_HANDLER)(
IN EFI_STATUS_CODE_TYPE Type, IN EFI_STATUS_CODE_TYPE Type,
IN EFI_STATUS_CODE_VALUE Value, IN EFI_STATUS_CODE_VALUE Value,
IN UINT32 Instance, IN UINT32 Instance,
@ -80,8 +80,8 @@ EFI_STATUS
*/ */
typedef typedef
UINT32 UINT32
(EFIAPI *FSP_DEBUG_HANDLER) ( (EFIAPI *FSP_DEBUG_HANDLER)(
IN CHAR8* DebugMessage, IN CHAR8 *DebugMessage,
IN UINT32 MessageLength IN UINT32 MessageLength
); );
@ -97,14 +97,14 @@ typedef struct {
/// "XXXXXX_S" for FSP-S /// "XXXXXX_S" for FSP-S
/// Where XXXXXX is an unique signature /// Where XXXXXX is an unique signature
/// ///
UINT64 Signature; UINT64 Signature;
/// ///
/// Revision of the Data structure. /// Revision of the Data structure.
/// For FSP spec 2.0/2.1 value is 1. /// For FSP spec 2.0/2.1 value is 1.
/// For FSP spec 2.2 value is 2. /// For FSP spec 2.2 value is 2.
/// ///
UINT8 Revision; UINT8 Revision;
UINT8 Reserved[23]; UINT8 Reserved[23];
} FSP_UPD_HEADER; } FSP_UPD_HEADER;
/// ///
@ -114,18 +114,18 @@ typedef struct {
/// ///
/// Revision Revision of the structure is 1 for this version of the specification. /// Revision Revision of the structure is 1 for this version of the specification.
/// ///
UINT8 Revision; UINT8 Revision;
UINT8 Reserved[3]; UINT8 Reserved[3];
/// ///
/// Length Length of the structure in bytes. The current value for this field is 32. /// Length Length of the structure in bytes. The current value for this field is 32.
/// ///
UINT32 Length; UINT32 Length;
/// ///
/// FspDebugHandler Optional debug handler for the bootloader to receive debug messages /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages
/// occurring during FSP execution. /// occurring during FSP execution.
/// ///
FSP_DEBUG_HANDLER FspDebugHandler; FSP_DEBUG_HANDLER FspDebugHandler;
UINT8 Reserved1[20]; UINT8 Reserved1[20];
} FSPT_ARCH_UPD; } FSPT_ARCH_UPD;
/// ///
@ -135,55 +135,55 @@ typedef struct {
/// ///
/// Revision of the structure. For FSP v2.0 value is 1. /// Revision of the structure. For FSP v2.0 value is 1.
/// ///
UINT8 Revision; UINT8 Revision;
UINT8 Reserved[3]; UINT8 Reserved[3];
/// ///
/// Pointer to the non-volatile storage (NVS) data buffer. /// Pointer to the non-volatile storage (NVS) data buffer.
/// If it is NULL it indicates the NVS data is not available. /// If it is NULL it indicates the NVS data is not available.
/// ///
VOID *NvsBufferPtr; VOID *NvsBufferPtr;
/// ///
/// Pointer to the temporary stack base address to be /// Pointer to the temporary stack base address to be
/// consumed inside FspMemoryInit() API. /// consumed inside FspMemoryInit() API.
/// ///
VOID *StackBase; VOID *StackBase;
/// ///
/// Temporary stack size to be consumed inside /// Temporary stack size to be consumed inside
/// FspMemoryInit() API. /// FspMemoryInit() API.
/// ///
UINT32 StackSize; UINT32 StackSize;
/// ///
/// Size of memory to be reserved by FSP below "top /// Size of memory to be reserved by FSP below "top
/// of low usable memory" for bootloader usage. /// of low usable memory" for bootloader usage.
/// ///
UINT32 BootLoaderTolumSize; UINT32 BootLoaderTolumSize;
/// ///
/// Current boot mode. /// Current boot mode.
/// ///
UINT32 BootMode; UINT32 BootMode;
/// ///
/// Optional event handler for the bootloader to be informed of events occurring during FSP execution. /// Optional event handler for the bootloader to be informed of events occurring during FSP execution.
/// This value is only valid if Revision is >= 2. /// This value is only valid if Revision is >= 2.
/// ///
FSP_EVENT_HANDLER *FspEventHandler; FSP_EVENT_HANDLER *FspEventHandler;
UINT8 Reserved1[4]; UINT8 Reserved1[4];
} FSPM_ARCH_UPD; } FSPM_ARCH_UPD;
typedef struct { typedef struct {
/// ///
/// Revision Revision of the structure is 1 for this version of the specification. /// Revision Revision of the structure is 1 for this version of the specification.
/// ///
UINT8 Revision; UINT8 Revision;
UINT8 Reserved[3]; UINT8 Reserved[3];
/// ///
/// Length Length of the structure in bytes. The current value for this field is 32. /// Length Length of the structure in bytes. The current value for this field is 32.
/// ///
UINT32 Length; UINT32 Length;
/// ///
/// FspEventHandler Optional event handler for the bootloader to be informed of events /// FspEventHandler Optional event handler for the bootloader to be informed of events
/// occurring during FSP execution. /// occurring during FSP execution.
/// ///
FSP_EVENT_HANDLER FspEventHandler; FSP_EVENT_HANDLER FspEventHandler;
/// ///
/// A FSP binary may optionally implement multi-phase silicon initialization, /// A FSP binary may optionally implement multi-phase silicon initialization,
/// This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER /// This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER
@ -191,8 +191,8 @@ typedef struct {
/// To enable multi-phase silicon initialization, the bootloader must set /// To enable multi-phase silicon initialization, the bootloader must set
/// EnableMultiPhaseSiliconInit to a non-zero value. /// EnableMultiPhaseSiliconInit to a non-zero value.
/// ///
UINT8 EnableMultiPhaseSiliconInit; UINT8 EnableMultiPhaseSiliconInit;
UINT8 Reserved1[19]; UINT8 Reserved1[19];
} FSPS_ARCH_UPD; } FSPS_ARCH_UPD;
/// ///
@ -202,7 +202,7 @@ typedef struct {
/// ///
/// FSP_UPD_HEADER Configuration. /// FSP_UPD_HEADER Configuration.
/// ///
FSP_UPD_HEADER FspUpdHeader; FSP_UPD_HEADER FspUpdHeader;
} FSPT_UPD_COMMON; } FSPT_UPD_COMMON;
/// ///
@ -212,12 +212,12 @@ typedef struct {
/// ///
/// FSP_UPD_HEADER Configuration. /// FSP_UPD_HEADER Configuration.
/// ///
FSP_UPD_HEADER FspUpdHeader; FSP_UPD_HEADER FspUpdHeader;
/// ///
/// FSPT_ARCH_UPD Configuration. /// FSPT_ARCH_UPD Configuration.
/// ///
FSPT_ARCH_UPD FsptArchUpd; FSPT_ARCH_UPD FsptArchUpd;
} FSPT_UPD_COMMON_FSP22; } FSPT_UPD_COMMON_FSP22;
/// ///
@ -227,11 +227,11 @@ typedef struct {
/// ///
/// FSP_UPD_HEADER Configuration. /// FSP_UPD_HEADER Configuration.
/// ///
FSP_UPD_HEADER FspUpdHeader; FSP_UPD_HEADER FspUpdHeader;
/// ///
/// FSPM_ARCH_UPD Configuration. /// FSPM_ARCH_UPD Configuration.
/// ///
FSPM_ARCH_UPD FspmArchUpd; FSPM_ARCH_UPD FspmArchUpd;
} FSPM_UPD_COMMON; } FSPM_UPD_COMMON;
/// ///
@ -241,7 +241,7 @@ typedef struct {
/// ///
/// FSP_UPD_HEADER Configuration. /// FSP_UPD_HEADER Configuration.
/// ///
FSP_UPD_HEADER FspUpdHeader; FSP_UPD_HEADER FspUpdHeader;
} FSPS_UPD_COMMON; } FSPS_UPD_COMMON;
/// ///
@ -251,12 +251,12 @@ typedef struct {
/// ///
/// FSP_UPD_HEADER Configuration. /// FSP_UPD_HEADER Configuration.
/// ///
FSP_UPD_HEADER FspUpdHeader; FSP_UPD_HEADER FspUpdHeader;
/// ///
/// FSPS_ARCH_UPD Configuration. /// FSPS_ARCH_UPD Configuration.
/// ///
FSPS_ARCH_UPD FspsArchUpd; FSPS_ARCH_UPD FspsArchUpd;
} FSPS_UPD_COMMON_FSP22; } FSPS_UPD_COMMON_FSP22;
/// ///
@ -273,13 +273,13 @@ typedef enum {
/// This stage is notified just before the bootloader hand-off /// This stage is notified just before the bootloader hand-off
/// to the OS loader. /// to the OS loader.
/// ///
EnumInitPhaseReadyToBoot = 0x40, EnumInitPhaseReadyToBoot = 0x40,
/// ///
/// This stage is notified just before the firmware/Preboot /// This stage is notified just before the firmware/Preboot
/// environment transfers management of all system resources /// environment transfers management of all system resources
/// to the OS or next level execution environment. /// to the OS or next level execution environment.
/// ///
EnumInitPhaseEndOfFirmware = 0xF0 EnumInitPhaseEndOfFirmware = 0xF0
} FSP_INIT_PHASE; } FSP_INIT_PHASE;
/// ///
@ -289,15 +289,15 @@ typedef struct {
/// ///
/// Notification phase used for NotifyPhase API /// Notification phase used for NotifyPhase API
/// ///
FSP_INIT_PHASE Phase; FSP_INIT_PHASE Phase;
} NOTIFY_PHASE_PARAMS; } NOTIFY_PHASE_PARAMS;
/// ///
/// Action definition for FspMultiPhaseSiInit API /// Action definition for FspMultiPhaseSiInit API
/// ///
typedef enum { typedef enum {
EnumMultiPhaseGetNumberOfPhases = 0x0, EnumMultiPhaseGetNumberOfPhases = 0x0,
EnumMultiPhaseExecutePhase = 0x1 EnumMultiPhaseExecutePhase = 0x1
} FSP_MULTI_PHASE_ACTION; } FSP_MULTI_PHASE_ACTION;
/// ///
@ -305,8 +305,8 @@ typedef enum {
/// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases) /// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases)
/// ///
typedef struct { typedef struct {
UINT32 NumberOfPhases; UINT32 NumberOfPhases;
UINT32 PhasesExecuted; UINT32 PhasesExecuted;
} FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS; } FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS;
/// ///
@ -321,9 +321,9 @@ typedef struct {
/// - MultiPhaseParamPtr shall be NULL. /// - MultiPhaseParamPtr shall be NULL.
/// ///
typedef struct { typedef struct {
IN FSP_MULTI_PHASE_ACTION MultiPhaseAction; IN FSP_MULTI_PHASE_ACTION MultiPhaseAction;
IN UINT32 PhaseIndex; IN UINT32 PhaseIndex;
IN OUT VOID *MultiPhaseParamPtr; IN OUT VOID *MultiPhaseParamPtr;
} FSP_MULTI_PHASE_PARAMS; } FSP_MULTI_PHASE_PARAMS;
#pragma pack() #pragma pack()
@ -359,7 +359,7 @@ typedef struct {
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *FSP_TEMP_RAM_INIT) ( (EFIAPI *FSP_TEMP_RAM_INIT)(
IN VOID *FsptUpdDataPtr IN VOID *FsptUpdDataPtr
); );
@ -379,7 +379,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *FSP_NOTIFY_PHASE) ( (EFIAPI *FSP_NOTIFY_PHASE)(
IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr
); );
@ -407,12 +407,11 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *FSP_MEMORY_INIT) ( (EFIAPI *FSP_MEMORY_INIT)(
IN VOID *FspmUpdDataPtr, IN VOID *FspmUpdDataPtr,
OUT VOID **HobListPtr OUT VOID **HobListPtr
); );
/** /**
This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary
memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure
@ -433,11 +432,10 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *FSP_TEMP_RAM_EXIT) ( (EFIAPI *FSP_TEMP_RAM_EXIT)(
IN VOID *TempRamExitParamPtr IN VOID *TempRamExitParamPtr
); );
/** /**
This FSP API is called after TempRamExit API. This FSP API is called after TempRamExit API.
FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the
@ -454,7 +452,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *FSP_SILICON_INIT) ( (EFIAPI *FSP_SILICON_INIT)(
IN VOID *FspsUpdDataPtr IN VOID *FspsUpdDataPtr
); );
@ -478,8 +476,8 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *FSP_MULTI_PHASE_SI_INIT) ( (EFIAPI *FSP_MULTI_PHASE_SI_INIT)(
IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr
); );
#endif #endif

84
IntelFsp2Pkg/Include/FspGlobalData.h
View File

@ -10,8 +10,8 @@
#include <FspEas.h> #include <FspEas.h>
#define FSP_IN_API_MODE 0 #define FSP_IN_API_MODE 0
#define FSP_IN_DISPATCH_MODE 1 #define FSP_IN_DISPATCH_MODE 1
#pragma pack(1) #pragma pack(1)
@ -27,50 +27,50 @@ typedef enum {
} FSP_API_INDEX; } FSP_API_INDEX;
typedef struct { typedef struct {
VOID *DataPtr; VOID *DataPtr;
UINT32 MicrocodeRegionBase; UINT32 MicrocodeRegionBase;
UINT32 MicrocodeRegionSize; UINT32 MicrocodeRegionSize;
UINT32 CodeRegionBase; UINT32 CodeRegionBase;
UINT32 CodeRegionSize; UINT32 CodeRegionSize;
} FSP_PLAT_DATA; } FSP_PLAT_DATA;
#define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D') #define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')
#define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F') #define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F')
#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF #define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF
typedef struct { typedef struct {
UINT32 Signature; UINT32 Signature;
UINT8 Version; UINT8 Version;
UINT8 Reserved1[3]; UINT8 Reserved1[3];
UINT32 CoreStack; UINT32 CoreStack;
UINT32 StatusCode; UINT32 StatusCode;
UINT32 Reserved2[8]; UINT32 Reserved2[8];
FSP_PLAT_DATA PlatformData; FSP_PLAT_DATA PlatformData;
FSP_INFO_HEADER *FspInfoHeader; FSP_INFO_HEADER *FspInfoHeader;
VOID *UpdDataPtr; VOID *UpdDataPtr;
VOID *TempRamInitUpdPtr; VOID *TempRamInitUpdPtr;
VOID *MemoryInitUpdPtr; VOID *MemoryInitUpdPtr;
VOID *SiliconInitUpdPtr; VOID *SiliconInitUpdPtr;
UINT8 ApiIdx; UINT8 ApiIdx;
/// ///
/// 0: FSP in API mode; 1: FSP in DISPATCH mode /// 0: FSP in API mode; 1: FSP in DISPATCH mode
/// ///
UINT8 FspMode; UINT8 FspMode;
UINT8 OnSeparateStack; UINT8 OnSeparateStack;
UINT8 Reserved3; UINT8 Reserved3;
UINT32 NumberOfPhases; UINT32 NumberOfPhases;
UINT32 PhasesExecuted; UINT32 PhasesExecuted;
/// ///
/// To store function parameters pointer /// To store function parameters pointer
/// so it can be retrieved after stack switched. /// so it can be retrieved after stack switched.
/// ///
VOID *FunctionParameterPtr; VOID *FunctionParameterPtr;
UINT8 Reserved4[16]; UINT8 Reserved4[16];
UINT32 PerfSig; UINT32 PerfSig;
UINT16 PerfLen; UINT16 PerfLen;
UINT16 Reserved5; UINT16 Reserved5;
UINT32 PerfIdx; UINT32 PerfIdx;
UINT64 PerfData[32]; UINT64 PerfData[32];
} FSP_GLOBAL_DATA; } FSP_GLOBAL_DATA;
#pragma pack() #pragma pack()

48
IntelFsp2Pkg/Include/FspMeasurePointId.h
View File

@ -11,44 +11,44 @@
// //
// 0xD0 - 0xEF are reserved for FSP common measure point // 0xD0 - 0xEF are reserved for FSP common measure point
// //
#define FSP_PERF_ID_MRC_INIT_ENTRY 0xD0 #define FSP_PERF_ID_MRC_INIT_ENTRY 0xD0
#define FSP_PERF_ID_MRC_INIT_EXIT (FSP_PERF_ID_MRC_INIT_ENTRY + 1) #define FSP_PERF_ID_MRC_INIT_EXIT (FSP_PERF_ID_MRC_INIT_ENTRY + 1)
#define FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY 0xD8 #define FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY 0xD8
#define FSP_PERF_ID_SYSTEM_AGENT_INIT_EXIT (FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY + 1) #define FSP_PERF_ID_SYSTEM_AGENT_INIT_EXIT (FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY + 1)
#define FSP_PERF_ID_PCH_INIT_ENTRY 0xDA #define FSP_PERF_ID_PCH_INIT_ENTRY 0xDA
#define FSP_PERF_ID_PCH_INIT_EXIT (FSP_PERF_ID_PCH_INIT_ENTRY + 1) #define FSP_PERF_ID_PCH_INIT_EXIT (FSP_PERF_ID_PCH_INIT_ENTRY + 1)
#define FSP_PERF_ID_CPU_INIT_ENTRY 0xE0 #define FSP_PERF_ID_CPU_INIT_ENTRY 0xE0
#define FSP_PERF_ID_CPU_INIT_EXIT (FSP_PERF_ID_CPU_INIT_ENTRY + 1) #define FSP_PERF_ID_CPU_INIT_EXIT (FSP_PERF_ID_CPU_INIT_ENTRY + 1)
#define FSP_PERF_ID_GFX_INIT_ENTRY 0xE8 #define FSP_PERF_ID_GFX_INIT_ENTRY 0xE8
#define FSP_PERF_ID_GFX_INIT_EXIT (FSP_PERF_ID_GFX_INIT_ENTRY + 1) #define FSP_PERF_ID_GFX_INIT_EXIT (FSP_PERF_ID_GFX_INIT_ENTRY + 1)
#define FSP_PERF_ID_ME_INIT_ENTRY 0xEA #define FSP_PERF_ID_ME_INIT_ENTRY 0xEA
#define FSP_PERF_ID_ME_INIT_EXIT (FSP_PERF_ID_ME_INIT_ENTRY + 1) #define FSP_PERF_ID_ME_INIT_EXIT (FSP_PERF_ID_ME_INIT_ENTRY + 1)
// //
// 0xF0 - 0xFF are reserved for FSP API // 0xF0 - 0xFF are reserved for FSP API
// //
#define FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY 0xF0 #define FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY 0xF0
#define FSP_PERF_ID_API_TEMP_RAM_INIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY + 1) #define FSP_PERF_ID_API_TEMP_RAM_INIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY + 1)
#define FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY 0xF2 #define FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY 0xF2
#define FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY + 1) #define FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY + 1)
#define FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY 0xF4 #define FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY 0xF4
#define FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY + 1) #define FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY + 1)
#define FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY 0xF6 #define FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY 0xF6
#define FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY + 1) #define FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY + 1)
#define FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY 0xF8 #define FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY 0xF8
#define FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + 1) #define FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + 1)
#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY 0xFA #define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY 0xFA
#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_EXIT (FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY + 1) #define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_EXIT (FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY + 1)
#define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY 0xFC #define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY 0xFC
#define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_EXIT (FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY + 1) #define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_EXIT (FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY + 1)

34
IntelFsp2Pkg/Include/FspStatusCode.h
View File

@ -12,29 +12,29 @@
// //
// FSP API - 4 BITS // FSP API - 4 BITS
// //
#define FSP_STATUS_CODE_TEMP_RAM_INIT 0xF000 #define FSP_STATUS_CODE_TEMP_RAM_INIT 0xF000
#define FSP_STATUS_CODE_MEMORY_INIT 0xD000 #define FSP_STATUS_CODE_MEMORY_INIT 0xD000
#define FSP_STATUS_CODE_TEMP_RAM_EXIT 0xB000 #define FSP_STATUS_CODE_TEMP_RAM_EXIT 0xB000
#define FSP_STATUS_CODE_SILICON_INIT 0x9000 #define FSP_STATUS_CODE_SILICON_INIT 0x9000
#define FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION 0x6000 #define FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION 0x6000
#define FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION 0x4000 #define FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION 0x4000
#define FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION 0x2000 #define FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION 0x2000
// //
// MODULE - 4 BITS // MODULE - 4 BITS
// //
#define FSP_STATUS_CODE_GFX_PEIM 0x0700 #define FSP_STATUS_CODE_GFX_PEIM 0x0700
#define FSP_STATUS_CODE_COMMON_CODE 0x0800 #define FSP_STATUS_CODE_COMMON_CODE 0x0800
#define FSP_STATUS_CODE_SILICON_COMMON_CODE 0x0900 #define FSP_STATUS_CODE_SILICON_COMMON_CODE 0x0900
#define FSP_STATUS_CODE_SYSTEM_AGENT 0x0A00 #define FSP_STATUS_CODE_SYSTEM_AGENT 0x0A00
#define FSP_STATUS_CODE_PCH 0x0B00 #define FSP_STATUS_CODE_PCH 0x0B00
#define FSP_STATUS_CODE_CPU 0x0C00 #define FSP_STATUS_CODE_CPU 0x0C00
#define FSP_STATUS_CODE_MRC 0x0D00 #define FSP_STATUS_CODE_MRC 0x0D00
#define FSP_STATUS_CODE_ME_BIOS 0x0E00 #define FSP_STATUS_CODE_ME_BIOS 0x0E00
// //
// Individual Codes - 1 BYTE // Individual Codes - 1 BYTE
// //
#define FSP_STATUS_CODE_API_ENTRY 0x0000 #define FSP_STATUS_CODE_API_ENTRY 0x0000
#define FSP_STATUS_CODE_API_EXIT 0x007F #define FSP_STATUS_CODE_API_EXIT 0x007F
#endif #endif

80
IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
View File

@ -10,7 +10,7 @@
#ifndef __FSP_HEADER_FILE_H__ #ifndef __FSP_HEADER_FILE_H__
#define __FSP_HEADER_FILE_H__ #define __FSP_HEADER_FILE_H__
#define FSP_HEADER_REVISION_3 3 #define FSP_HEADER_REVISION_3 3
#define FSPE_HEADER_REVISION_1 1 #define FSPE_HEADER_REVISION_1 1
#define FSPP_HEADER_REVISION_1 1 #define FSPP_HEADER_REVISION_1 1
@ -18,7 +18,7 @@
/// ///
/// Fixed FSP header offset in the FSP image /// Fixed FSP header offset in the FSP image
/// ///
#define FSP_INFO_HEADER_OFF 0x94 #define FSP_INFO_HEADER_OFF 0x94
#define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x #define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x
@ -33,25 +33,25 @@ typedef struct {
/// ///
/// Byte 0x00: Signature ('FSPH') for the FSP Information Header. /// Byte 0x00: Signature ('FSPH') for the FSP Information Header.
/// ///
UINT32 Signature; UINT32 Signature;
/// ///
/// Byte 0x04: Length of the FSP Information Header. /// Byte 0x04: Length of the FSP Information Header.
/// ///
UINT32 HeaderLength; UINT32 HeaderLength;
/// ///
/// Byte 0x08: Reserved. /// Byte 0x08: Reserved.
/// ///
UINT8 Reserved1[2]; UINT8 Reserved1[2];
/// ///
/// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format. /// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.
/// For revision v2.3 the value will be 0x23. /// For revision v2.3 the value will be 0x23.
/// ///
UINT8 SpecVersion; UINT8 SpecVersion;
/// ///
/// Byte 0x0B: Revision of the FSP Information Header. /// Byte 0x0B: Revision of the FSP Information Header.
/// The Current value for this field is 0x6. /// The Current value for this field is 0x6.
/// ///
UINT8 HeaderRevision; UINT8 HeaderRevision;
/// ///
/// Byte 0x0C: Revision of the FSP binary. /// Byte 0x0C: Revision of the FSP binary.
/// Major.Minor.Revision.Build /// Major.Minor.Revision.Build
@ -67,69 +67,69 @@ typedef struct {
/// 23 : 16 - Minor Version /// 23 : 16 - Minor Version
/// 31 : 24 - Major Version /// 31 : 24 - Major Version
/// ///
UINT32 ImageRevision; UINT32 ImageRevision;
/// ///
/// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration. /// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration.
/// ///
CHAR8 ImageId[8]; CHAR8 ImageId[8];
/// ///
/// Byte 0x18: Size of the entire FSP binary. /// Byte 0x18: Size of the entire FSP binary.
/// ///
UINT32 ImageSize; UINT32 ImageSize;
/// ///
/// Byte 0x1C: FSP binary preferred base address. /// Byte 0x1C: FSP binary preferred base address.
/// ///
UINT32 ImageBase; UINT32 ImageBase;
/// ///
/// Byte 0x20: Attribute for the FSP binary. /// Byte 0x20: Attribute for the FSP binary.
/// ///
UINT16 ImageAttribute; UINT16 ImageAttribute;
/// ///
/// Byte 0x22: Attributes of the FSP Component. /// Byte 0x22: Attributes of the FSP Component.
/// ///
UINT16 ComponentAttribute; UINT16 ComponentAttribute;
/// ///
/// Byte 0x24: Offset of the FSP configuration region. /// Byte 0x24: Offset of the FSP configuration region.
/// ///
UINT32 CfgRegionOffset; UINT32 CfgRegionOffset;
/// ///
/// Byte 0x28: Size of the FSP configuration region. /// Byte 0x28: Size of the FSP configuration region.
/// ///
UINT32 CfgRegionSize; UINT32 CfgRegionSize;
/// ///
/// Byte 0x2C: Reserved2. /// Byte 0x2C: Reserved2.
/// ///
UINT32 Reserved2; UINT32 Reserved2;
/// ///
/// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized. /// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized.
/// ///
UINT32 TempRamInitEntryOffset; UINT32 TempRamInitEntryOffset;
/// ///
/// Byte 0x34: Reserved3. /// Byte 0x34: Reserved3.
/// ///
UINT32 Reserved3; UINT32 Reserved3;
/// ///
/// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process. /// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process.
/// ///
UINT32 NotifyPhaseEntryOffset; UINT32 NotifyPhaseEntryOffset;
/// ///
/// Byte 0x3C: The offset for the API to initialize the memory. /// Byte 0x3C: The offset for the API to initialize the memory.
/// ///
UINT32 FspMemoryInitEntryOffset; UINT32 FspMemoryInitEntryOffset;
/// ///
/// Byte 0x40: The offset for the API to tear down temporary RAM. /// Byte 0x40: The offset for the API to tear down temporary RAM.
/// ///
UINT32 TempRamExitEntryOffset; UINT32 TempRamExitEntryOffset;
/// ///
/// Byte 0x44: The offset for the API to initialize the CPU and chipset. /// Byte 0x44: The offset for the API to initialize the CPU and chipset.
/// ///
UINT32 FspSiliconInitEntryOffset; UINT32 FspSiliconInitEntryOffset;
/// ///
/// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization. /// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization.
/// This value is only valid if FSP HeaderRevision is >= 5. /// This value is only valid if FSP HeaderRevision is >= 5.
/// If the value is set to 0x00000000, then this API is not available in this component. /// If the value is set to 0x00000000, then this API is not available in this component.
/// ///
UINT32 FspMultiPhaseSiInitEntryOffset; UINT32 FspMultiPhaseSiInitEntryOffset;
/// ///
/// Byte 0x4C: Extended revision of the FSP binary. /// Byte 0x4C: Extended revision of the FSP binary.
/// This value is only valid if FSP HeaderRevision is >= 6. /// This value is only valid if FSP HeaderRevision is >= 6.
@ -142,11 +142,11 @@ typedef struct {
/// Minor Version = ImageRevision[23:16] /// Minor Version = ImageRevision[23:16]
/// Major Version = ImageRevision[31:24] /// Major Version = ImageRevision[31:24]
/// ///
UINT16 ExtendedImageRevision; UINT16 ExtendedImageRevision;
/// ///
/// Byte 0x4E: Reserved4. /// Byte 0x4E: Reserved4.
/// ///
UINT16 Reserved4; UINT16 Reserved4;
} FSP_INFO_HEADER; } FSP_INFO_HEADER;
/// ///
@ -161,31 +161,31 @@ typedef struct {
/// ///
/// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header. /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header.
/// ///
UINT32 Signature; UINT32 Signature;
/// ///
/// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data. /// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.
/// ///
UINT32 Length; UINT32 Length;
/// ///
/// Byte 0x08: FSP producer defined revision of the table. /// Byte 0x08: FSP producer defined revision of the table.
/// ///
UINT8 Revision; UINT8 Revision;
/// ///
/// Byte 0x09: Reserved for future use. /// Byte 0x09: Reserved for future use.
/// ///
UINT8 Reserved; UINT8 Reserved;
/// ///
/// Byte 0x0A: FSP producer identification string /// Byte 0x0A: FSP producer identification string
/// ///
CHAR8 FspProducerId[6]; CHAR8 FspProducerId[6];
/// ///
/// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions. /// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.
/// ///
UINT32 FspProducerRevision; UINT32 FspProducerRevision;
/// ///
/// Byte 0x14: Size of the FSP producer defined data (n) in bytes. /// Byte 0x14: Size of the FSP producer defined data (n) in bytes.
/// ///
UINT32 FspProducerDataSize; UINT32 FspProducerDataSize;
/// ///
/// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize. /// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.
/// ///
@ -195,7 +195,7 @@ typedef struct {
// A generic table search algorithm for additional tables can be implemented with a // A generic table search algorithm for additional tables can be implemented with a
// signature search algorithm until a terminator signature 'FSPP' is found. // signature search algorithm until a terminator signature 'FSPP' is found.
// //
#define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P') #define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P')
#define FSP_PATCH_TABLE_SIGNATURE FSP_FSPP_SIGNATURE #define FSP_PATCH_TABLE_SIGNATURE FSP_FSPP_SIGNATURE
/// ///
@ -205,31 +205,31 @@ typedef struct {
/// ///
/// Byte 0x00: FSP Patch Table Signature "FSPP". /// Byte 0x00: FSP Patch Table Signature "FSPP".
/// ///
UINT32 Signature; UINT32 Signature;
/// ///
/// Byte 0x04: Size including the PatchData. /// Byte 0x04: Size including the PatchData.
/// ///
UINT16 HeaderLength; UINT16 HeaderLength;
/// ///
/// Byte 0x06: Revision is set to 0x01. /// Byte 0x06: Revision is set to 0x01.
/// ///
UINT8 HeaderRevision; UINT8 HeaderRevision;
/// ///
/// Byte 0x07: Reserved for future use. /// Byte 0x07: Reserved for future use.
/// ///
UINT8 Reserved; UINT8 Reserved;
/// ///
/// Byte 0x08: Number of entries to Patch. /// Byte 0x08: Number of entries to Patch.
/// ///
UINT32 PatchEntryNum; UINT32 PatchEntryNum;
/// ///
/// Byte 0x0C: Patch Data. /// Byte 0x0C: Patch Data.
/// ///
//UINT32 PatchData[]; // UINT32 PatchData[];
} FSP_PATCH_TABLE; } FSP_PATCH_TABLE;
#pragma pack() #pragma pack()
extern EFI_GUID gFspHeaderFileGuid; extern EFI_GUID gFspHeaderFileGuid;
#endif #endif

8
IntelFsp2Pkg/Include/Guid/FspNonVolatileStorageHob2.h
View File

@ -14,11 +14,11 @@
/// The Non-Volatile Storage (NVS) HOB version 2 provides > 64KB buffer support. /// The Non-Volatile Storage (NVS) HOB version 2 provides > 64KB buffer support.
/// ///
typedef struct { typedef struct {
EFI_HOB_GUID_TYPE GuidHob; EFI_HOB_GUID_TYPE GuidHob;
EFI_PHYSICAL_ADDRESS NvsDataPtr; EFI_PHYSICAL_ADDRESS NvsDataPtr;
UINT64 NvsDataLength; UINT64 NvsDataLength;
} FSP_NON_VOLATILE_STORAGE_HOB2; } FSP_NON_VOLATILE_STORAGE_HOB2;
extern EFI_GUID gFspNonVolatileStorageHob2Guid; extern EFI_GUID gFspNonVolatileStorageHob2Guid;
#endif #endif

6
IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h
View File

@ -10,8 +10,8 @@
#ifndef __GUID_HOB_FSP_EAS_GUID__ #ifndef __GUID_HOB_FSP_EAS_GUID__
#define __GUID_HOB_FSP_EAS_GUID__ #define __GUID_HOB_FSP_EAS_GUID__
extern EFI_GUID gFspBootLoaderTolumHobGuid; extern EFI_GUID gFspBootLoaderTolumHobGuid;
extern EFI_GUID gFspReservedMemoryResourceHobGuid; extern EFI_GUID gFspReservedMemoryResourceHobGuid;
extern EFI_GUID gFspNonVolatileStorageHobGuid; extern EFI_GUID gFspNonVolatileStorageHobGuid;
#endif #endif

3
IntelFsp2Pkg/Include/Library/CacheAsRamLib.h
View File

@ -17,8 +17,7 @@
VOID VOID
EFIAPI EFIAPI
DisableCacheAsRam ( DisableCacheAsRam (
IN BOOLEAN DisableCar IN BOOLEAN DisableCar
); );
#endif #endif

17
IntelFsp2Pkg/Include/Library/CacheLib.h
View File

@ -13,11 +13,11 @@
// //
typedef INT32 EFI_MEMORY_CACHE_TYPE; typedef INT32 EFI_MEMORY_CACHE_TYPE;
#define EFI_CACHE_UNCACHEABLE 0 #define EFI_CACHE_UNCACHEABLE 0
#define EFI_CACHE_WRITECOMBINING 1 #define EFI_CACHE_WRITECOMBINING 1
#define EFI_CACHE_WRITETHROUGH 4 #define EFI_CACHE_WRITETHROUGH 4
#define EFI_CACHE_WRITEPROTECTED 5 #define EFI_CACHE_WRITEPROTECTED 5
#define EFI_CACHE_WRITEBACK 6 #define EFI_CACHE_WRITEBACK 6
/** /**
Reset all the MTRRs to a known state. Reset all the MTRRs to a known state.
@ -47,10 +47,9 @@ ResetCacheAttributes (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
SetCacheAttributes ( SetCacheAttributes (
IN EFI_PHYSICAL_ADDRESS MemoryAddress, IN EFI_PHYSICAL_ADDRESS MemoryAddress,
IN UINT64 MemoryLength, IN UINT64 MemoryLength,
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
); );
#endif #endif

22
IntelFsp2Pkg/Include/Library/FspCommonLib.h
View File

@ -20,7 +20,7 @@
VOID VOID
EFIAPI EFIAPI
SetFspGlobalDataPointer ( SetFspGlobalDataPointer (
IN FSP_GLOBAL_DATA *FspData IN FSP_GLOBAL_DATA *FspData
); );
/** /**
@ -60,7 +60,7 @@ GetFspApiParameter2 (
@retval FSP entry stack pointer. @retval FSP entry stack pointer.
**/ **/
VOID* VOID *
EFIAPI EFIAPI
GetFspEntryStack ( GetFspEntryStack (
VOID VOID
@ -75,7 +75,7 @@ GetFspEntryStack (
VOID VOID
EFIAPI EFIAPI
SetFspApiParameter ( SetFspApiParameter (
IN UINT32 Value IN UINT32 Value
); );
/** /**
@ -99,7 +99,7 @@ SetFspApiReturnStatus (
VOID VOID
EFIAPI EFIAPI
SetFspCoreStackPointer ( SetFspCoreStackPointer (
IN VOID *NewStackTop IN VOID *NewStackTop
); );
/** /**
@ -111,7 +111,7 @@ SetFspCoreStackPointer (
VOID VOID
EFIAPI EFIAPI
SetFspPlatformDataPointer ( SetFspPlatformDataPointer (
IN VOID *PlatformData IN VOID *PlatformData
); );
/** /**
@ -134,7 +134,7 @@ GetFspPlatformDataPointer (
VOID VOID
EFIAPI EFIAPI
SetFspUpdDataPointer ( SetFspUpdDataPointer (
IN VOID *UpdDataPtr IN VOID *UpdDataPtr
); );
/** /**
@ -156,7 +156,7 @@ GetFspUpdDataPointer (
VOID VOID
EFIAPI EFIAPI
SetFspMemoryInitUpdDataPointer ( SetFspMemoryInitUpdDataPointer (
IN VOID *MemoryInitUpdPtr IN VOID *MemoryInitUpdPtr
); );
/** /**
@ -178,7 +178,7 @@ GetFspMemoryInitUpdDataPointer (
VOID VOID
EFIAPI EFIAPI
SetFspSiliconInitUpdDataPointer ( SetFspSiliconInitUpdDataPointer (
IN VOID *SiliconInitUpdPtr IN VOID *SiliconInitUpdPtr
); );
/** /**
@ -224,7 +224,7 @@ GetFspInfoHeader (
VOID VOID
EFIAPI EFIAPI
SetFspInfoHeader ( SetFspInfoHeader (
FSP_INFO_HEADER *FspInfoHeader FSP_INFO_HEADER *FspInfoHeader
); );
/** /**
@ -282,7 +282,6 @@ GetPhaseStatusCode (
VOID VOID
); );
/** /**
This function sets FSP Phase StatusCode. This function sets FSP Phase StatusCode.
@ -303,6 +302,7 @@ SetPhaseStatusCode (
VOID VOID
EFIAPI EFIAPI
FspApiReturnStatusReset ( FspApiReturnStatusReset (
IN UINT32 FspResetType IN UINT32 FspResetType
); );
#endif #endif

17
IntelFsp2Pkg/Include/Library/FspPlatformLib.h
View File

@ -16,7 +16,7 @@
EFI_HOB_RESOURCE_DESCRIPTOR * EFI_HOB_RESOURCE_DESCRIPTOR *
EFIAPI EFIAPI
FspGetResourceDescriptorByOwner ( FspGetResourceDescriptorByOwner (
IN EFI_GUID *OwnerGuid IN EFI_GUID *OwnerGuid
); );
/** /**
@ -28,11 +28,10 @@ FspGetResourceDescriptorByOwner (
VOID VOID
EFIAPI EFIAPI
FspGetSystemMemorySize ( FspGetSystemMemorySize (
IN OUT UINT64 *LowMemoryLength, IN OUT UINT64 *LowMemoryLength,
IN OUT UINT64 *HighMemoryLength IN OUT UINT64 *HighMemoryLength
); );
/** /**
Set a new stack frame for the continuation function. Set a new stack frame for the continuation function.
@ -61,7 +60,7 @@ FspSiliconInitDone (
VOID VOID
EFIAPI EFIAPI
FspMemoryInitDone ( FspMemoryInitDone (
IN OUT VOID **HobListPtr IN OUT VOID **HobListPtr
); );
/** /**
@ -95,7 +94,7 @@ FspWaitForNotify (
VOID VOID
EFIAPI EFIAPI
FspSiliconInitDone2 ( FspSiliconInitDone2 (
IN EFI_STATUS Status IN EFI_STATUS Status
); );
/** /**
@ -107,8 +106,8 @@ FspSiliconInitDone2 (
VOID VOID
EFIAPI EFIAPI
FspMemoryInitDone2 ( FspMemoryInitDone2 (
IN EFI_STATUS Status, IN EFI_STATUS Status,
IN OUT VOID **HobListPtr IN OUT VOID **HobListPtr
); );
/** /**
@ -119,7 +118,7 @@ FspMemoryInitDone2 (
VOID VOID
EFIAPI EFIAPI
FspTempRamExitDone2 ( FspTempRamExitDone2 (
IN EFI_STATUS Status IN EFI_STATUS Status
); );
#endif #endif

12
IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h
View File

@ -43,7 +43,7 @@ SecPlatformInit (
UINT32 UINT32
EFIAPI EFIAPI
LoadMicrocode ( LoadMicrocode (
IN VOID *FsptUpdDataPtr IN VOID *FsptUpdDataPtr
); );
/** /**
@ -62,7 +62,7 @@ LoadMicrocode (
UINT32 UINT32
EFIAPI EFIAPI
SecCarInit ( SecCarInit (
IN VOID *FsptUpdDataPtr IN VOID *FsptUpdDataPtr
); );
/** /**
@ -75,8 +75,8 @@ SecCarInit (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FspUpdSignatureCheck ( FspUpdSignatureCheck (
IN UINT32 ApiIdx, IN UINT32 ApiIdx,
IN VOID *ApiParam IN VOID *ApiParam
); );
/** /**
@ -89,8 +89,8 @@ FspUpdSignatureCheck (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FspMultiPhaseSiInitApiHandler ( FspMultiPhaseSiInitApiHandler (
IN UINT32 ApiIdx, IN UINT32 ApiIdx,
IN VOID *ApiParam IN VOID *ApiParam
); );
#endif #endif

14
IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
View File

@ -10,7 +10,7 @@
#ifndef _FSPM_ARCH_CONFIG_PPI_H_ #ifndef _FSPM_ARCH_CONFIG_PPI_H_
#define _FSPM_ARCH_CONFIG_PPI_H_ #define _FSPM_ARCH_CONFIG_PPI_H_
#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1 #define FSPM_ARCH_CONFIG_PPI_REVISION 0x1
/// ///
/// Global ID for the FSPM_ARCH_CONFIG_PPI. /// Global ID for the FSPM_ARCH_CONFIG_PPI.
@ -27,21 +27,21 @@ typedef struct {
/// ///
/// Revision of the structure /// Revision of the structure
/// ///
UINT8 Revision; UINT8 Revision;
UINT8 Reserved[3]; UINT8 Reserved[3];
/// ///
/// Pointer to the non-volatile storage (NVS) data buffer. /// Pointer to the non-volatile storage (NVS) data buffer.
/// If it is NULL it indicates the NVS data is not available. /// If it is NULL it indicates the NVS data is not available.
/// ///
VOID *NvsBufferPtr; VOID *NvsBufferPtr;
/// ///
/// Size of memory to be reserved by FSP below "top /// Size of memory to be reserved by FSP below "top
/// of low usable memory" for bootloader usage. /// of low usable memory" for bootloader usage.
/// ///
UINT32 BootLoaderTolumSize; UINT32 BootLoaderTolumSize;
UINT8 Reserved1[4]; UINT8 Reserved1[4];
} FSPM_ARCH_CONFIG_PPI; } FSPM_ARCH_CONFIG_PPI;
extern EFI_GUID gFspmArchConfigPpiGuid; extern EFI_GUID gFspmArchConfigPpiGuid;
#endif // _FSPM_ARCH_CONFIG_PPI_H_ #endif // _FSPM_ARCH_CONFIG_PPI_H_

6
IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
View File

@ -36,7 +36,7 @@ typedef struct _FSP_TEMP_RAM_EXIT_PPI FSP_TEMP_RAM_EXIT_PPI;
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *FSP_TEMP_RAM_EXIT) ( (EFIAPI *FSP_TEMP_RAM_EXIT)(
IN VOID *TempRamExitParamPtr IN VOID *TempRamExitParamPtr
); );
@ -44,9 +44,9 @@ EFI_STATUS
/// This PPI provides function to disable temporary memory. /// This PPI provides function to disable temporary memory.
/// ///
struct _FSP_TEMP_RAM_EXIT_PPI { struct _FSP_TEMP_RAM_EXIT_PPI {
FSP_TEMP_RAM_EXIT TempRamExit; FSP_TEMP_RAM_EXIT TempRamExit;
}; };
extern EFI_GUID gFspTempRamExitPpiGuid; extern EFI_GUID gFspTempRamExitPpiGuid;
#endif // _FSP_TEMP_RAM_EXIT_PPI_H_ #endif // _FSP_TEMP_RAM_EXIT_PPI_H_

6
IntelFsp2Pkg/Library/BaseCacheAsRamLibNull/DisableCacheAsRamNull.c
View File

@ -18,7 +18,7 @@
VOID VOID
EFIAPI EFIAPI
DisableCacheAsRam ( DisableCacheAsRam (
IN BOOLEAN DisableCar IN BOOLEAN DisableCar
) )
{ {
// //
@ -28,8 +28,8 @@ DisableCacheAsRam (
if (DisableCar) { if (DisableCar) {
AsmInvd (); AsmInvd ();
} else { } else {
AsmWbinvd(); AsmWbinvd ();
} }
return ; return;
} }

288
IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
View File

@ -26,11 +26,11 @@
**/ **/
EFI_STATUS EFI_STATUS
SearchForExactMtrr ( SearchForExactMtrr (
IN EFI_PHYSICAL_ADDRESS MemoryAddress, IN EFI_PHYSICAL_ADDRESS MemoryAddress,
IN UINT64 MemoryLength, IN UINT64 MemoryLength,
IN UINT64 ValidMtrrAddressMask, IN UINT64 ValidMtrrAddressMask,
OUT UINT32 *UsedMsrNum, OUT UINT32 *UsedMsrNum,
OUT EFI_MEMORY_CACHE_TYPE *MemoryCacheType OUT EFI_MEMORY_CACHE_TYPE *MemoryCacheType
); );
/** /**
@ -43,7 +43,7 @@ SearchForExactMtrr (
**/ **/
BOOLEAN BOOLEAN
IsDefaultType ( IsDefaultType (
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
); );
/** /**
@ -58,8 +58,8 @@ IsDefaultType (
**/ **/
UINT32 UINT32
CheckMtrrAlignment ( CheckMtrrAlignment (
IN UINT64 BaseAddress, IN UINT64 BaseAddress,
IN UINT64 Size IN UINT64 Size
); );
typedef struct { typedef struct {
@ -68,18 +68,18 @@ typedef struct {
UINT32 Length; UINT32 Length;
} EFI_FIXED_MTRR; } EFI_FIXED_MTRR;
EFI_FIXED_MTRR mFixedMtrrTable[] = { EFI_FIXED_MTRR mFixedMtrrTable[] = {
{ EFI_MSR_IA32_MTRR_FIX64K_00000, 0, 0x10000}, { EFI_MSR_IA32_MTRR_FIX64K_00000, 0, 0x10000 },
{ EFI_MSR_IA32_MTRR_FIX16K_80000, 0x80000, 0x4000}, { EFI_MSR_IA32_MTRR_FIX16K_80000, 0x80000, 0x4000 },
{ EFI_MSR_IA32_MTRR_FIX16K_A0000, 0xA0000, 0x4000}, { EFI_MSR_IA32_MTRR_FIX16K_A0000, 0xA0000, 0x4000 },
{ EFI_MSR_IA32_MTRR_FIX4K_C0000, 0xC0000, 0x1000}, { EFI_MSR_IA32_MTRR_FIX4K_C0000, 0xC0000, 0x1000 },
{ EFI_MSR_IA32_MTRR_FIX4K_C8000, 0xC8000, 0x1000}, { EFI_MSR_IA32_MTRR_FIX4K_C8000, 0xC8000, 0x1000 },
{ EFI_MSR_IA32_MTRR_FIX4K_D0000, 0xD0000, 0x1000}, { EFI_MSR_IA32_MTRR_FIX4K_D0000, 0xD0000, 0x1000 },
{ EFI_MSR_IA32_MTRR_FIX4K_D8000, 0xD8000, 0x1000}, { EFI_MSR_IA32_MTRR_FIX4K_D8000, 0xD8000, 0x1000 },
{ EFI_MSR_IA32_MTRR_FIX4K_E0000, 0xE0000, 0x1000}, { EFI_MSR_IA32_MTRR_FIX4K_E0000, 0xE0000, 0x1000 },
{ EFI_MSR_IA32_MTRR_FIX4K_E8000, 0xE8000, 0x1000}, { EFI_MSR_IA32_MTRR_FIX4K_E8000, 0xE8000, 0x1000 },
{ EFI_MSR_IA32_MTRR_FIX4K_F0000, 0xF0000, 0x1000}, { EFI_MSR_IA32_MTRR_FIX4K_F0000, 0xF0000, 0x1000 },
{ EFI_MSR_IA32_MTRR_FIX4K_F8000, 0xF8000, 0x1000} { EFI_MSR_IA32_MTRR_FIX4K_F8000, 0xF8000, 0x1000 }
}; };
/** /**
@ -94,7 +94,7 @@ EFI_FIXED_MTRR mFixedMtrrTable[] = {
**/ **/
INT8 INT8
CheckDirection ( CheckDirection (
IN UINT64 Input IN UINT64 Input
) )
{ {
return 0; return 0;
@ -108,7 +108,7 @@ CheckDirection (
**/ **/
VOID VOID
EfiDisableCacheMtrr ( EfiDisableCacheMtrr (
OUT UINT64 *OldMtrr OUT UINT64 *OldMtrr
) )
{ {
UINT64 TempQword; UINT64 TempQword;
@ -116,9 +116,9 @@ EfiDisableCacheMtrr (
// //
// Disable Cache MTRR // Disable Cache MTRR
// //
*OldMtrr = AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE); *OldMtrr = AsmReadMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE);
TempQword = (*OldMtrr) & ~B_EFI_MSR_GLOBAL_MTRR_ENABLE & ~B_EFI_MSR_FIXED_MTRR_ENABLE; TempQword = (*OldMtrr) & ~B_EFI_MSR_GLOBAL_MTRR_ENABLE & ~B_EFI_MSR_FIXED_MTRR_ENABLE;
AsmWriteMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, TempQword); AsmWriteMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, TempQword);
AsmDisableCache (); AsmDisableCache ();
} }
@ -131,8 +131,8 @@ EfiDisableCacheMtrr (
**/ **/
VOID VOID
EfiRecoverCacheMtrr ( EfiRecoverCacheMtrr (
IN BOOLEAN EnableMtrr, IN BOOLEAN EnableMtrr,
IN UINT64 OldMtrr IN UINT64 OldMtrr
) )
{ {
UINT64 TempQword; UINT64 TempQword;
@ -141,7 +141,7 @@ EfiRecoverCacheMtrr (
// Enable Cache MTRR // Enable Cache MTRR
// //
if (EnableMtrr) { if (EnableMtrr) {
TempQword = AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE); TempQword = AsmReadMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE);
TempQword |= (UINT64)(B_EFI_MSR_GLOBAL_MTRR_ENABLE | B_EFI_MSR_FIXED_MTRR_ENABLE); TempQword |= (UINT64)(B_EFI_MSR_GLOBAL_MTRR_ENABLE | B_EFI_MSR_FIXED_MTRR_ENABLE);
} else { } else {
TempQword = OldMtrr; TempQword = OldMtrr;
@ -164,15 +164,15 @@ EfiRecoverCacheMtrr (
**/ **/
VOID VOID
EfiProgramMtrr ( EfiProgramMtrr (
IN UINT32 MtrrNumber, IN UINT32 MtrrNumber,
IN EFI_PHYSICAL_ADDRESS MemoryAddress, IN EFI_PHYSICAL_ADDRESS MemoryAddress,
IN UINT64 MemoryLength, IN UINT64 MemoryLength,
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType, IN EFI_MEMORY_CACHE_TYPE MemoryCacheType,
IN UINT64 ValidMtrrAddressMask IN UINT64 ValidMtrrAddressMask
) )
{ {
UINT64 TempQword; UINT64 TempQword;
UINT64 OldMtrr; UINT64 OldMtrr;
if (MemoryLength == 0) { if (MemoryLength == 0) {
return; return;
@ -206,11 +206,11 @@ EfiProgramMtrr (
**/ **/
UINT64 UINT64
Power2MaxMemory ( Power2MaxMemory (
IN UINT64 MemoryAddress, IN UINT64 MemoryAddress,
IN UINT64 MemoryLength IN UINT64 MemoryLength
) )
{ {
UINT64 Result; UINT64 Result;
if (MemoryLength == 0) { if (MemoryLength == 0) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
@ -219,7 +219,7 @@ Power2MaxMemory (
// //
// Compute initial power of 2 size to return // Compute initial power of 2 size to return
// //
Result = GetPowerOfTwo64(MemoryLength); Result = GetPowerOfTwo64 (MemoryLength);
// //
// Special case base of 0 as all ranges are valid // Special case base of 0 as all ranges are valid
@ -253,20 +253,20 @@ Power2MaxMemory (
**/ **/
UINT32 UINT32
CheckMtrrAlignment ( CheckMtrrAlignment (
IN UINT64 BaseAddress, IN UINT64 BaseAddress,
IN UINT64 Size IN UINT64 Size
) )
{ {
UINT32 ShiftedBase; UINT32 ShiftedBase;
UINT32 ShiftedSize; UINT32 ShiftedSize;
// //
// Shift base and size right 12 bits to allow for larger memory sizes. The // Shift base and size right 12 bits to allow for larger memory sizes. The
// MTRRs do not use the first 12 bits so this is safe for now. Only supports // MTRRs do not use the first 12 bits so this is safe for now. Only supports
// up to 52 bits of physical address space. // up to 52 bits of physical address space.
// //
ShiftedBase = (UINT32) RShiftU64 (BaseAddress, 12); ShiftedBase = (UINT32)RShiftU64 (BaseAddress, 12);
ShiftedSize = (UINT32) RShiftU64 (Size, 12); ShiftedSize = (UINT32)RShiftU64 (Size, 12);
// //
// Return the results to the caller of the MOD // Return the results to the caller of the MOD
@ -288,47 +288,53 @@ CheckMtrrAlignment (
**/ **/
EFI_STATUS EFI_STATUS
ProgramFixedMtrr ( ProgramFixedMtrr (
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType, IN EFI_MEMORY_CACHE_TYPE MemoryCacheType,
IN UINT64 *Base, IN UINT64 *Base,
IN UINT64 *Len IN UINT64 *Len
) )
{ {
UINT32 MsrNum; UINT32 MsrNum;
UINT32 ByteShift; UINT32 ByteShift;
UINT64 TempQword; UINT64 TempQword;
UINT64 OrMask; UINT64 OrMask;
UINT64 ClearMask; UINT64 ClearMask;
TempQword = 0; TempQword = 0;
OrMask = 0; OrMask = 0;
ClearMask = 0; ClearMask = 0;
for (MsrNum = 0; MsrNum < V_EFI_FIXED_MTRR_NUMBER; MsrNum++) { for (MsrNum = 0; MsrNum < V_EFI_FIXED_MTRR_NUMBER; MsrNum++) {
if ((*Base >= mFixedMtrrTable[MsrNum].BaseAddress) && if ((*Base >= mFixedMtrrTable[MsrNum].BaseAddress) &&
(*Base < (mFixedMtrrTable[MsrNum].BaseAddress + 8 * mFixedMtrrTable[MsrNum].Length))) { (*Base < (mFixedMtrrTable[MsrNum].BaseAddress + 8 * mFixedMtrrTable[MsrNum].Length)))
{
break; break;
} }
} }
if (MsrNum == V_EFI_FIXED_MTRR_NUMBER ) { if (MsrNum == V_EFI_FIXED_MTRR_NUMBER ) {
return EFI_DEVICE_ERROR; return EFI_DEVICE_ERROR;
} }
// //
// We found the fixed MTRR to be programmed // We found the fixed MTRR to be programmed
// //
for (ByteShift=0; ByteShift < 8; ByteShift++) { for (ByteShift = 0; ByteShift < 8; ByteShift++) {
if ( *Base == (mFixedMtrrTable[MsrNum].BaseAddress + ByteShift * mFixedMtrrTable[MsrNum].Length)) { if ( *Base == (mFixedMtrrTable[MsrNum].BaseAddress + ByteShift * mFixedMtrrTable[MsrNum].Length)) {
break; break;
} }
} }
if (ByteShift == 8 ) { if (ByteShift == 8 ) {
return EFI_DEVICE_ERROR; return EFI_DEVICE_ERROR;
} }
for (; ((ByteShift<8) && (*Len >= mFixedMtrrTable[MsrNum].Length));ByteShift++) {
OrMask |= LShiftU64((UINT64) MemoryCacheType, (UINT32) (ByteShift* 8)); for ( ; ((ByteShift < 8) && (*Len >= mFixedMtrrTable[MsrNum].Length)); ByteShift++) {
ClearMask |= LShiftU64((UINT64) 0xFF, (UINT32) (ByteShift * 8)); OrMask |= LShiftU64 ((UINT64)MemoryCacheType, (UINT32)(ByteShift* 8));
*Len -= mFixedMtrrTable[MsrNum].Length; ClearMask |= LShiftU64 ((UINT64)0xFF, (UINT32)(ByteShift * 8));
*Base += mFixedMtrrTable[MsrNum].Length; *Len -= mFixedMtrrTable[MsrNum].Length;
*Base += mFixedMtrrTable[MsrNum].Length;
} }
TempQword = (AsmReadMsr64 (mFixedMtrrTable[MsrNum].Msr) & (~ClearMask)) | OrMask; TempQword = (AsmReadMsr64 (mFixedMtrrTable[MsrNum].Msr) & (~ClearMask)) | OrMask;
AsmWriteMsr64 (mFixedMtrrTable[MsrNum].Msr, TempQword); AsmWriteMsr64 (mFixedMtrrTable[MsrNum].Msr, TempQword);
@ -346,8 +352,8 @@ ProgramFixedMtrr (
**/ **/
BOOLEAN BOOLEAN
CheckMtrrOverlap ( CheckMtrrOverlap (
IN EFI_PHYSICAL_ADDRESS Start, IN EFI_PHYSICAL_ADDRESS Start,
IN EFI_PHYSICAL_ADDRESS End IN EFI_PHYSICAL_ADDRESS End
) )
{ {
return FALSE; return FALSE;
@ -369,33 +375,33 @@ CheckMtrrOverlap (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
SetCacheAttributes ( SetCacheAttributes (
IN EFI_PHYSICAL_ADDRESS MemoryAddress, IN EFI_PHYSICAL_ADDRESS MemoryAddress,
IN UINT64 MemoryLength, IN UINT64 MemoryLength,
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 MsrNum, MsrNumEnd; UINT32 MsrNum, MsrNumEnd;
UINT64 TempQword; UINT64 TempQword;
UINT32 LastVariableMtrrForBios; UINT32 LastVariableMtrrForBios;
UINT64 OldMtrr; UINT64 OldMtrr;
UINT32 UsedMsrNum; UINT32 UsedMsrNum;
EFI_MEMORY_CACHE_TYPE UsedMemoryCacheType; EFI_MEMORY_CACHE_TYPE UsedMemoryCacheType;
UINT64 ValidMtrrAddressMask; UINT64 ValidMtrrAddressMask;
UINT32 Cpuid_RegEax; UINT32 Cpuid_RegEax;
AsmCpuid (CPUID_EXTENDED_FUNCTION, &Cpuid_RegEax, NULL, NULL, NULL); AsmCpuid (CPUID_EXTENDED_FUNCTION, &Cpuid_RegEax, NULL, NULL, NULL);
if (Cpuid_RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) { if (Cpuid_RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) {
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Cpuid_RegEax, NULL, NULL, NULL); AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Cpuid_RegEax, NULL, NULL, NULL);
ValidMtrrAddressMask = (LShiftU64((UINT64) 1, (Cpuid_RegEax & 0xFF)) - 1) & (~(UINT64)0x0FFF); ValidMtrrAddressMask = (LShiftU64 ((UINT64)1, (Cpuid_RegEax & 0xFF)) - 1) & (~(UINT64)0x0FFF);
} else { } else {
ValidMtrrAddressMask = (LShiftU64((UINT64) 1, 36) - 1) & (~(UINT64)0x0FFF); ValidMtrrAddressMask = (LShiftU64 ((UINT64)1, 36) - 1) & (~(UINT64)0x0FFF);
} }
// //
// Check for invalid parameter // Check for invalid parameter
// //
if ((MemoryAddress & ~ValidMtrrAddressMask) != 0 || (MemoryLength & ~ValidMtrrAddressMask) != 0) { if (((MemoryAddress & ~ValidMtrrAddressMask) != 0) || ((MemoryLength & ~ValidMtrrAddressMask) != 0)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@ -424,6 +430,7 @@ SetCacheAttributes (
while ((MemoryLength > 0) && (Status == EFI_SUCCESS)) { while ((MemoryLength > 0) && (Status == EFI_SUCCESS)) {
Status = ProgramFixedMtrr (MemoryCacheType, &MemoryAddress, &MemoryLength); Status = ProgramFixedMtrr (MemoryCacheType, &MemoryAddress, &MemoryLength);
} }
EfiRecoverCacheMtrr (TRUE, OldMtrr); EfiRecoverCacheMtrr (TRUE, OldMtrr);
return Status; return Status;
} }
@ -431,15 +438,15 @@ SetCacheAttributes (
// //
// Search if the range attribute has been set before // Search if the range attribute has been set before
// //
Status = SearchForExactMtrr( Status = SearchForExactMtrr (
MemoryAddress, MemoryAddress,
MemoryLength, MemoryLength,
ValidMtrrAddressMask, ValidMtrrAddressMask,
&UsedMsrNum, &UsedMsrNum,
&UsedMemoryCacheType &UsedMemoryCacheType
); );
if (!EFI_ERROR(Status)) { if (!EFI_ERROR (Status)) {
// //
// Compare if it has the same type as current setting // Compare if it has the same type as current setting
// //
@ -453,49 +460,51 @@ SetCacheAttributes (
// //
// Check if the set type is the same as Default Type // Check if the set type is the same as Default Type
// //
if (IsDefaultType(MemoryCacheType)) { if (IsDefaultType (MemoryCacheType)) {
// //
// Clear the MTRR // Clear the MTRR
// //
AsmWriteMsr64(UsedMsrNum, 0); AsmWriteMsr64 (UsedMsrNum, 0);
AsmWriteMsr64(UsedMsrNum + 1, 0); AsmWriteMsr64 (UsedMsrNum + 1, 0);
return EFI_SUCCESS; return EFI_SUCCESS;
} else { } else {
// //
// Modify the MTRR type // Modify the MTRR type
// //
EfiProgramMtrr(UsedMsrNum, EfiProgramMtrr (
MemoryAddress, UsedMsrNum,
MemoryLength, MemoryAddress,
MemoryCacheType, MemoryLength,
ValidMtrrAddressMask MemoryCacheType,
); ValidMtrrAddressMask
);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
} }
} }
#if 0 #if 0
// //
// @bug - Need to create memory map so that when checking for overlap we // @bug - Need to create memory map so that when checking for overlap we
// can determine if an overlap exists based on all caching requests. // can determine if an overlap exists based on all caching requests.
// //
// Don't waste a variable MTRR if the caching attrib is same as default in MTRR_DEF_TYPE // Don't waste a variable MTRR if the caching attrib is same as default in MTRR_DEF_TYPE
// //
if (MemoryCacheType == (AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE)) { if (MemoryCacheType == (AsmReadMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE)) {
if (!CheckMtrrOverlap (MemoryAddress, MemoryAddress+MemoryLength-1)) { if (!CheckMtrrOverlap (MemoryAddress, MemoryAddress+MemoryLength-1)) {
return EFI_SUCCESS; return EFI_SUCCESS;
} }
} }
#endif
#endif
// //
// Find first unused MTRR // Find first unused MTRR
// //
MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64(EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT)); MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64 (EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));
for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum +=2) { for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum += 2) {
if ((AsmReadMsr64(MsrNum+1) & B_EFI_MSR_CACHE_MTRR_VALID) == 0 ) { if ((AsmReadMsr64 (MsrNum+1) & B_EFI_MSR_CACHE_MTRR_VALID) == 0 ) {
break; break;
} }
} }
@ -520,14 +529,14 @@ SetCacheAttributes (
// //
TempQword = MemoryLength; TempQword = MemoryLength;
if (TempQword == Power2MaxMemory(MemoryAddress, TempQword)) { if (TempQword == Power2MaxMemory (MemoryAddress, TempQword)) {
EfiProgramMtrr(MsrNum, EfiProgramMtrr (
MemoryAddress, MsrNum,
MemoryLength, MemoryAddress,
MemoryCacheType, MemoryLength,
ValidMtrrAddressMask MemoryCacheType,
); ValidMtrrAddressMask
);
} else { } else {
// //
// Fill in MTRRs with values. Direction can not be checked for this method // Fill in MTRRs with values. Direction can not be checked for this method
@ -545,16 +554,17 @@ SetCacheAttributes (
// //
// Set next power of 2 region // Set next power of 2 region
// //
MemoryLength = Power2MaxMemory(MemoryAddress, TempQword); MemoryLength = Power2MaxMemory (MemoryAddress, TempQword);
EfiProgramMtrr(MsrNum, EfiProgramMtrr (
MemoryAddress, MsrNum,
MemoryLength, MemoryAddress,
MemoryCacheType, MemoryLength,
ValidMtrrAddressMask MemoryCacheType,
); ValidMtrrAddressMask
);
MemoryAddress += MemoryLength; MemoryAddress += MemoryLength;
TempQword -= MemoryLength; TempQword -= MemoryLength;
MsrNum += 2; MsrNum += 2;
} while (TempQword != 0); } while (TempQword != 0);
} }
@ -573,12 +583,13 @@ ResetCacheAttributes (
VOID VOID
) )
{ {
UINT32 MsrNum, MsrNumEnd; UINT32 MsrNum, MsrNumEnd;
UINT16 Index; UINT16 Index;
UINT64 OldMtrr; UINT64 OldMtrr;
UINT64 CacheType; UINT64 CacheType;
BOOLEAN DisableCar; BOOLEAN DisableCar;
Index = 0;
Index = 0;
DisableCar = TRUE; DisableCar = TRUE;
// //
@ -589,7 +600,7 @@ ResetCacheAttributes (
// //
// Set default cache type // Set default cache type
// //
AsmWriteMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, CacheType); AsmWriteMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, CacheType);
// //
// Disable CAR // Disable CAR
@ -608,7 +619,7 @@ ResetCacheAttributes (
// //
// Reset Variable MTRRs // Reset Variable MTRRs
// //
MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64(EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT)); MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64 (EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));
for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum++) { for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum++) {
AsmWriteMsr64 (MsrNum, 0); AsmWriteMsr64 (MsrNum, 0);
} }
@ -636,23 +647,23 @@ ResetCacheAttributes (
**/ **/
EFI_STATUS EFI_STATUS
SearchForExactMtrr ( SearchForExactMtrr (
IN EFI_PHYSICAL_ADDRESS MemoryAddress, IN EFI_PHYSICAL_ADDRESS MemoryAddress,
IN UINT64 MemoryLength, IN UINT64 MemoryLength,
IN UINT64 ValidMtrrAddressMask, IN UINT64 ValidMtrrAddressMask,
OUT UINT32 *UsedMsrNum, OUT UINT32 *UsedMsrNum,
OUT EFI_MEMORY_CACHE_TYPE *UsedMemoryCacheType OUT EFI_MEMORY_CACHE_TYPE *UsedMemoryCacheType
) )
{ {
UINT32 MsrNum, MsrNumEnd; UINT32 MsrNum, MsrNumEnd;
UINT64 TempQword; UINT64 TempQword;
if (MemoryLength == 0) { if (MemoryLength == 0) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64(EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT)); MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64 (EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));
for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum +=2) { for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum += 2) {
TempQword = AsmReadMsr64(MsrNum+1); TempQword = AsmReadMsr64 (MsrNum+1);
if ((TempQword & B_EFI_MSR_CACHE_MTRR_VALID) == 0) { if ((TempQword & B_EFI_MSR_CACHE_MTRR_VALID) == 0) {
continue; continue;
} }
@ -667,7 +678,7 @@ SearchForExactMtrr (
} }
*UsedMemoryCacheType = (EFI_MEMORY_CACHE_TYPE)(TempQword & B_EFI_MSR_CACHE_MEMORY_TYPE); *UsedMemoryCacheType = (EFI_MEMORY_CACHE_TYPE)(TempQword & B_EFI_MSR_CACHE_MEMORY_TYPE);
*UsedMsrNum = MsrNum; *UsedMsrNum = MsrNum;
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -685,13 +696,12 @@ SearchForExactMtrr (
**/ **/
BOOLEAN BOOLEAN
IsDefaultType ( IsDefaultType (
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
) )
{ {
if ((AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE) != MemoryCacheType) { if ((AsmReadMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE) != MemoryCacheType) {
return FALSE; return FALSE;
} }
return TRUE; return TRUE;
} }

67
IntelFsp2Pkg/Library/BaseCacheLib/CacheLibInternal.h
View File

@ -8,46 +8,45 @@
#ifndef _CACHE_LIB_INTERNAL_H_ #ifndef _CACHE_LIB_INTERNAL_H_
#define _CACHE_LIB_INTERNAL_H_ #define _CACHE_LIB_INTERNAL_H_
#define EFI_MSR_CACHE_VARIABLE_MTRR_BASE 0x00000200 #define EFI_MSR_CACHE_VARIABLE_MTRR_BASE 0x00000200
#define EFI_MSR_CACHE_VARIABLE_MTRR_END 0x0000020F #define EFI_MSR_CACHE_VARIABLE_MTRR_END 0x0000020F
#define V_EFI_FIXED_MTRR_NUMBER 11 #define V_EFI_FIXED_MTRR_NUMBER 11
#define EFI_MSR_IA32_MTRR_FIX64K_00000 0x00000250 #define EFI_MSR_IA32_MTRR_FIX64K_00000 0x00000250
#define EFI_MSR_IA32_MTRR_FIX16K_80000 0x00000258 #define EFI_MSR_IA32_MTRR_FIX16K_80000 0x00000258
#define EFI_MSR_IA32_MTRR_FIX16K_A0000 0x00000259 #define EFI_MSR_IA32_MTRR_FIX16K_A0000 0x00000259
#define EFI_MSR_IA32_MTRR_FIX4K_C0000 0x00000268 #define EFI_MSR_IA32_MTRR_FIX4K_C0000 0x00000268
#define EFI_MSR_IA32_MTRR_FIX4K_C8000 0x00000269 #define EFI_MSR_IA32_MTRR_FIX4K_C8000 0x00000269
#define EFI_MSR_IA32_MTRR_FIX4K_D0000 0x0000026A #define EFI_MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
#define EFI_MSR_IA32_MTRR_FIX4K_D8000 0x0000026B #define EFI_MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
#define EFI_MSR_IA32_MTRR_FIX4K_E0000 0x0000026C #define EFI_MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
#define EFI_MSR_IA32_MTRR_FIX4K_E8000 0x0000026D #define EFI_MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
#define EFI_MSR_IA32_MTRR_FIX4K_F0000 0x0000026E #define EFI_MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
#define EFI_MSR_IA32_MTRR_FIX4K_F8000 0x0000026F #define EFI_MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
#define EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE 0x000002FF #define EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE 0x000002FF
#define B_EFI_MSR_CACHE_MTRR_VALID BIT11 #define B_EFI_MSR_CACHE_MTRR_VALID BIT11
#define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11 #define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11
#define B_EFI_MSR_FIXED_MTRR_ENABLE BIT10 #define B_EFI_MSR_FIXED_MTRR_ENABLE BIT10
#define B_EFI_MSR_CACHE_MEMORY_TYPE (BIT2 | BIT1 | BIT0) #define B_EFI_MSR_CACHE_MEMORY_TYPE (BIT2 | BIT1 | BIT0)
#define EFI_MSR_VALID_MASK 0xFFFFFFFFF #define EFI_MSR_VALID_MASK 0xFFFFFFFFF
#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000 #define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000
#define EFI_SMRR_CACHE_VALID_ADDRESS 0xFFFFF000 #define EFI_SMRR_CACHE_VALID_ADDRESS 0xFFFFF000
#define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000 #define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000
// Leave one MTRR pairs for OS use // Leave one MTRR pairs for OS use
#define EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS 1 #define EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS 1
#define EFI_CACHE_LAST_VARIABLE_MTRR_FOR_BIOS (EFI_MSR_CACHE_VARIABLE_MTRR_END) - \ #define EFI_CACHE_LAST_VARIABLE_MTRR_FOR_BIOS (EFI_MSR_CACHE_VARIABLE_MTRR_END) -\
(EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS * 2) (EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS * 2)
#define EFI_MSR_IA32_MTRR_CAP 0x000000FE #define EFI_MSR_IA32_MTRR_CAP 0x000000FE
#define B_EFI_MSR_IA32_MTRR_CAP_EMRR_SUPPORT BIT12 #define B_EFI_MSR_IA32_MTRR_CAP_EMRR_SUPPORT BIT12
#define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11 #define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11
#define B_EFI_MSR_IA32_MTRR_CAP_WC_SUPPORT BIT10 #define B_EFI_MSR_IA32_MTRR_CAP_WC_SUPPORT BIT10
#define B_EFI_MSR_IA32_MTRR_CAP_FIXED_SUPPORT BIT8 #define B_EFI_MSR_IA32_MTRR_CAP_FIXED_SUPPORT BIT8
#define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) #define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008 #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
#define CPUID_EXTENDED_FUNCTION 0x80000000 #define CPUID_EXTENDED_FUNCTION 0x80000000
#endif #endif

101
IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
View File

@ -57,11 +57,11 @@ typedef struct {
VOID VOID
EFIAPI EFIAPI
SetFspGlobalDataPointer ( SetFspGlobalDataPointer (
IN FSP_GLOBAL_DATA *FspData IN FSP_GLOBAL_DATA *FspData
) )
{ {
ASSERT (FspData != NULL); ASSERT (FspData != NULL);
*((volatile UINT32 *)(UINTN)PcdGet32(PcdGlobalDataPointerAddress)) = (UINT32)(UINTN)FspData; *((volatile UINT32 *)(UINTN)PcdGet32 (PcdGlobalDataPointerAddress)) = (UINT32)(UINTN)FspData;
} }
/** /**
@ -74,9 +74,9 @@ GetFspGlobalDataPointer (
VOID VOID
) )
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
FspData = *(FSP_GLOBAL_DATA **)(UINTN)PcdGet32(PcdGlobalDataPointerAddress); FspData = *(FSP_GLOBAL_DATA **)(UINTN)PcdGet32 (PcdGlobalDataPointerAddress);
return FspData; return FspData;
} }
@ -93,8 +93,8 @@ GetFspApiParameter (
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
return *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam[0])); return *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET (ApiParam[0]));
} }
/** /**
@ -102,7 +102,7 @@ GetFspApiParameter (
@retval FSP entry stack pointer. @retval FSP entry stack pointer.
**/ **/
VOID* VOID *
EFIAPI EFIAPI
GetFspEntryStack ( GetFspEntryStack (
VOID VOID
@ -110,8 +110,8 @@ GetFspEntryStack (
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
return (VOID*)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam[0])); return (VOID *)(FspData->CoreStack + CONTEXT_STACK_OFFSET (ApiParam[0]));
} }
/** /**
@ -127,8 +127,8 @@ GetFspApiParameter2 (
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
return *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam[1])); return *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET (ApiParam[1]));
} }
/** /**
@ -140,13 +140,13 @@ GetFspApiParameter2 (
VOID VOID
EFIAPI EFIAPI
SetFspApiParameter ( SetFspApiParameter (
IN UINT32 Value IN UINT32 Value
) )
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
*(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam)) = Value; *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET (ApiParam)) = Value;
} }
/** /**
@ -163,8 +163,8 @@ SetFspApiReturnStatus (
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
*(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(Eax)) = ReturnStatus; *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET (Eax)) = ReturnStatus;
} }
/** /**
@ -176,7 +176,7 @@ SetFspApiReturnStatus (
VOID VOID
EFIAPI EFIAPI
SetFspCoreStackPointer ( SetFspCoreStackPointer (
IN VOID *NewStackTop IN VOID *NewStackTop
) )
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
@ -184,14 +184,14 @@ SetFspCoreStackPointer (
UINT32 *NewStack; UINT32 *NewStack;
UINT32 StackContextLen; UINT32 StackContextLen;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
StackContextLen = sizeof(CONTEXT_STACK) / sizeof(UINT32); StackContextLen = sizeof (CONTEXT_STACK) / sizeof (UINT32);
// //
// Reserve space for the ContinuationFunc two parameters // Reserve space for the ContinuationFunc two parameters
// //
OldStack = (UINT32 *)FspData->CoreStack; OldStack = (UINT32 *)FspData->CoreStack;
NewStack = (UINT32 *)NewStackTop - StackContextLen - 2; NewStack = (UINT32 *)NewStackTop - StackContextLen - 2;
FspData->CoreStack = (UINT32)NewStack; FspData->CoreStack = (UINT32)NewStack;
while (StackContextLen-- != 0) { while (StackContextLen-- != 0) {
*NewStack++ = *OldStack++; *NewStack++ = *OldStack++;
@ -207,16 +207,15 @@ SetFspCoreStackPointer (
VOID VOID
EFIAPI EFIAPI
SetFspPlatformDataPointer ( SetFspPlatformDataPointer (
IN VOID *PlatformData IN VOID *PlatformData
) )
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
FspData->PlatformData.DataPtr = PlatformData; FspData->PlatformData.DataPtr = PlatformData;
} }
/** /**
This function gets the platform specific data pointer. This function gets the platform specific data pointer.
@ -231,11 +230,10 @@ GetFspPlatformDataPointer (
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
return FspData->PlatformData.DataPtr; return FspData->PlatformData.DataPtr;
} }
/** /**
This function sets the UPD data pointer. This function sets the UPD data pointer.
@ -244,7 +242,7 @@ GetFspPlatformDataPointer (
VOID VOID
EFIAPI EFIAPI
SetFspUpdDataPointer ( SetFspUpdDataPointer (
IN VOID *UpdDataPtr IN VOID *UpdDataPtr
) )
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
@ -252,7 +250,7 @@ SetFspUpdDataPointer (
// //
// Get the FSP Global Data Pointer // Get the FSP Global Data Pointer
// //
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
// //
// Set the UPD pointer. // Set the UPD pointer.
@ -273,11 +271,10 @@ GetFspUpdDataPointer (
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
return FspData->UpdDataPtr; return FspData->UpdDataPtr;
} }
/** /**
This function sets the FspMemoryInit UPD data pointer. This function sets the FspMemoryInit UPD data pointer.
@ -286,7 +283,7 @@ GetFspUpdDataPointer (
VOID VOID
EFIAPI EFIAPI
SetFspMemoryInitUpdDataPointer ( SetFspMemoryInitUpdDataPointer (
IN VOID *MemoryInitUpdPtr IN VOID *MemoryInitUpdPtr
) )
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
@ -294,7 +291,7 @@ SetFspMemoryInitUpdDataPointer (
// //
// Get the FSP Global Data Pointer // Get the FSP Global Data Pointer
// //
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
// //
// Set the FspMemoryInit UPD pointer. // Set the FspMemoryInit UPD pointer.
@ -315,11 +312,10 @@ GetFspMemoryInitUpdDataPointer (
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
return FspData->MemoryInitUpdPtr; return FspData->MemoryInitUpdPtr;
} }
/** /**
This function sets the FspSiliconInit UPD data pointer. This function sets the FspSiliconInit UPD data pointer.
@ -328,7 +324,7 @@ GetFspMemoryInitUpdDataPointer (
VOID VOID
EFIAPI EFIAPI
SetFspSiliconInitUpdDataPointer ( SetFspSiliconInitUpdDataPointer (
IN VOID *SiliconInitUpdPtr IN VOID *SiliconInitUpdPtr
) )
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
@ -336,7 +332,7 @@ SetFspSiliconInitUpdDataPointer (
// //
// Get the FSP Global Data Pointer // Get the FSP Global Data Pointer
// //
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
// //
// Set the FspSiliconInit UPD data pointer. // Set the FspSiliconInit UPD data pointer.
@ -357,11 +353,10 @@ GetFspSiliconInitUpdDataPointer (
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
return FspData->SiliconInitUpdPtr; return FspData->SiliconInitUpdPtr;
} }
/** /**
Set FSP measurement point timestamp. Set FSP measurement point timestamp.
@ -381,9 +376,9 @@ SetFspMeasurePoint (
// Bit [55: 0] will be the timestamp // Bit [55: 0] will be the timestamp
// Bit [63:56] will be the ID // Bit [63:56] will be the ID
// //
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
if (FspData->PerfIdx < sizeof(FspData->PerfData) / sizeof(FspData->PerfData[0])) { if (FspData->PerfIdx < sizeof (FspData->PerfData) / sizeof (FspData->PerfData[0])) {
FspData->PerfData[FspData->PerfIdx] = AsmReadTsc (); FspData->PerfData[FspData->PerfIdx] = AsmReadTsc ();
((UINT8 *)(&FspData->PerfData[FspData->PerfIdx]))[7] = Id; ((UINT8 *)(&FspData->PerfData[FspData->PerfIdx]))[7] = Id;
} }
@ -401,7 +396,7 @@ GetFspInfoHeader (
VOID VOID
) )
{ {
return GetFspGlobalDataPointer()->FspInfoHeader; return GetFspGlobalDataPointer ()->FspInfoHeader;
} }
/** /**
@ -412,10 +407,10 @@ GetFspInfoHeader (
VOID VOID
EFIAPI EFIAPI
SetFspInfoHeader ( SetFspInfoHeader (
FSP_INFO_HEADER *FspInfoHeader FSP_INFO_HEADER *FspInfoHeader
) )
{ {
GetFspGlobalDataPointer()->FspInfoHeader = FspInfoHeader; GetFspGlobalDataPointer ()->FspInfoHeader = FspInfoHeader;
} }
/** /**
@ -431,8 +426,8 @@ GetFspInfoHeaderFromApiContext (
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
return (FSP_INFO_HEADER *)(*(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(FspInfoHeader))); return (FSP_INFO_HEADER *)(*(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET (FspInfoHeader)));
} }
/** /**
@ -446,7 +441,7 @@ GetFspCfgRegionDataPointer (
VOID VOID
) )
{ {
FSP_INFO_HEADER *FspInfoHeader; FSP_INFO_HEADER *FspInfoHeader;
FspInfoHeader = GetFspInfoHeader (); FspInfoHeader = GetFspInfoHeader ();
return (VOID *)(FspInfoHeader->ImageBase + FspInfoHeader->CfgRegionOffset); return (VOID *)(FspInfoHeader->ImageBase + FspInfoHeader->CfgRegionOffset);
@ -463,7 +458,7 @@ GetFspApiCallingIndex (
VOID VOID
) )
{ {
return GetFspGlobalDataPointer()->ApiIdx; return GetFspGlobalDataPointer ()->ApiIdx;
} }
/** /**
@ -479,7 +474,7 @@ SetFspApiCallingIndex (
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
FspData->ApiIdx = Index; FspData->ApiIdx = Index;
} }
@ -494,7 +489,7 @@ GetPhaseStatusCode (
VOID VOID
) )
{ {
return GetFspGlobalDataPointer()->StatusCode; return GetFspGlobalDataPointer ()->StatusCode;
} }
/** /**
@ -510,7 +505,7 @@ SetPhaseStatusCode (
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
FspData->StatusCode = StatusCode; FspData->StatusCode = StatusCode;
} }
@ -523,13 +518,13 @@ SetPhaseStatusCode (
VOID VOID
EFIAPI EFIAPI
FspApiReturnStatusReset ( FspApiReturnStatusReset (
IN UINT32 FspResetType IN UINT32 FspResetType
) )
{ {
volatile BOOLEAN LoopUntilReset; volatile BOOLEAN LoopUntilReset;
LoopUntilReset = TRUE; LoopUntilReset = TRUE;
DEBUG ((DEBUG_INFO, "FSP returning control to Bootloader with reset required return status %x\n",FspResetType)); DEBUG ((DEBUG_INFO, "FSP returning control to Bootloader with reset required return status %x\n", FspResetType));
if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) { if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) {
/// ///
/// Below code is not an infinite loop.The control will go back to API calling function in BootLoader each time BootLoader /// Below code is not an infinite loop.The control will go back to API calling function in BootLoader each time BootLoader

56
IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c
View File

@ -26,7 +26,7 @@ CONST CHAR8 *mHexTable = "0123456789ABCDEF";
// VA_LIST can not initialize to NULL for all compiler, so we use this to // VA_LIST can not initialize to NULL for all compiler, so we use this to
// indicate a null VA_LIST // indicate a null VA_LIST
// //
VA_LIST mVaListNull; VA_LIST mVaListNull;
/** /**
Get stack frame pointer of function call. Get stack frame pointer of function call.
@ -39,7 +39,6 @@ GetStackFramePointer (
VOID VOID
); );
/** /**
Prints a debug message to the debug output device if the specified error level is enabled. Prints a debug message to the debug output device if the specified error level is enabled.
@ -63,7 +62,7 @@ DebugPrint (
... ...
) )
{ {
VA_LIST Marker; VA_LIST Marker;
VA_START (Marker, Format); VA_START (Marker, Format);
DebugVPrint (ErrorLevel, Format, Marker); DebugVPrint (ErrorLevel, Format, Marker);
@ -89,13 +88,13 @@ DebugPrint (
**/ **/
VOID VOID
DebugPrintMarker ( DebugPrintMarker (
IN UINTN ErrorLevel, IN UINTN ErrorLevel,
IN CONST CHAR8 *Format, IN CONST CHAR8 *Format,
IN VA_LIST VaListMarker, IN VA_LIST VaListMarker,
IN BASE_LIST BaseListMarker IN BASE_LIST BaseListMarker
) )
{ {
CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH]; CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];
// //
// If Format is NULL, then ASSERT(). // If Format is NULL, then ASSERT().
@ -149,9 +148,9 @@ DebugPrintMarker (
VOID VOID
EFIAPI EFIAPI
DebugVPrint ( DebugVPrint (
IN UINTN ErrorLevel, IN UINTN ErrorLevel,
IN CONST CHAR8 *Format, IN CONST CHAR8 *Format,
IN VA_LIST VaListMarker IN VA_LIST VaListMarker
) )
{ {
DebugPrintMarker (ErrorLevel, Format, VaListMarker, NULL); DebugPrintMarker (ErrorLevel, Format, VaListMarker, NULL);
@ -177,9 +176,9 @@ DebugVPrint (
VOID VOID
EFIAPI EFIAPI
DebugBPrint ( DebugBPrint (
IN UINTN ErrorLevel, IN UINTN ErrorLevel,
IN CONST CHAR8 *Format, IN CONST CHAR8 *Format,
IN BASE_LIST BaseListMarker IN BASE_LIST BaseListMarker
) )
{ {
DebugPrintMarker (ErrorLevel, Format, mVaListNull, BaseListMarker); DebugPrintMarker (ErrorLevel, Format, mVaListNull, BaseListMarker);
@ -194,14 +193,15 @@ DebugBPrint (
**/ **/
VOID VOID
FillHex ( FillHex (
UINT32 Value, UINT32 Value,
CHAR8 *Buffer CHAR8 *Buffer
) )
{ {
INTN Idx; INTN Idx;
for (Idx = 7; Idx >= 0; Idx--) { for (Idx = 7; Idx >= 0; Idx--) {
Buffer[Idx] = mHexTable[Value & 0x0F]; Buffer[Idx] = mHexTable[Value & 0x0F];
Value >>= 4; Value >>= 4;
} }
} }
@ -227,8 +227,8 @@ DebugAssertInternal (
VOID VOID
) )
{ {
CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH]; CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];
UINT32 *Frame; UINT32 *Frame;
Frame = (UINT32 *)GetStackFramePointer (); Frame = (UINT32 *)GetStackFramePointer ();
@ -237,9 +237,9 @@ DebugAssertInternal (
// //
AsciiStrnCpyS ( AsciiStrnCpyS (
Buffer, Buffer,
sizeof(Buffer) / sizeof(CHAR8), sizeof (Buffer) / sizeof (CHAR8),
"-> EBP:0x00000000 EIP:0x00000000\n", "-> EBP:0x00000000 EIP:0x00000000\n",
sizeof(Buffer) / sizeof(CHAR8) - 1 sizeof (Buffer) / sizeof (CHAR8) - 1
); );
SerialPortWrite ((UINT8 *)"ASSERT DUMP:\n", 13); SerialPortWrite ((UINT8 *)"ASSERT DUMP:\n", 13);
while (Frame != NULL) { while (Frame != NULL) {
@ -291,7 +291,6 @@ DebugAssert (
DebugAssertInternal (); DebugAssertInternal ();
} }
/** /**
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer. Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
@ -317,7 +316,6 @@ DebugClearMemory (
return Buffer; return Buffer;
} }
/** /**
Returns TRUE if ASSERT() macros are enabled. Returns TRUE if ASSERT() macros are enabled.
@ -334,10 +332,9 @@ DebugAssertEnabled (
VOID VOID
) )
{ {
return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0); return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);
} }
/** /**
Returns TRUE if DEBUG() macros are enabled. Returns TRUE if DEBUG() macros are enabled.
@ -354,7 +351,7 @@ DebugPrintEnabled (
VOID VOID
) )
{ {
return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0); return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);
} }
/** /**
@ -373,10 +370,9 @@ DebugCodeEnabled (
VOID VOID
) )
{ {
return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0); return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);
} }
/** /**
Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled. Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.
@ -393,7 +389,7 @@ DebugClearMemoryEnabled (
VOID VOID
) )
{ {
return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0); return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);
} }
/** /**
@ -408,8 +404,8 @@ DebugClearMemoryEnabled (
BOOLEAN BOOLEAN
EFIAPI EFIAPI
DebugPrintLevelEnabled ( DebugPrintLevelEnabled (
IN CONST UINTN ErrorLevel IN CONST UINTN ErrorLevel
) )
{ {
return (BOOLEAN) ((ErrorLevel & PcdGet32(PcdFixedDebugPrintErrorLevel)) != 0); return (BOOLEAN)((ErrorLevel & PcdGet32 (PcdFixedDebugPrintErrorLevel)) != 0);
} }

37
IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformMemory.c
View File

@ -25,10 +25,10 @@
EFI_HOB_RESOURCE_DESCRIPTOR * EFI_HOB_RESOURCE_DESCRIPTOR *
EFIAPI EFIAPI
FspGetResourceDescriptorByOwner ( FspGetResourceDescriptorByOwner (
IN EFI_GUID *OwnerGuid IN EFI_GUID *OwnerGuid
) )
{ {
EFI_PEI_HOB_POINTERS Hob; EFI_PEI_HOB_POINTERS Hob;
// //
// Get the HOB list for processing // Get the HOB list for processing
@ -41,10 +41,12 @@ FspGetResourceDescriptorByOwner (
while (!END_OF_HOB_LIST (Hob)) { while (!END_OF_HOB_LIST (Hob)) {
if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) && \ if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) && \
(CompareGuid (&Hob.ResourceDescriptor->Owner, OwnerGuid))) { (CompareGuid (&Hob.ResourceDescriptor->Owner, OwnerGuid)))
return Hob.ResourceDescriptor; {
return Hob.ResourceDescriptor;
} }
} }
Hob.Raw = GET_NEXT_HOB (Hob); Hob.Raw = GET_NEXT_HOB (Hob);
} }
@ -60,14 +62,14 @@ FspGetResourceDescriptorByOwner (
VOID VOID
EFIAPI EFIAPI
FspGetSystemMemorySize ( FspGetSystemMemorySize (
IN OUT UINT64 *LowMemoryLength, IN OUT UINT64 *LowMemoryLength,
IN OUT UINT64 *HighMemoryLength IN OUT UINT64 *HighMemoryLength
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_BOOT_MODE BootMode; EFI_BOOT_MODE BootMode;
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
EFI_PEI_HOB_POINTERS Hob; EFI_PEI_HOB_POINTERS Hob;
ResourceAttribute = ( ResourceAttribute = (
EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_PRESENT |
@ -99,18 +101,21 @@ FspGetSystemMemorySize (
if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) || if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||
((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) && ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&
(Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))) { (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute)))
{
// //
// Need memory above 1MB to be collected here // Need memory above 1MB to be collected here
// //
if (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB && if ((Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB) &&
Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) BASE_4GB) { (Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS)BASE_4GB))
*LowMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength); {
} else if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) BASE_4GB) { *LowMemoryLength += (UINT64)(Hob.ResourceDescriptor->ResourceLength);
*HighMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength); } else if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS)BASE_4GB) {
*HighMemoryLength += (UINT64)(Hob.ResourceDescriptor->ResourceLength);
} }
} }
} }
Hob.Raw = GET_NEXT_HOB (Hob); Hob.Raw = GET_NEXT_HOB (Hob);
} }
} }

133
IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c
View File

@ -21,21 +21,21 @@
#include <Protocol/PciEnumerationComplete.h> #include <Protocol/PciEnumerationComplete.h>
#include <Library/ReportStatusCodeLib.h> #include <Library/ReportStatusCodeLib.h>
#include <Library/PerformanceLib.h> #include <Library/PerformanceLib.h>
extern EFI_GUID gFspPerformanceDataGuid; extern EFI_GUID gFspPerformanceDataGuid;
EFI_PEI_PPI_DESCRIPTOR mPeiPostPciEnumerationPpi = { EFI_PEI_PPI_DESCRIPTOR mPeiPostPciEnumerationPpi = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiPciEnumerationCompleteProtocolGuid, &gEfiPciEnumerationCompleteProtocolGuid,
NULL NULL
}; };
EFI_PEI_PPI_DESCRIPTOR mPeiReadyToBootPpi = { EFI_PEI_PPI_DESCRIPTOR mPeiReadyToBootPpi = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiEventReadyToBootGuid, &gEfiEventReadyToBootGuid,
NULL NULL
}; };
EFI_PEI_PPI_DESCRIPTOR mPeiEndOfFirmwarePpi = { EFI_PEI_PPI_DESCRIPTOR mPeiEndOfFirmwarePpi = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gFspEventEndOfFirmwareGuid, &gFspEventEndOfFirmwareGuid,
NULL NULL
@ -59,41 +59,41 @@ UINT32 mFspNotifySequence[] = {
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FspNotificationHandler ( FspNotificationHandler (
IN UINT32 NotificationCode IN UINT32 NotificationCode
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
switch (NotificationCode) { switch (NotificationCode) {
case EnumInitPhaseAfterPciEnumeration: case EnumInitPhaseAfterPciEnumeration:
// //
// Do POST PCI initialization if needed // Do POST PCI initialization if needed
// //
DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Post PCI Enumeration ...\n")); DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Post PCI Enumeration ...\n"));
PeiServicesInstallPpi (&mPeiPostPciEnumerationPpi); PeiServicesInstallPpi (&mPeiPostPciEnumerationPpi);
break; break;
case EnumInitPhaseReadyToBoot: case EnumInitPhaseReadyToBoot:
// //
// Ready To Boot // Ready To Boot
// //
DEBUG ((DEBUG_INFO| DEBUG_INIT, "FSP Ready To Boot ...\n")); DEBUG ((DEBUG_INFO| DEBUG_INIT, "FSP Ready To Boot ...\n"));
PeiServicesInstallPpi (&mPeiReadyToBootPpi); PeiServicesInstallPpi (&mPeiReadyToBootPpi);
break; break;
case EnumInitPhaseEndOfFirmware: case EnumInitPhaseEndOfFirmware:
// //
// End of Firmware // End of Firmware
// //
DEBUG ((DEBUG_INFO| DEBUG_INIT, "FSP End of Firmware ...\n")); DEBUG ((DEBUG_INFO| DEBUG_INIT, "FSP End of Firmware ...\n"));
PeiServicesInstallPpi (&mPeiEndOfFirmwarePpi); PeiServicesInstallPpi (&mPeiEndOfFirmwarePpi);
break; break;
default: default:
Status = EFI_INVALID_PARAMETER; Status = EFI_INVALID_PARAMETER;
break; break;
} }
return Status; return Status;
@ -108,10 +108,10 @@ FspNotificationHandler (
VOID VOID
EFIAPI EFIAPI
FspSiliconInitDone2 ( FspSiliconInitDone2 (
IN EFI_STATUS Status IN EFI_STATUS Status
) )
{ {
volatile EFI_STATUS FspStatus; volatile EFI_STATUS FspStatus;
FspStatus = Status; FspStatus = Status;
// //
@ -128,6 +128,7 @@ FspSiliconInitDone2 (
Status = EFI_DEVICE_ERROR; // Force to known error. Status = EFI_DEVICE_ERROR; // Force to known error.
break; break;
} }
// //
// This is the end of the FspSiliconInit API // This is the end of the FspSiliconInit API
// Give control back to the boot loader // Give control back to the boot loader
@ -156,12 +157,12 @@ FspSiliconInitDone2 (
VOID VOID
EFIAPI EFIAPI
FspMemoryInitDone2 ( FspMemoryInitDone2 (
IN EFI_STATUS Status, IN EFI_STATUS Status,
IN OUT VOID **HobListPtr IN OUT VOID **HobListPtr
) )
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
volatile EFI_STATUS FspStatus; volatile EFI_STATUS FspStatus;
FspStatus = Status; FspStatus = Status;
// //
@ -171,9 +172,11 @@ FspMemoryInitDone2 (
if (HobListPtr == NULL) { if (HobListPtr == NULL) {
HobListPtr = (VOID **)GetFspApiParameter2 (); HobListPtr = (VOID **)GetFspApiParameter2 ();
} }
if (HobListPtr != NULL) { if (HobListPtr != NULL) {
*HobListPtr = (VOID *) GetHobList (); *HobListPtr = (VOID *)GetHobList ();
} }
// //
// Convert to FSP EAS defined API return codes // Convert to FSP EAS defined API return codes
// //
@ -189,6 +192,7 @@ FspMemoryInitDone2 (
Status = EFI_DEVICE_ERROR; // Force to known error. Status = EFI_DEVICE_ERROR; // Force to known error.
break; break;
} }
// //
// This is the end of the FspMemoryInit API // This is the end of the FspMemoryInit API
// Give control back to the boot loader // Give control back to the boot loader
@ -196,10 +200,10 @@ FspMemoryInitDone2 (
DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspMemoryInitApi() - [Status: 0x%08X] - End\n", Status)); DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspMemoryInitApi() - [Status: 0x%08X] - End\n", Status));
SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT); SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT);
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[0] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_TEMP_RAM_INIT | FSP_STATUS_CODE_COMMON_CODE| FSP_STATUS_CODE_API_ENTRY); PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[0] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_TEMP_RAM_INIT | FSP_STATUS_CODE_COMMON_CODE| FSP_STATUS_CODE_API_ENTRY);
PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[1] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_TEMP_RAM_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[1] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_TEMP_RAM_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);
PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[2] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[2] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);
PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);
if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) { if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) {
do { do {
@ -217,13 +221,13 @@ FspMemoryInitDone2 (
if (GetFspApiCallingIndex () == TempRamExitApiIndex) { if (GetFspApiCallingIndex () == TempRamExitApiIndex) {
SetPhaseStatusCode (FSP_STATUS_CODE_TEMP_RAM_EXIT); SetPhaseStatusCode (FSP_STATUS_CODE_TEMP_RAM_EXIT);
SetFspMeasurePoint (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY); SetFspMeasurePoint (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY);
PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);
DEBUG ((DEBUG_INFO | DEBUG_INIT, "TempRamExitApi() - Begin\n")); DEBUG ((DEBUG_INFO | DEBUG_INIT, "TempRamExitApi() - Begin\n"));
} else { } else {
SetPhaseStatusCode (FSP_STATUS_CODE_SILICON_INIT); SetPhaseStatusCode (FSP_STATUS_CODE_SILICON_INIT);
SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY); SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY);
PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);
DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspSiliconInitApi() - Begin\n")); DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspSiliconInitApi() - Begin\n"));
} }
@ -238,11 +242,11 @@ FspMemoryInitDone2 (
VOID VOID
EFIAPI EFIAPI
FspTempRamExitDone2 ( FspTempRamExitDone2 (
IN EFI_STATUS Status IN EFI_STATUS Status
) )
{ {
// //
volatile EFI_STATUS FspStatus; volatile EFI_STATUS FspStatus;
FspStatus = Status; FspStatus = Status;
// Convert to FSP EAS defined API return codes // Convert to FSP EAS defined API return codes
@ -258,13 +262,14 @@ FspTempRamExitDone2 (
Status = EFI_DEVICE_ERROR; // Force to known error. Status = EFI_DEVICE_ERROR; // Force to known error.
break; break;
} }
// //
// This is the end of the TempRamExit API // This is the end of the TempRamExit API
// Give control back to the boot loader // Give control back to the boot loader
// //
DEBUG ((DEBUG_INFO | DEBUG_INIT, "TempRamExitApi() - [Status: 0x%08X] - End\n", Status)); DEBUG ((DEBUG_INFO | DEBUG_INIT, "TempRamExitApi() - [Status: 0x%08X] - End\n", Status));
SetFspMeasurePoint (FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT); SetFspMeasurePoint (FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT);
PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);
if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) { if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) {
do { do {
@ -275,9 +280,10 @@ FspTempRamExitDone2 (
} }
} while (FspStatus != EFI_SUCCESS); } while (FspStatus != EFI_SUCCESS);
} }
SetPhaseStatusCode (FSP_STATUS_CODE_SILICON_INIT); SetPhaseStatusCode (FSP_STATUS_CODE_SILICON_INIT);
SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY); SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY);
PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);
DEBUG ((DEBUG_INFO | DEBUG_INIT, "SiliconInitApi() - Begin\n")); DEBUG ((DEBUG_INFO | DEBUG_INIT, "SiliconInitApi() - Begin\n"));
} }
@ -294,15 +300,14 @@ FspWaitForNotify (
VOID VOID
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 NotificationValue; UINT32 NotificationValue;
UINT32 NotificationCount; UINT32 NotificationCount;
UINT8 Count; UINT8 Count;
volatile EFI_STATUS FspStatus; volatile EFI_STATUS FspStatus;
NotificationCount = 0; NotificationCount = 0;
while (NotificationCount < sizeof(mFspNotifySequence) / sizeof(UINT32)) { while (NotificationCount < sizeof (mFspNotifySequence) / sizeof (UINT32)) {
Count = (UINT8)((NotificationCount << 1) & 0x07); Count = (UINT8)((NotificationCount << 1) & 0x07);
SetFspMeasurePoint (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + Count); SetFspMeasurePoint (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + Count);
@ -312,7 +317,7 @@ FspWaitForNotify (
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);
} else if (NotificationCount == 1) { } else if (NotificationCount == 1) {
SetPhaseStatusCode (FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION); SetPhaseStatusCode (FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION);
PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);
} else if (NotificationCount == 2) { } else if (NotificationCount == 2) {
SetPhaseStatusCode (FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION); SetPhaseStatusCode (FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION);
@ -333,7 +338,7 @@ FspWaitForNotify (
// Process Notification and Give control back to the boot loader framework caller // Process Notification and Give control back to the boot loader framework caller
// //
Status = FspNotificationHandler (NotificationValue); Status = FspNotificationHandler (NotificationValue);
if (!EFI_ERROR(Status)) { if (!EFI_ERROR (Status)) {
NotificationCount++; NotificationCount++;
} }
} }
@ -342,26 +347,28 @@ FspWaitForNotify (
SetFspMeasurePoint (FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT + Count); SetFspMeasurePoint (FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT + Count);
if ((NotificationCount - 1) == 0) { if ((NotificationCount - 1) == 0) {
PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);
} else if ((NotificationCount - 1) == 1) { } else if ((NotificationCount - 1) == 1) {
PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);
} else if ((NotificationCount - 1) == 2) { } else if ((NotificationCount - 1) == 2) {
PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);
} }
if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) { if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) {
FspStatus = Status; FspStatus = Status;
do { do {
SetFspApiReturnStatus(Status); SetFspApiReturnStatus (Status);
Pei2LoaderSwitchStack(); Pei2LoaderSwitchStack ();
if (Status != EFI_SUCCESS) { if (Status != EFI_SUCCESS) {
DEBUG ((DEBUG_ERROR, "!!!ERROR: NotifyPhaseApi() [Phase: %08X] - Failed - [Status: 0x%08X]\n", NotificationValue, Status)); DEBUG ((DEBUG_ERROR, "!!!ERROR: NotifyPhaseApi() [Phase: %08X] - Failed - [Status: 0x%08X]\n", NotificationValue, Status));
} }
} while (FspStatus != EFI_SUCCESS); } while (FspStatus != EFI_SUCCESS);
} }
} }
// //
// Control goes back to the PEI Core and it dispatches further PEIMs. // Control goes back to the PEI Core and it dispatches further PEIMs.
// DXEIPL is the final one to transfer control back to the boot loader. // DXEIPL is the final one to transfer control back to the boot loader.
@ -389,7 +396,7 @@ FspSiliconInitDone (
VOID VOID
EFIAPI EFIAPI
FspMemoryInitDone ( FspMemoryInitDone (
IN OUT VOID **HobListPtr IN OUT VOID **HobListPtr
) )
{ {
FspMemoryInitDone2 (EFI_SUCCESS, HobListPtr); FspMemoryInitDone2 (EFI_SUCCESS, HobListPtr);

9
IntelFsp2Pkg/Library/BaseFspSwitchStackLib/FspSwitchStackLib.c
View File

@ -22,15 +22,14 @@
**/ **/
UINT32 UINT32
SwapStack ( SwapStack (
IN UINT32 NewStack IN UINT32 NewStack
) )
{ {
FSP_GLOBAL_DATA *FspData; FSP_GLOBAL_DATA *FspData;
UINT32 OldStack; UINT32 OldStack;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
OldStack = FspData->CoreStack; OldStack = FspData->CoreStack;
FspData->CoreStack = NewStack; FspData->CoreStack = NewStack;
return OldStack; return OldStack;
} }

8
IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c
View File

@ -19,8 +19,8 @@
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FspUpdSignatureCheck ( FspUpdSignatureCheck (
IN UINT32 ApiIdx, IN UINT32 ApiIdx,
IN VOID *ApiParam IN VOID *ApiParam
) )
{ {
return EFI_SUCCESS; return EFI_SUCCESS;
@ -36,8 +36,8 @@ FspUpdSignatureCheck (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
FspMultiPhaseSiInitApiHandler ( FspMultiPhaseSiInitApiHandler (
IN UINT32 ApiIdx, IN UINT32 ApiIdx,
IN VOID *ApiParam IN VOID *ApiParam
) )
{ {
return EFI_SUCCESS; return EFI_SUCCESS;

6
IntelFsp2Pkg/Tools/Tests/ExpectedFspUpd.h
View File

@ -5,11 +5,11 @@
#pragma pack(1) #pragma pack(1)
#define FSPT_UPD_SIGNATURE 0x545F4450554D4551 /* 'QEMUPD_T' */ #define FSPT_UPD_SIGNATURE 0x545F4450554D4551 /* 'QEMUPD_T' */
#define FSPM_UPD_SIGNATURE 0x4D5F4450554D4551 /* 'QEMUPD_M' */ #define FSPM_UPD_SIGNATURE 0x4D5F4450554D4551 /* 'QEMUPD_M' */
#define FSPS_UPD_SIGNATURE 0x535F4450554D4551 /* 'QEMUPD_S' */ #define FSPS_UPD_SIGNATURE 0x535F4450554D4551 /* 'QEMUPD_S' */
#pragma pack() #pragma pack()

89
IntelFsp2Pkg/Tools/Tests/ExpectedFspmUpd.h
View File

@ -5,69 +5,66 @@
#pragma pack(1) #pragma pack(1)
/** Fsp M Configuration /** Fsp M Configuration
**/ **/
typedef struct { typedef struct {
/** Offset 0x00C8 - Debug Serial Port Base address
Debug serial port base address. This option will be used only when the 'Serial Port
Debug Device' option is set to 'External Device'. 0x00000000(Default).
**/
UINT32 SerialDebugPortAddress;
/** Offset 0x00C8 - Debug Serial Port Base address /** Offset 0x00CC - Debug Serial Port Type
Debug serial port base address. This option will be used only when the 'Serial Port 16550 compatible debug serial port resource type. NONE means no serial port support.
Debug Device' option is set to 'External Device'. 0x00000000(Default). 0x02:MMIO(Default).
**/ 0:NONE, 1:I/O, 2:MMIO
UINT32 SerialDebugPortAddress; **/
UINT8 SerialDebugPortType;
/** Offset 0x00CC - Debug Serial Port Type /** Offset 0x00CD - Serial Port Debug Device
16550 compatible debug serial port resource type. NONE means no serial port support. Select active serial port device for debug.For SOC UART devices,'Debug Serial Port
0x02:MMIO(Default). Base' options will be ignored. 0x02:SOC UART2(Default).
0:NONE, 1:I/O, 2:MMIO 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device
**/ **/
UINT8 SerialDebugPortType; UINT8 SerialDebugPortDevice;
/** Offset 0x00CD - Serial Port Debug Device /** Offset 0x00CE - Debug Serial Port Stride Size
Select active serial port device for debug.For SOC UART devices,'Debug Serial Port Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default).
Base' options will be ignored. 0x02:SOC UART2(Default). 0:1, 2:4
0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device **/
**/ UINT8 SerialDebugPortStrideSize;
UINT8 SerialDebugPortDevice;
/** Offset 0x00CE - Debug Serial Port Stride Size /** Offset 0x00CF
Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default). **/
0:1, 2:4 UINT8 UnusedUpdSpace2[1];
**/
UINT8 SerialDebugPortStrideSize;
/** Offset 0x00CF /** Offset 0x00D0
**/ **/
UINT8 UnusedUpdSpace2[1]; UINT8 ReservedFspmUpd[4];
/** Offset 0x00D0
**/
UINT8 ReservedFspmUpd[4];
} FSP_M_CONFIG; } FSP_M_CONFIG;
/** Fsp M UPD Configuration /** Fsp M UPD Configuration
**/ **/
typedef struct { typedef struct {
/** Offset 0x0000
**/
FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0000 /** Offset 0x00A8
**/ **/
FSP_UPD_HEADER FspUpdHeader; FSPM_ARCH_UPD FspmArchUpd;
/** Offset 0x00A8 /** Offset 0x00C8
**/ **/
FSPM_ARCH_UPD FspmArchUpd; FSP_M_CONFIG FspmConfig;
/** Offset 0x00C8 /** Offset 0x00D4
**/ **/
FSP_M_CONFIG FspmConfig; UINT8 UnusedUpdSpace3[2];
/** Offset 0x00D4 /** Offset 0x00D6
**/ **/
UINT8 UnusedUpdSpace3[2]; UINT16 UpdTerminator;
/** Offset 0x00D6
**/
UINT16 UpdTerminator;
} FSPM_UPD; } FSPM_UPD;
#pragma pack() #pragma pack()

77
IntelFsp2Pkg/Tools/Tests/ExpectedFspsUpd.h
View File

@ -5,63 +5,60 @@
#pragma pack(1) #pragma pack(1)
/** Fsp S Configuration /** Fsp S Configuration
**/ **/
typedef struct { typedef struct {
/** Offset 0x0118 - BMP Logo Data Size
BMP logo data buffer size. 0x00000000(Default).
**/
UINT32 LogoSize;
/** Offset 0x0118 - BMP Logo Data Size /** Offset 0x011C - BMP Logo Data Pointer
BMP logo data buffer size. 0x00000000(Default). BMP logo data pointer to a BMP format buffer. 0x00000000(Default).
**/ **/
UINT32 LogoSize; UINT32 LogoPtr;
/** Offset 0x011C - BMP Logo Data Pointer /** Offset 0x0120 - Graphics Configuration Data Pointer
BMP logo data pointer to a BMP format buffer. 0x00000000(Default). Graphics configuration data used for initialization. 0x00000000(Default).
**/ **/
UINT32 LogoPtr; UINT32 GraphicsConfigPtr;
/** Offset 0x0120 - Graphics Configuration Data Pointer /** Offset 0x0124 - PCI GFX Temporary MMIO Base
Graphics configuration data used for initialization. 0x00000000(Default). PCI Temporary PCI GFX Base used before full PCI enumeration. 0x80000000(Default).
**/ **/
UINT32 GraphicsConfigPtr; UINT32 PciTempResourceBase;
/** Offset 0x0124 - PCI GFX Temporary MMIO Base /** Offset 0x0128
PCI Temporary PCI GFX Base used before full PCI enumeration. 0x80000000(Default). **/
**/ UINT8 UnusedUpdSpace1[3];
UINT32 PciTempResourceBase;
/** Offset 0x0128 /** Offset 0x012B
**/ **/
UINT8 UnusedUpdSpace1[3]; UINT8 ReservedFspsUpd;
/** Offset 0x012B
**/
UINT8 ReservedFspsUpd;
} FSP_S_CONFIG; } FSP_S_CONFIG;
/** Fsp S UPD Configuration /** Fsp S UPD Configuration
**/ **/
typedef struct { typedef struct {
/** Offset 0x0000
**/
FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0000 /** Offset 0x00F8
**/ **/
FSP_UPD_HEADER FspUpdHeader; FSPS_ARCH_UPD FspsArchUpd;
/** Offset 0x00F8 /** Offset 0x0118
**/ **/
FSPS_ARCH_UPD FspsArchUpd; FSP_S_CONFIG FspsConfig;
/** Offset 0x0118 /** Offset 0x012C
**/ **/
FSP_S_CONFIG FspsConfig; UINT8 UnusedUpdSpace2[2];
/** Offset 0x012C /** Offset 0x012E
**/ **/
UINT8 UnusedUpdSpace2[2]; UINT16 UpdTerminator;
/** Offset 0x012E
**/
UINT16 UpdTerminator;
} FSPS_UPD; } FSPS_UPD;
#pragma pack() #pragma pack()

96
IntelFsp2Pkg/Tools/Tests/ExpectedFsptUpd.h
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@ -5,81 +5,77 @@
#pragma pack(1) #pragma pack(1)
/** Fsp T Common UPD /** Fsp T Common UPD
**/ **/
typedef struct { typedef struct {
/** Offset 0x0040
**/
UINT8 Revision;
/** Offset 0x0040 /** Offset 0x0041
**/ **/
UINT8 Revision; UINT8 Reserved[3];
/** Offset 0x0041 /** Offset 0x0044
**/ **/
UINT8 Reserved[3]; UINT32 MicrocodeRegionBase;
/** Offset 0x0044 /** Offset 0x0048
**/ **/
UINT32 MicrocodeRegionBase; UINT32 MicrocodeRegionLength;
/** Offset 0x0048 /** Offset 0x004C
**/ **/
UINT32 MicrocodeRegionLength; UINT32 CodeRegionBase;
/** Offset 0x004C /** Offset 0x0050
**/ **/
UINT32 CodeRegionBase; UINT32 CodeRegionLength;
/** Offset 0x0050 /** Offset 0x0054
**/ **/
UINT32 CodeRegionLength; UINT8 Reserved1[12];
/** Offset 0x0054
**/
UINT8 Reserved1[12];
} FSPT_COMMON_UPD; } FSPT_COMMON_UPD;
/** Fsp T Configuration /** Fsp T Configuration
**/ **/
typedef struct { typedef struct {
/** Offset 0x0060 - Chicken bytes to test Hex config
This option shows how to present option for 4 bytes data
**/
UINT32 ChickenBytes;
/** Offset 0x0060 - Chicken bytes to test Hex config /** Offset 0x0064
This option shows how to present option for 4 bytes data **/
**/ UINT8 ReservedFsptUpd1[28];
UINT32 ChickenBytes;
/** Offset 0x0064
**/
UINT8 ReservedFsptUpd1[28];
} FSP_T_CONFIG; } FSP_T_CONFIG;
/** Fsp T UPD Configuration /** Fsp T UPD Configuration
**/ **/
typedef struct { typedef struct {
/** Offset 0x0000
**/
FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0000 /** Offset 0x0020
**/ **/
FSP_UPD_HEADER FspUpdHeader; FSPT_ARCH_UPD FsptArchUpd;
/** Offset 0x0020 /** Offset 0x0040
**/ **/
FSPT_ARCH_UPD FsptArchUpd; FSPT_COMMON_UPD FsptCommonUpd;
/** Offset 0x0040 /** Offset 0x0060
**/ **/
FSPT_COMMON_UPD FsptCommonUpd; FSP_T_CONFIG FsptConfig;
/** Offset 0x0060 /** Offset 0x0080
**/ **/
FSP_T_CONFIG FsptConfig; UINT8 UnusedUpdSpace0[6];
/** Offset 0x0080 /** Offset 0x0086
**/ **/
UINT8 UnusedUpdSpace0[6]; UINT16 UpdTerminator;
/** Offset 0x0086
**/
UINT16 UpdTerminator;
} FSPT_UPD; } FSPT_UPD;
#pragma pack() #pragma pack()