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Arm Packages: Fixed coding style/Line endings to follow EDK2 coding convention

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Arm Packages: Fixed mispelling

Arm Packages: Reduced warnings all over the code




git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12407 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-09-22 22:53:54 +00:00
parent 5439ccda50
commit 11c20f4e06
39 changed files with 2288 additions and 2431 deletions
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2
ArmPkg/ArmPkg.dec
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@ -35,7 +35,7 @@
ArmLib|Include/Library/ArmLib.h ArmLib|Include/Library/ArmLib.h
SemihostLib|Include/Library/Semihosting.h SemihostLib|Include/Library/Semihosting.h
UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h
DefaultExceptioHandlerLib|Include/Library/DefaultExceptioHandlerLib.h DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
[Guids.common] [Guids.common]

2
ArmPkg/ArmPkg.dsc
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@ -62,7 +62,7 @@
SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
DefaultExceptioHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf

8
ArmPkg/Drivers/CpuDxe/CpuDxe.inf
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@ -52,14 +52,12 @@
[LibraryClasses] [LibraryClasses]
BaseMemoryLib BaseMemoryLib
CacheMaintenanceLib CacheMaintenanceLib
UefiDriverEntryPoint CpuLib
ArmLib DebugLib
DefaultExceptionHandlerLib
DxeServicesTableLib DxeServicesTableLib
PeCoffGetEntryPointLib PeCoffGetEntryPointLib
UefiLib UefiLib
CpuLib
DefaultExceptioHandlerLib
DebugLib
[Protocols] [Protocols]
gEfiCpuArchProtocolGuid gEfiCpuArchProtocolGuid

37
ArmPkg/Drivers/CpuDxe/Mmu.c
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@ -543,49 +543,49 @@ UpdatePageEntries (
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
// obtain page table base // Obtain page table base
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress (); FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
// calculate number of 4KB page table entries to change // Calculate number of 4KB page table entries to change
NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE; NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;
// iterate for the number of 4KB pages to change // Iterate for the number of 4KB pages to change
Offset = 0; Offset = 0;
for(p = 0; p < NumPageEntries; p++) { for(p = 0; p < NumPageEntries; p++) {
// calculate index into first level translation table for page table value // Calculate index into first level translation table for page table value
FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT; FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
// read the descriptor from the first level page table // Read the descriptor from the first level page table
Descriptor = FirstLevelTable[FirstLevelIdx]; Descriptor = FirstLevelTable[FirstLevelIdx];
// does this descriptor need to be converted from section entry to 4K pages? // Does this descriptor need to be converted from section entry to 4K pages?
if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) { if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {
Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT); Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
if (EFI_ERROR(Status)) { if (EFI_ERROR(Status)) {
// exit for loop // Exit for loop
break; break;
} }
// re-read descriptor // Re-read descriptor
Descriptor = FirstLevelTable[FirstLevelIdx]; Descriptor = FirstLevelTable[FirstLevelIdx];
} }
// obtain page table base address // Obtain page table base address
PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor); PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);
// calculate index into the page table // Calculate index into the page table
PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT; PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT); ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);
// get the entry // Get the entry
CurrentPageTableEntry = PageTable[PageTableIndex]; CurrentPageTableEntry = PageTable[PageTableIndex];
// mask off appropriate fields // Mask off appropriate fields
PageTableEntry = CurrentPageTableEntry & ~EntryMask; PageTableEntry = CurrentPageTableEntry & ~EntryMask;
// mask in new attributes and/or permissions // Mask in new attributes and/or permissions
PageTableEntry |= EntryValue; PageTableEntry |= EntryValue;
if (VirtualMask != 0) { if (VirtualMask != 0) {
@ -609,7 +609,7 @@ UpdatePageEntries (
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
Offset += TT_DESCRIPTOR_PAGE_SIZE; Offset += TT_DESCRIPTOR_PAGE_SIZE;
} // end first level translation table loop } // End first level translation table loop
return Status; return Status;
} }
@ -815,22 +815,23 @@ SetMemoryAttributes (
EFI_STATUS Status; EFI_STATUS Status;
if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) { if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {
// is the base and length a multiple of 1 MB? // Is the base and length a multiple of 1 MB?
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes)); DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask); Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);
} else { } else {
// base and/or length is not a multiple of 1 MB // Base and/or length is not a multiple of 1 MB
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes)); DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask); Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);
} }
// flush d-cache so descriptors make it back to uncached memory for subsequent table walks // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks
// flush and invalidate pages // flush and invalidate pages
//TODO: Do we really need to invalidate the caches everytime we change the memory attributes ?
ArmCleanInvalidateDataCache (); ArmCleanInvalidateDataCache ();
ArmInvalidateInstructionCache (); ArmInvalidateInstructionCache ();
// invalidate all TLB entries so changes are synced // Invalidate all TLB entries so changes are synced
ArmInvalidateTlb (); ArmInvalidateTlb ();
return Status; return Status;

213
ArmPkg/Include/Chipset/ArmV7.h
View File

@ -15,6 +15,8 @@
#ifndef __ARM_V7_H__ #ifndef __ARM_V7_H__
#define __ARM_V7_H__ #define __ARM_V7_H__
#include <Chipset/ArmV7Mmu.h>
// Domain Access Control Register // Domain Access Control Register
#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a))) #define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a))) #define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
@ -22,207 +24,6 @@
#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a))) #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a))) #define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
#define TTBR_NOT_OUTER_SHAREABLE BIT5
#define TTBR_RGN_OUTER_NON_CACHEABLE 0
#define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3
#define TTBR_RGN_OUTER_WRITE_THROUGH BIT4
#define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)
#define TTBR_SHAREABLE BIT1
#define TTBR_NON_SHAREABLE 0
#define TTBR_INNER_CACHEABLE BIT0
#define TTBR_NON_INNER_CACHEABLE BIT0
#define TTBR_RGN_INNER_NON_CACHEABLE 0
#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6
#define TTBR_RGN_INNER_WRITE_THROUGH BIT0
#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)
#define TTBR_WRITE_THROUGH_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC )
#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC )
#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )
#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC )
#define TRANSLATION_TABLE_SECTION_COUNT 4096
#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1)
#define TRANSLATION_TABLE_PAGE_COUNT 256
#define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
#define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
#define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1)
#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))
// Translation table descriptor types
#define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0))
#define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0)
#define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0)
#define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0))
#define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))
#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)
// Translation table descriptor types
#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)
// Section descriptor definitions
#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)
#define TT_DESCRIPTOR_SECTION_NS_SECURE (0UL << 19)
#define TT_DESCRIPTOR_SECTION_NS_NON_SECURE (1UL << 19)
#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)
#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)
#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)
#define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11)
#define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11)
#define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11)
#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)
#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)
#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)
#define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10)
#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)
#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)
#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))
#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))
#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)
#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)
#define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15)
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3)
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_SIZE (0x00001000)
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHEABLE_MASK (1UL << 3)
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc,IsLargePage) ((IsLargePage)? \
((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_LARGEPAGE_XN_MASK): \
((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) << 11) & TT_DESCRIPTOR_PAGE_XN_MASK))
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \
(((Desc) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK): \
(((((Desc) & (0x3 << 12)) >> 6) | (Desc & (0x3 << 2)))))
#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \
(((Desc) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK): \
(((((Desc) & (0x3 << 6)) << 6) | (Desc & (0x3 << 2)))))
#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)
#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
#define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00)
#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
#define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20
#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000)
#define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000)
#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK)
#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12
#define TT_DESCRIPTOR_SECTION_WRITE_BACK(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
#define TT_DESCRIPTOR_SECTION_DEVICE(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)
#define TT_DESCRIPTOR_SECTION_UNCACHED(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC)
#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE)
#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE)
// Cortex A9 feature bit definitions // Cortex A9 feature bit definitions
#define A9_FEATURE_PARITY (1<<9) #define A9_FEATURE_PARITY (1<<9)
#define A9_FEATURE_AOW (1<<8) #define A9_FEATURE_AOW (1<<8)
@ -245,7 +46,7 @@
#define SMP_GIC_CPUIF_BASE 0x100 #define SMP_GIC_CPUIF_BASE 0x100
#define SMP_GIC_DIST_BASE 0x1000 #define SMP_GIC_DIST_BASE 0x1000
// CPACR - Coprocessor Access Control Register defintions // CPACR - Coprocessor Access Control Register definitions
#define CPACR_CP_DENIED(cp) 0x00 #define CPACR_CP_DENIED(cp) 0x00
#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF) #define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF) #define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
@ -253,7 +54,7 @@
#define CPACR_D32DIS (1 << 30) #define CPACR_D32DIS (1 << 30)
#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF #define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
// NSACR - Non-Secure Access Control Register defintions // NSACR - Non-Secure Access Control Register definitions
#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF) #define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
#define NSACR_NSD32DIS (1 << 14) #define NSACR_NSD32DIS (1 << 14)
#define NSACR_NSASEDIS (1 << 15) #define NSACR_NSASEDIS (1 << 15)
@ -262,7 +63,7 @@
#define NSACR_NS_SMP (1 << 18) #define NSACR_NS_SMP (1 << 18)
#define NSACR_RFR (1 << 19) #define NSACR_RFR (1 << 19)
// SCR - Secure Configuration Register defintions // SCR - Secure Configuration Register definitions
#define SCR_NS (1 << 0) #define SCR_NS (1 << 0)
#define SCR_IRQ (1 << 1) #define SCR_IRQ (1 << 1)
#define SCR_FIQ (1 << 2) #define SCR_FIQ (1 << 2)
@ -330,7 +131,6 @@ ArmInvalidScu (
VOID VOID
); );
UINTN UINTN
EFIAPI EFIAPI
ArmGetScuBaseAddress ( ArmGetScuBaseAddress (
@ -367,7 +167,6 @@ ArmSetupSmpNonSecure (
IN UINTN CoreId IN UINTN CoreId
); );
UINTN UINTN
EFIAPI EFIAPI
ArmReadCbar ( ArmReadCbar (
@ -387,14 +186,12 @@ ArmReadMpidr (
VOID VOID
); );
UINTN UINTN
EFIAPI EFIAPI
ArmReadTpidrurw ( ArmReadTpidrurw (
VOID VOID
); );
VOID VOID
EFIAPI EFIAPI
ArmWriteTpidrurw ( ArmWriteTpidrurw (

25
ArmPkg/Include/Library/ArmTrustZoneLib.h
View File

@ -26,12 +26,22 @@
/** /**
FIXME: Need documentation FIXME: Need documentation
**/ **/
EFI_STATUS TZPCSetDecProtBits(UINTN tzpc_base, UINTN tzpc_id, UINTN bits); EFI_STATUS
TZPCSetDecProtBits (
IN UINTN TzpcBase,
IN UINTN TzpcId,
IN UINTN Bits
);
/** /**
FIXME: Need documentation FIXME: Need documentation
**/ **/
EFI_STATUS TZPCClearDecProtBits(UINTN tzpc_base, UINTN tzpc_id, UINTN bits); EFI_STATUS
TZPCClearDecProtBits (
IN UINTN TzpcBase,
IN UINTN TzpcId,
IN UINTN Bits
);
// Setup TZ Address Space Controller // Setup TZ Address Space Controller
#define TZASC_REGION_ENABLED 1 #define TZASC_REGION_ENABLED 1
@ -64,6 +74,15 @@ EFI_STATUS TZPCClearDecProtBits(UINTN tzpc_base, UINTN tzpc_id, UINTN bits);
/** /**
FIXME: Need documentation FIXME: Need documentation
**/ **/
EFI_STATUS TZASCSetRegion(UINTN tzasc_base, UINTN region_id, UINTN enabled, UINTN low_address, UINTN high_address, UINTN size, UINTN security); EFI_STATUS
TZASCSetRegion (
IN INTN TzascBase,
IN UINTN RegionId,
IN UINTN Enabled,
IN UINTN LowAddress,
IN UINTN HighAddress,
IN UINTN Size,
IN UINTN Security
);
#endif #endif

34
ArmPkg/Library/ArmTrustZoneLib/ArmTrustZone.c
View File

@ -29,7 +29,13 @@
/** /**
FIXME: Need documentation FIXME: Need documentation
**/ **/
EFI_STATUS TZPCSetDecProtBits(UINTN TzpcBase, UINTN TzpcId, UINTN Bits) { EFI_STATUS
TZPCSetDecProtBits (
IN UINTN TzpcBase,
IN UINTN TzpcId,
IN UINTN Bits
)
{
if (TzpcId > TZPC_DECPROT_MAX) { if (TzpcId > TZPC_DECPROT_MAX) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@ -42,7 +48,13 @@ EFI_STATUS TZPCSetDecProtBits(UINTN TzpcBase, UINTN TzpcId, UINTN Bits) {
/** /**
FIXME: Need documentation FIXME: Need documentation
**/ **/
EFI_STATUS TZPCClearDecProtBits(UINTN TzpcBase, UINTN TzpcId, UINTN Bits) { EFI_STATUS
TZPCClearDecProtBits (
IN UINTN TzpcBase,
IN UINTN TzpcId,
IN UINTN Bits
)
{
if (TzpcId> TZPC_DECPROT_MAX) { if (TzpcId> TZPC_DECPROT_MAX) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@ -55,14 +67,28 @@ EFI_STATUS TZPCClearDecProtBits(UINTN TzpcBase, UINTN TzpcId, UINTN Bits) {
/** /**
FIXME: Need documentation FIXME: Need documentation
**/ **/
UINT32 TZASCGetNumRegions(UINTN TzascBase) { UINT32
TZASCGetNumRegions (
IN UINTN TzascBase
)
{
return (MmioRead32 ((UINTN)TzascBase + TZASC_CONFIGURATION_REG) & 0xF); return (MmioRead32 ((UINTN)TzascBase + TZASC_CONFIGURATION_REG) & 0xF);
} }
/** /**
FIXME: Need documentation FIXME: Need documentation
**/ **/
EFI_STATUS TZASCSetRegion(UINTN TzascBase, UINTN RegionId, UINTN Enabled, UINTN LowAddress, UINTN HighAddress, UINTN Size, UINTN Security) { EFI_STATUS
TZASCSetRegion (
IN INTN TzascBase,
IN UINTN RegionId,
IN UINTN Enabled,
IN UINTN LowAddress,
IN UINTN HighAddress,
IN UINTN Size,
IN UINTN Security
)
{
UINT32* Region; UINT32* Region;
if (RegionId > TZASCGetNumRegions(TzascBase)) { if (RegionId > TZASCGetNumRegions(TzascBase)) {

17
ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandler.c
View File

@ -34,8 +34,6 @@ typedef struct {
} CPSR_CHAR; } CPSR_CHAR;
/** /**
Use the EFI Debug Image Table to lookup the FaultAddress and find which PE/COFF image Use the EFI Debug Image Table to lookup the FaultAddress and find which PE/COFF image
it came from. As long as the PE/COFF image contains a debug directory entry a it came from. As long as the PE/COFF image contains a debug directory entry a
@ -61,7 +59,6 @@ GetImageName (
UINTN Entry; UINTN Entry;
CHAR8 *Address; CHAR8 *Address;
DebugTable = gDebugImageTableHeader->EfiDebugImageInfoTable; DebugTable = gDebugImageTableHeader->EfiDebugImageInfoTable;
if (DebugTable == NULL) { if (DebugTable == NULL) {
return NULL; return NULL;
@ -103,7 +100,7 @@ CpsrString (
) )
{ {
UINTN Index; UINTN Index;
CHAR8 *Str = ReturnStr; CHAR8* Str;
CHAR8* ModeStr; CHAR8* ModeStr;
CPSR_CHAR CpsrChar[] = { CPSR_CHAR CpsrChar[] = {
{ 31, 'n' }, { 31, 'n' },
@ -119,6 +116,8 @@ CpsrString (
{ 0, '?' } { 0, '?' }
}; };
Str = ReturnStr;
for (Index = 0; CpsrChar[Index].BIT != 0; Index++, Str++) { for (Index = 0; CpsrChar[Index].BIT != 0; Index++, Str++) {
*Str = CpsrChar[Index].Char; *Str = CpsrChar[Index].Char;
if ((Cpsr & (1 << CpsrChar[Index].BIT)) != 0) { if ((Cpsr & (1 << CpsrChar[Index].BIT)) != 0) {
@ -194,8 +193,7 @@ FaultStatusToString (
return FaultSource; return FaultSource;
} }
STATIC CHAR8 *gExceptionTypeString[] = {
CHAR8 *gExceptionTypeString[] = {
"Reset", "Reset",
"Undefined OpCode", "Undefined OpCode",
"SWI", "SWI",
@ -206,7 +204,6 @@ CHAR8 *gExceptionTypeString[] = {
"FIQ" "FIQ"
}; };
/** /**
This is the default action to take on an unexpected exception This is the default action to take on an unexpected exception
@ -228,7 +225,7 @@ DefaultExceptionHandler (
BOOLEAN DfsrWrite; BOOLEAN DfsrWrite;
UINT32 PcAdjust = 0; UINT32 PcAdjust = 0;
DEBUG ((EFI_D_ERROR, "\n%a Exception PC at 0x%08x CPSR 0x%08x ", gExceptionTypeString[ExceptionType], SystemContext.SystemContextArm->PC, SystemContext.SystemContextArm->CPSR)); Print(L"\n%a Exception PC at 0x%08x CPSR 0x%08x ", gExceptionTypeString[ExceptionType], SystemContext.SystemContextArm->PC, SystemContext.SystemContextArm->CPSR);
DEBUG_CODE_BEGIN (); DEBUG_CODE_BEGIN ();
CHAR8 *Pdb; CHAR8 *Pdb;
UINT32 ImageBase; UINT32 ImageBase;
@ -249,10 +246,10 @@ DefaultExceptionHandler (
// //
// A PE/COFF image loads its headers into memory so the headers are // A PE/COFF image loads its headers into memory so the headers are
// included in the linked addressess. ELF and Mach-O images do not // included in the linked addresses. ELF and Mach-O images do not
// include the headers so the first byte of the image is usually // include the headers so the first byte of the image is usually
// text (code). If you look at link maps from ELF or Mach-O images // text (code). If you look at link maps from ELF or Mach-O images
// you need to subtact out the size of the PE/COFF header to get // you need to subtract out the size of the PE/COFF header to get
// get the offset that matches the link map. // get the offset that matches the link map.
// //
DEBUG ((EFI_D_ERROR, "loaded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader)); DEBUG ((EFI_D_ERROR, "loaded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader));

2
ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.c
View File

@ -89,7 +89,7 @@ DeCygwinPathIfNeeded (
Ptr[9] = Ptr[10]; Ptr[9] = Ptr[10];
Ptr[10] = ':'; Ptr[10] = ':';
// switch path seperators // switch path separators
for (Index = 11; Index < Len; Index++) { for (Index = 11; Index < Len; Index++) {
if (Ptr[Index] == '/') { if (Ptr[Index] == '/') {
Ptr[Index] = '\\' ; Ptr[Index] = '\\' ;

2
ArmPlatformPkg/ArmPlatformPkg.dec
View File

@ -1,5 +1,4 @@
#/** @file #/** @file
# Arm Versatile Express package.
# #
# Copyright (c) 2011, ARM Limited. All rights reserved. # Copyright (c) 2011, ARM Limited. All rights reserved.
# #
@ -46,7 +45,6 @@
gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002 gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004 gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004
[PcdsFixedAtBuild.common] [PcdsFixedAtBuild.common]
# These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file. # These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor. # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.

2
ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c
View File

@ -142,6 +142,8 @@ LcdPlatformGetVram (
EFI_STATUS Status; EFI_STATUS Status;
EFI_CPU_ARCH_PROTOCOL *Cpu; EFI_CPU_ARCH_PROTOCOL *Cpu;
Status = EFI_SUCCESS;
// Is it on the motherboard or on the daughterboard? // Is it on the motherboard or on the daughterboard?
switch(PL111_CLCD_SITE) { switch(PL111_CLCD_SITE) {

1
ArmPlatformPkg/Bds/Bds.inf
View File

@ -45,6 +45,7 @@
UefiDriverEntryPoint UefiDriverEntryPoint
DebugLib DebugLib
PrintLib PrintLib
BaseLib
[Guids] [Guids]
gEfiFileSystemInfoGuid gEfiFileSystemInfoGuid

3
ArmPlatformPkg/Bds/BdsInternal.h
View File

@ -42,6 +42,9 @@
#define IS_ARM_BDS_BOOTENTRY(ptr) (ReadUnaligned32 ((CONST UINT32*)&((ARM_BDS_LOADER_OPTIONAL_DATA*)((ptr)->OptionalData))->Header.Signature) == ARM_BDS_OPTIONAL_DATA_SIGNATURE) #define IS_ARM_BDS_BOOTENTRY(ptr) (ReadUnaligned32 ((CONST UINT32*)&((ARM_BDS_LOADER_OPTIONAL_DATA*)((ptr)->OptionalData))->Header.Signature) == ARM_BDS_OPTIONAL_DATA_SIGNATURE)
#define UPDATE_BOOT_ENTRY L"Update entry: "
#define DELETE_BOOT_ENTRY L"Delete entry: "
typedef enum { typedef enum {
BDS_LOADER_EFI_APPLICATION = 0, BDS_LOADER_EFI_APPLICATION = 0,
BDS_LOADER_KERNEL_LINUX_ATAG, BDS_LOADER_KERNEL_LINUX_ATAG,

10
ArmPlatformPkg/Bds/BootMenu.c
View File

@ -315,7 +315,7 @@ BootMenuRemoveBootOption (
EFI_STATUS Status; EFI_STATUS Status;
BDS_LOAD_OPTION_ENTRY* BootOptionEntry; BDS_LOAD_OPTION_ENTRY* BootOptionEntry;
Status = BootMenuSelectBootOption (BootOptionsList, L"Delete entry: ", FALSE, &BootOptionEntry); Status = BootMenuSelectBootOption (BootOptionsList, DELETE_BOOT_ENTRY, FALSE, &BootOptionEntry);
if (EFI_ERROR(Status)) { if (EFI_ERROR(Status)) {
return Status; return Status;
} }
@ -352,7 +352,7 @@ BootMenuUpdateBootOption (
UINTN InitrdSize; UINTN InitrdSize;
UINTN CmdLineSize; UINTN CmdLineSize;
Status = BootMenuSelectBootOption (BootOptionsList, L"Update entry: ", TRUE, &BootOptionEntry); Status = BootMenuSelectBootOption (BootOptionsList, UPDATE_BOOT_ENTRY, TRUE, &BootOptionEntry);
if (EFI_ERROR(Status)) { if (EFI_ERROR(Status)) {
return Status; return Status;
} }
@ -476,8 +476,7 @@ BootMenuManager (
BootManagerEntries[OptionSelected-1].Callback (BootOptionsList); BootManagerEntries[OptionSelected-1].Callback (BootOptionsList);
} }
} }
// Should never go here
return EFI_SUCCESS;
} }
EFI_STATUS EFI_STATUS
@ -619,6 +618,5 @@ BootMenuMain (
Status = BootOptionStart (BootOption); Status = BootOptionStart (BootOption);
} }
} }
// Should never go here
return Status;
} }

18
ArmPlatformPkg/Drivers/SP804TimerDxe/SP804Timer.c
View File

@ -29,16 +29,16 @@
#include <Drivers/SP804Timer.h> #include <Drivers/SP804Timer.h>
#define SP804_TIMER_PERIODIC_BASE (UINTN)PcdGet32 (PcdSP804TimerPeriodicBase) #define SP804_TIMER_PERIODIC_BASE ((UINTN)PcdGet32 (PcdSP804TimerPeriodicBase))
#define SP804_TIMER_METRONOME_BASE (UINTN)PcdGet32 (PcdSP804TimerMetronomeBase) #define SP804_TIMER_METRONOME_BASE ((UINTN)PcdGet32 (PcdSP804TimerMetronomeBase))
#define SP804_TIMER_PERFORMANCE_BASE (UINTN)PcdGet32 (PcdSP804TimerPerformanceBase) #define SP804_TIMER_PERFORMANCE_BASE ((UINTN)PcdGet32 (PcdSP804TimerPerformanceBase))
// The notification function to call on every timer interrupt. // The notification function to call on every timer interrupt.
volatile EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL; EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL; EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
// The current period of the timer interrupt // The current period of the timer interrupt
volatile UINT64 mTimerPeriod = 0; UINT64 mTimerPeriod = 0;
// Cached copy of the Hardware Interrupt protocol instance // Cached copy of the Hardware Interrupt protocol instance
EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL; EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
@ -78,10 +78,10 @@ TimerInterruptHandler (
// If the interrupt is shared then we must check if this interrupt source is the one associated to this Timer // If the interrupt is shared then we must check if this interrupt source is the one associated to this Timer
if (MmioRead32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_MSK_INT_STS_REG) != 0) { if (MmioRead32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_MSK_INT_STS_REG) != 0) {
// clear the periodic interrupt // Clear the periodic interrupt
MmioWrite32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_INT_CLR_REG, 0); MmioWrite32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_INT_CLR_REG, 0);
// signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers // Signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers
gInterrupt->EndOfInterrupt (gInterrupt, Source); gInterrupt->EndOfInterrupt (gInterrupt, Source);
if (mTimerNotifyFunction) { if (mTimerNotifyFunction) {
@ -213,15 +213,13 @@ TimerDriverSetTimerPeriod (
// Disable timer 0/1 interrupt for a TimerPeriod of 0 // Disable timer 0/1 interrupt for a TimerPeriod of 0
Status = gInterrupt->DisableInterruptSource (gInterrupt, gVector); Status = gInterrupt->DisableInterruptSource (gInterrupt, gVector);
} else { } else {
// Convert TimerPeriod into 1MHz clock counts (us units = 100ns units / 10) // Convert TimerPeriod into 1MHz clock counts (us units = 100ns units * 10)
TimerTicks = DivU64x32 (TimerPeriod, 10); TimerTicks = DivU64x32 (TimerPeriod, 10);
TimerTicks = MultU64x32 (TimerTicks, PcdGet32(PcdSP804TimerFrequencyInMHz)); TimerTicks = MultU64x32 (TimerTicks, PcdGet32(PcdSP804TimerFrequencyInMHz));
// if it's larger than 32-bits, pin to highest value // if it's larger than 32-bits, pin to highest value
if (TimerTicks > 0xffffffff) { if (TimerTicks > 0xffffffff) {
TimerTicks = 0xffffffff; TimerTicks = 0xffffffff;
} }
// Program the SP804 timer with the new count value // Program the SP804 timer with the new count value

4
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
View File

@ -44,6 +44,7 @@
DebugAgentLib DebugAgentLib
IoLib IoLib
PrintLib PrintLib
SerialPortLib
[Ppis] [Ppis]
gEfiTemporaryRamSupportPpiGuid gEfiTemporaryRamSupportPpiGuid
@ -62,6 +63,3 @@
gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdNormalFvSize

1
ArmPlatformPkg/PrePi/PrePi.c
View File

@ -15,6 +15,7 @@
#include <PiPei.h> #include <PiPei.h>
#include <Library/DebugAgentLib.h> #include <Library/DebugAgentLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PrePiLib.h> #include <Library/PrePiLib.h>
#include <Library/IoLib.h> #include <Library/IoLib.h>
#include <Library/PrintLib.h> #include <Library/PrintLib.h>

2
BeagleBoardPkg/BeagleBoardPkg-next.dsc
View File

@ -77,7 +77,7 @@
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
DefaultExceptioHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
SerialPortLib|Omap35xxPkg/Library/SerialPortLib/SerialPortLib.inf SerialPortLib|Omap35xxPkg/Library/SerialPortLib/SerialPortLib.inf

2
BeagleBoardPkg/BeagleBoardPkg.dsc
View File

@ -77,7 +77,7 @@
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
DefaultExceptioHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
SerialPortLib|Omap35xxPkg/Library/SerialPortLib/SerialPortLib.inf SerialPortLib|Omap35xxPkg/Library/SerialPortLib/SerialPortLib.inf

6
BeagleBoardPkg/Library/EblCmdLib/EblCmdLib.c
View File

@ -44,7 +44,7 @@
@param Argc Number of command arguments in Argv @param Argc Number of command arguments in Argv
@param Argv Array of strings that represent the parsed command line. @param Argv Array of strings that represent the parsed command line.
Argv[0] is the comamnd name Argv[0] is the command name
@return EFI_SUCCESS @return EFI_SUCCESS
@ -122,7 +122,7 @@ EblSymbolTable (
@param Argc Number of command arguments in Argv @param Argc Number of command arguments in Argv
@param Argv Array of strings that represent the parsed command line. @param Argv Array of strings that represent the parsed command line.
Argv[0] is the comamnd name Argv[0] is the command name
@return EFI_SUCCESS @return EFI_SUCCESS
@ -204,7 +204,7 @@ CHAR8 *mTokenList[] = {
@param Argc Number of command arguments in Argv @param Argc Number of command arguments in Argv
@param Argv Array of strings that represent the parsed command line. @param Argv Array of strings that represent the parsed command line.
Argv[0] is the comamnd name Argv[0] is the command name
@return EFI_SUCCESS @return EFI_SUCCESS

4
EmbeddedPkg/Ebl/HwDebug.c
View File

@ -24,7 +24,7 @@
/** /**
Dump memory Dump memory
Argv[0] - "md"[.#] # is optiona width 1, 2, 4, or 8. Default 1 Argv[0] - "md"[.#] # is optional width 1, 2, 4, or 8. Default 1
Argv[1] - Hex Address to dump Argv[1] - Hex Address to dump
Argv[2] - Number of hex bytes to dump (0x20 is default) Argv[2] - Number of hex bytes to dump (0x20 is default)
@ -34,7 +34,7 @@
@param Argc Number of command arguments in Argv @param Argc Number of command arguments in Argv
@param Argv Array of strings that represent the parsed command line. @param Argv Array of strings that represent the parsed command line.
Argv[0] is the comamnd name Argv[0] is the command name
@return EFI_SUCCESS @return EFI_SUCCESS

2
EmbeddedPkg/EblExternCmd/EntryPointGlue.c
View File

@ -17,6 +17,8 @@
**/ **/
#include "Ebl.h"
#define CMD_SEPARATOR ';' #define CMD_SEPARATOR ';'
#define MAX_ARGS 32 #define MAX_ARGS 32

1
EmbeddedPkg/EblExternCmd/Main.c
View File

@ -23,6 +23,7 @@
**/ **/
#include "Ebl.h"
/** /**
Entry point with Argc, Argv. Put your code here. Entry point with Argc, Argv. Put your code here.

3
EmbeddedPkg/EmbeddedPkg.dsc
View File

@ -172,9 +172,6 @@
gEmbeddedTokenSpaceGuid.PcdPrePiHobBase|0 gEmbeddedTokenSpaceGuid.PcdPrePiHobBase|0
gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0 gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0
gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0 gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0
gEmbeddedTokenSpaceGuid.PcdPrePiTempMemorySize|0
gEmbeddedTokenSpaceGuid.PcdPrePiBfvBaseAddress|0
gEmbeddedTokenSpaceGuid.PcdPrePiBfvSize|0
# #
# Optinal feature to help prevent EFI memory map fragments # Optinal feature to help prevent EFI memory map fragments

6
EmbeddedPkg/GdbStub/Arm/Processor.c
View File

@ -195,7 +195,7 @@ BasicReadRegister (
} }
/** ‘p n’ /**
Reads the n-th register's value into an output buffer and sends it as a packet Reads the n-th register's value into an output buffer and sends it as a packet
@param SystemContext Register content at time of the exception @param SystemContext Register content at time of the exception
@param InBuffer Pointer to the input buffer received from gdb server @param InBuffer Pointer to the input buffer received from gdb server
@ -225,7 +225,7 @@ ReadNthRegister (
} }
/** ‘g’ /**
Reads the general registers into an output buffer and sends it as a packet Reads the general registers into an output buffer and sends it as a packet
@param SystemContext Register content at time of the exception @param SystemContext Register content at time of the exception
**/ **/
@ -452,7 +452,7 @@ RemoveSingleStep (
/** ‘c [addr ]’ /**
Continue. addr is Address to resume. If addr is omitted, resume at current Continue. addr is Address to resume. If addr is omitted, resume at current
Address. Address.

5
EmbeddedPkg/GdbStub/GdbStub.c
View File

@ -132,9 +132,8 @@ GdbStubEntry (
Status = DebugSupport->GetMaximumProcessorIndex (DebugSupport, &gMaxProcessorIndex); Status = DebugSupport->GetMaximumProcessorIndex (DebugSupport, &gMaxProcessorIndex);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// Make this an EFI_D_INFO after we get everything debugged. DEBUG ((EFI_D_INFO, "Debug Support Protocol ISA %x\n", DebugSupport->Isa));
DEBUG ((EFI_D_ERROR, "Debug Support Protocol ISA %x\n", DebugSupport->Isa)); DEBUG ((EFI_D_INFO, "Debug Support Protocol Processor Index %d\n", gMaxProcessorIndex));
DEBUG ((EFI_D_ERROR, "Debug Support Protocol Processor Index %d\n", gMaxProcessorIndex));
// Call processor-specific init routine // Call processor-specific init routine
InitializeProcessor(); InitializeProcessor();

6
EmbeddedPkg/Library/GdbDebugAgent/Arm/Processor.c
View File

@ -210,7 +210,7 @@ BasicReadRegister (
} }
/** ‘p n’ /**
Reads the n-th register's value into an output buffer and sends it as a packet Reads the n-th register's value into an output buffer and sends it as a packet
@param SystemContext Register content at time of the exception @param SystemContext Register content at time of the exception
@param InBuffer Pointer to the input buffer received from gdb server @param InBuffer Pointer to the input buffer received from gdb server
@ -240,7 +240,7 @@ ReadNthRegister (
} }
/** ‘g’ /**
Reads the general registers into an output buffer and sends it as a packet Reads the general registers into an output buffer and sends it as a packet
@param SystemContext Register content at time of the exception @param SystemContext Register content at time of the exception
**/ **/
@ -390,7 +390,7 @@ WriteGeneralRegisters (
/** ‘c [addr ]’ /**
Continue. addr is Address to resume. If addr is omitted, resume at current Continue. addr is Address to resume. If addr is omitted, resume at current
Address. Address.

1
EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.c
View File

@ -678,7 +678,6 @@ GdbFWrite (
case 'F': case 'F':
return; return;
break;
} }
} }
} }

10
EmbeddedPkg/Library/TemplateSerialPortLib/TemplateSerialPortLib.c
View File

@ -37,11 +37,11 @@ SerialPortInitialize (
/** /**
Write data to serial device. Write data to serial device.
@param Buffer Point of data buffer which need to be writed. @param Buffer Point of data buffer which need to be written.
@param NumberOfBytes Number of output bytes which are cached in Buffer. @param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Write data failed. @retval 0 Write data failed.
@retval !0 Actual number of bytes writed to serial device. @retval !0 Actual number of bytes written to serial device.
**/ **/
UINTN UINTN
@ -56,13 +56,13 @@ SerialPortWrite (
/** /**
Read data from serial device and save the datas in buffer. Read data from serial device and save the data in buffer.
@param Buffer Point of data buffer which need to be writed. @param Buffer Point of data buffer which need to be written.
@param NumberOfBytes Number of output bytes which are cached in Buffer. @param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Read data failed. @retval 0 Read data failed.
@retval !0 Aactual number of bytes read from serial device. @retval !0 Actual number of bytes read from serial device.
**/ **/
UINTN UINTN

45
EmbeddedPkg/Universal/MmcDxe/Diagnostics.c
View File

@ -25,13 +25,21 @@
CHAR16* mLogBuffer = NULL; CHAR16* mLogBuffer = NULL;
UINTN mLogRemainChar = 0; UINTN mLogRemainChar = 0;
CHAR16* DiagnosticInitLog(UINTN MaxBufferChar) { CHAR16*
DiagnosticInitLog (
UINTN MaxBufferChar
)
{
mLogRemainChar = MaxBufferChar; mLogRemainChar = MaxBufferChar;
mLogBuffer = AllocatePool ((UINTN)MaxBufferChar * sizeof(CHAR16)); mLogBuffer = AllocatePool ((UINTN)MaxBufferChar * sizeof(CHAR16));
return mLogBuffer; return mLogBuffer;
} }
UINTN DiagnosticLog(CONST CHAR16* Str) { UINTN
DiagnosticLog (
CONST CHAR16* Str
)
{
UINTN len = StrLen (Str); UINTN len = StrLen (Str);
if (len <= mLogRemainChar) { if (len <= mLogRemainChar) {
mLogRemainChar -= len; mLogRemainChar -= len;
@ -43,7 +51,12 @@ UINTN DiagnosticLog(CONST CHAR16* Str) {
} }
} }
VOID GenerateRandomBuffer(VOID* Buffer, UINTN BufferSize) { VOID
GenerateRandomBuffer (
VOID* Buffer,
UINTN BufferSize
)
{
UINT64 i; UINT64 i;
UINT64* Buffer64 = (UINT64*)Buffer; UINT64* Buffer64 = (UINT64*)Buffer;
@ -53,7 +66,13 @@ VOID GenerateRandomBuffer(VOID* Buffer, UINTN BufferSize) {
} }
} }
BOOLEAN CompareBuffer(VOID *BufferA, VOID *BufferB, UINTN BufferSize) { BOOLEAN
CompareBuffer (
VOID *BufferA,
VOID *BufferB,
UINTN BufferSize
)
{
UINTN i; UINTN i;
UINT64* BufferA64 = (UINT64*)BufferA; UINT64* BufferA64 = (UINT64*)BufferA;
UINT64* BufferB64 = (UINT64*)BufferB; UINT64* BufferB64 = (UINT64*)BufferB;
@ -70,7 +89,13 @@ BOOLEAN CompareBuffer(VOID *BufferA, VOID *BufferB, UINTN BufferSize) {
return TRUE; return TRUE;
} }
EFI_STATUS MmcReadWriteDataTest(MMC_HOST_INSTANCE *MmcHostInstance, EFI_LBA Lba, UINTN BufferSize) { EFI_STATUS
MmcReadWriteDataTest (
MMC_HOST_INSTANCE *MmcHostInstance,
EFI_LBA Lba,
UINTN BufferSize
)
{
VOID *BackBuffer; VOID *BackBuffer;
VOID *WriteBuffer; VOID *WriteBuffer;
VOID *ReadBuffer; VOID *ReadBuffer;
@ -159,11 +184,11 @@ MmcDriverDiagnosticsRunDiagnostics (
MMC_HOST_INSTANCE *MmcHostInstance; MMC_HOST_INSTANCE *MmcHostInstance;
EFI_STATUS Status; EFI_STATUS Status;
if (Language == NULL || if ((Language == NULL) ||
ErrorType == NULL || (ErrorType == NULL) ||
Buffer == NULL || (Buffer == NULL) ||
ControllerHandle == NULL || (ControllerHandle == NULL) ||
BufferSize == NULL) { (BufferSize == NULL)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }

3
Omap35xxPkg/InterruptDxe/InterruptDxe.inf
View File

@ -43,9 +43,6 @@
IoLib IoLib
ArmLib ArmLib
[Guids]
[Protocols] [Protocols]
gHardwareInterruptProtocolGuid gHardwareInterruptProtocolGuid
gEfiCpuArchProtocolGuid gEfiCpuArchProtocolGuid

2
Omap35xxPkg/Library/EblCmdLib/EblCmdLib.c
View File

@ -36,7 +36,7 @@
@param Argc Number of command arguments in Argv @param Argc Number of command arguments in Argv
@param Argv Array of strings that represent the parsed command line. @param Argv Array of strings that represent the parsed command line.
Argv[0] is the comamnd name Argv[0] is the command name
@return EFI_SUCCESS @return EFI_SUCCESS