mirror of https://github.com/acidanthera/audk.git
DynamicTablesPkg: Move Pci Interrupt Map Info to Arch Common
Move Pci Interrupt Map Info object from Arm Namespace to the Arch Common namespace. Correspondingly also update the following modules to reflect the changes introduced by the move: - SSDT PCIe library - ConfigurationManagerObjectParser - Dynamic Plat Repo TokenFixer map - FdtHwInfoParserLib/Pci/ArmPciConfigSpaceParser. Cc: Pierre Gondois <Pierre.Gondois@arm.com> Cc: Yeo Reum Yun <YeoReum.Yun@arm.com> Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com> Cc: Jeshua Smith <jeshuas@nvidia.com> Cc: Jeff Brasen <jbrasen@nvidia.com> Cc: Girish Mahadevan <gmahadevan@nvidia.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
This commit is contained in:
Sami Mujawar
mergify[bot]
parent
4333f5c316
commit
11dcf74d42
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@ -30,6 +30,7 @@ typedef enum ArchCommonObjectID {
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EArchCommonObjCmRef, ///< 7 - CM Object Reference
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EArchCommonObjPciConfigSpaceInfo, ///< 8 - PCI Configuration Space Info
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EArchCommonObjPciAddressMapInfo, ///< 9 - Pci Address Map Info
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EArchCommonObjPciInterruptMapInfo, ///< 10 - Pci Interrupt Map Info
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EArchCommonObjMax
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} EARCH_COMMON_OBJECT_ID;
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@ -185,6 +186,43 @@ typedef struct CmArchCommonGenericInterrupt {
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UINT32 Flags;
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} CM_ARCH_COMMON_GENERIC_INTERRUPT;
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/** A structure that describes a PCI Interrupt Map.
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The legacy PCI interrupts used by PCI devices are described by this object.
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Cf Devicetree Specification - Release v0.3
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s2.4.3 "Interrupt Nexus Properties"
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ID: EArchCommonObjPciInterruptMapInfo
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*/
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typedef struct CmArchCommonPciInterruptMapInfo {
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/// Pci Bus.
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/// Value on 8 bits (max 255).
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UINT8 PciBus;
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/// Pci Device.
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/// Value on 5 bits (max 31).
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UINT8 PciDevice;
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/** PCI interrupt
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ACPI bindings are used:
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Cf. ACPI 6.4, s6.2.13 _PRT (PCI Routing Table):
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"0-INTA, 1-INTB, 2-INTC, 3-INTD"
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Device-tree bindings are shifted by 1:
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"INTA=1, INTB=2, INTC=3, INTD=4"
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*/
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UINT8 PciInterrupt;
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/** Interrupt controller interrupt.
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Cf Devicetree Specification - Release v0.3
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s2.4.3 "Interrupt Nexus Properties": "parent interrupt specifier"
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*/
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CM_ARCH_COMMON_GENERIC_INTERRUPT IntcInterrupt;
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} CM_ARCH_COMMON_PCI_INTERRUPT_MAP_INFO;
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#pragma pack()
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#endif // ARCH_COMMON_NAMESPACE_OBJECTS_H_
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@ -56,18 +56,17 @@ typedef enum ArmObjectID {
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EArmObjGenericInitiatorAffinityInfo, ///< 25 - Generic Initiator Affinity
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EArmObjCmn600Info, ///< 26 - CMN-600 Info
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EArmObjLpiInfo, ///< 27 - Lpi Info
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EArmObjPciInterruptMapInfo, ///< 28 - Pci Interrupt Map Info
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EArmObjRmr, ///< 29 - Reserved Memory Range Node
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EArmObjMemoryRangeDescriptor, ///< 30 - Memory Range Descriptor
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EArmObjCpcInfo, ///< 31 - Continuous Performance Control Info
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EArmObjPccSubspaceType0Info, ///< 32 - Pcc Subspace Type 0 Info
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EArmObjPccSubspaceType1Info, ///< 33 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType2Info, ///< 34 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType3Info, ///< 35 - Pcc Subspace Type 3 Info
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EArmObjPccSubspaceType4Info, ///< 36 - Pcc Subspace Type 4 Info
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EArmObjPccSubspaceType5Info, ///< 37 - Pcc Subspace Type 5 Info
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EArmObjEtInfo, ///< 38 - Embedded Trace Extension/Module Info
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EArmObjPsdInfo, ///< 39 - P-State Dependency (PSD) Info
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EArmObjRmr, ///< 28 - Reserved Memory Range Node
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EArmObjMemoryRangeDescriptor, ///< 29 - Memory Range Descriptor
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EArmObjCpcInfo, ///< 30 - Continuous Performance Control Info
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EArmObjPccSubspaceType0Info, ///< 31 - Pcc Subspace Type 0 Info
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EArmObjPccSubspaceType1Info, ///< 32 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType2Info, ///< 33 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType3Info, ///< 34 - Pcc Subspace Type 3 Info
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EArmObjPccSubspaceType4Info, ///< 35 - Pcc Subspace Type 4 Info
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EArmObjPccSubspaceType5Info, ///< 36 - Pcc Subspace Type 5 Info
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EArmObjEtInfo, ///< 37 - Embedded Trace Extension/Module Info
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EArmObjPsdInfo, ///< 38 - P-State Dependency (PSD) Info
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EArmObjMax
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} EARM_OBJECT_ID;
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@ -885,43 +884,6 @@ typedef struct CmArmLpiInfo {
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CHAR8 StateName[16];
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} CM_ARM_LPI_INFO;
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/** A structure that describes a PCI Interrupt Map.
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The legacy PCI interrupts used by PCI devices are described by this object.
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Cf Devicetree Specification - Release v0.3
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s2.4.3 "Interrupt Nexus Properties"
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ID: EArmObjPciInterruptMapInfo
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*/
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typedef struct CmArmPciInterruptMapInfo {
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/// Pci Bus.
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/// Value on 8 bits (max 255).
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UINT8 PciBus;
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/// Pci Device.
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/// Value on 5 bits (max 31).
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UINT8 PciDevice;
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/** PCI interrupt
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ACPI bindings are used:
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Cf. ACPI 6.4, s6.2.13 _PRT (PCI Routing Table):
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"0-INTA, 1-INTB, 2-INTC, 3-INTD"
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Device-tree bindings are shifted by 1:
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"INTA=1, INTB=2, INTC=3, INTD=4"
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*/
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UINT8 PciInterrupt;
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/** Interrupt controller interrupt.
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Cf Devicetree Specification - Release v0.3
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s2.4.3 "Interrupt Nexus Properties": "parent interrupt specifier"
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*/
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CM_ARCH_COMMON_GENERIC_INTERRUPT IntcInterrupt;
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} CM_ARM_PCI_INTERRUPT_MAP_INFO;
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/** A structure that describes the
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RMR node for the Platform.
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@ -45,7 +45,7 @@ Requirements:
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- EArchCommonObjCmRef
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- EArchCommonObjPciConfigSpaceInfo
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- EArchCommonObjPciAddressMapInfo
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- EArmObjPciInterruptMapInfo
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- EArchCommonObjPciInterruptMapInfo
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*/
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/** This macro expands to a function that retrieves the cross-CM-object-
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@ -79,9 +79,9 @@ GET_OBJECT_LIST (
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Interrupt Mapping Information from the Configuration Manager.
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*/
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GET_OBJECT_LIST (
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EObjNameSpaceArm,
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EArmObjPciInterruptMapInfo,
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CM_ARM_PCI_INTERRUPT_MAP_INFO
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EObjNameSpaceArchCommon,
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EArchCommonObjPciInterruptMapInfo,
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CM_ARCH_COMMON_PCI_INTERRUPT_MAP_INFO
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);
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/** Initialize the MappingTable.
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@ -310,12 +310,12 @@ GeneratePrt (
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IN OUT AML_OBJECT_NODE_HANDLE PciNode
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)
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{
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EFI_STATUS Status;
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INT32 Index;
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AML_OBJECT_NODE_HANDLE PrtNode;
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CM_ARCH_COMMON_OBJ_REF *RefInfo;
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UINT32 RefCount;
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CM_ARM_PCI_INTERRUPT_MAP_INFO *IrqMapInfo;
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EFI_STATUS Status;
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INT32 Index;
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AML_OBJECT_NODE_HANDLE PrtNode;
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CM_ARCH_COMMON_OBJ_REF *RefInfo;
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UINT32 RefCount;
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CM_ARCH_COMMON_PCI_INTERRUPT_MAP_INFO *IrqMapInfo;
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ASSERT (Generator != NULL);
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ASSERT (CfgMgrProtocol != NULL);
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@ -325,7 +325,7 @@ GeneratePrt (
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PrtNode = NULL;
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// Get the array of CM_ARCH_COMMON_OBJ_REF referencing the
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// CM_ARM_PCI_INTERRUPT_MAP_INFO objects.
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// CM_ARCH_COMMON_PCI_INTERRUPT_MAP_INFO objects.
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Status = GetEArchCommonObjCmRef (
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CfgMgrProtocol,
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PciInfo->InterruptMapToken,
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@ -352,8 +352,8 @@ GeneratePrt (
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}
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for (Index = 0; Index < RefCount; Index++) {
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// Get CM_ARM_PCI_INTERRUPT_MAP_INFO structures one by one.
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Status = GetEArmObjPciInterruptMapInfo (
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// Get CM_ARCH_COMMON_PCI_INTERRUPT_MAP_INFO structures one by one.
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Status = GetEArchCommonObjPciInterruptMapInfo (
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CfgMgrProtocol,
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RefInfo[Index].ReferenceToken,
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&IrqMapInfo,
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@ -171,18 +171,17 @@ CM_OBJECT_TOKEN_FIXER TokenFixer[EArmObjMax] = {
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NULL, ///< 25 - Generic Initiator Affinity
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NULL, ///< 26 - CMN-600 Info
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NULL, ///< 27 - Lpi Info
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NULL, ///< 28 - Pci Interrupt Map Info
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NULL, ///< 29 - Reserved Memory Range Node
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NULL, ///< 30 - Memory Range Descriptor
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NULL, ///< 31 - Continuous Performance Control Info
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NULL, ///< 32 - Pcc Subspace Type 0 Info
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NULL, ///< 28 - Reserved Memory Range Node
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NULL, ///< 29 - Memory Range Descriptor
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NULL, ///< 30 - Continuous Performance Control Info
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NULL, ///< 31 - Pcc Subspace Type 0 Info
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NULL, ///< 32 - Pcc Subspace Type 2 Info
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NULL, ///< 33 - Pcc Subspace Type 2 Info
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NULL, ///< 34 - Pcc Subspace Type 2 Info
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NULL, ///< 35 - Pcc Subspace Type 3 Info
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NULL, ///< 36 - Pcc Subspace Type 4 Info
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NULL, ///< 37 - Pcc Subspace Type 5 Info
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NULL, ///< 38 - Embedded Trace Extension/Module Info
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NULL ///< 39 - P-State Dependency (PSD) Info
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NULL, ///< 34 - Pcc Subspace Type 3 Info
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NULL, ///< 35 - Pcc Subspace Type 4 Info
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NULL, ///< 36 - Pcc Subspace Type 5 Info
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NULL, ///< 37 - Embedded Trace Extension/Module Info
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NULL ///< 38 - P-State Dependency (PSD) Info
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};
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/** CmObj token fixer.
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@ -449,9 +449,9 @@ STATIC CONST CM_OBJ_PARSER CmArchCommonPciAddressMapInfoParser[] = {
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{ "AddressSize", 8, "0x%llx", NULL },
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};
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/** A parser for EArmObjPciInterruptMapInfo.
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/** A parser for EArchCommonObjPciInterruptMapInfo.
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*/
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STATIC CONST CM_OBJ_PARSER CmPciInterruptMapInfoParser[] = {
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STATIC CONST CM_OBJ_PARSER CmArchCommonPciInterruptMapInfoParser[] = {
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{ "PciBus", 1, "0x%x", NULL },
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{ "PciDevice", 1, "0x%x", NULL },
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{ "PciInterrupt", 1, "0x%x", NULL },
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@ -680,6 +680,7 @@ STATIC CONST CM_OBJ_PARSER_ARRAY ArchCommonNamespaceObjectParser[] = {
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CM_PARSER_ADD_OBJECT (EArchCommonObjCmRef, CmArchCommonObjRefParser),
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CM_PARSER_ADD_OBJECT (EArchCommonObjPciConfigSpaceInfo, CmArchCommonPciConfigSpaceInfoParser),
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CM_PARSER_ADD_OBJECT (EArchCommonObjPciAddressMapInfo, CmArchCommonPciAddressMapInfoParser),
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CM_PARSER_ADD_OBJECT (EArchCommonObjPciInterruptMapInfo, CmArchCommonPciInterruptMapInfoParser),
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CM_PARSER_ADD_OBJECT_RESERVED (EArchCommonObjMax)
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};
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@ -714,7 +715,6 @@ STATIC CONST CM_OBJ_PARSER_ARRAY ArmNamespaceObjectParser[] = {
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CM_PARSER_ADD_OBJECT (EArmObjGenericInitiatorAffinityInfo,CmArmGenericInitiatorAffinityInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjCmn600Info, CmArmCmn600InfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjLpiInfo, CmArmLpiInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjPciInterruptMapInfo, CmPciInterruptMapInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjRmr, CmArmRmrInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjMemoryRangeDescriptor, CmArmMemoryRangeDescriptorInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjCpcInfo, CmArmCpcInfoParser),
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@ -311,8 +311,8 @@ ParseIrqMap (
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UINT32 PciAddressAttr;
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CM_ARM_PCI_INTERRUPT_MAP_INFO *PciInterruptMapInfo;
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UINT32 BufferSize;
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CM_ARCH_COMMON_PCI_INTERRUPT_MAP_INFO *PciInterruptMapInfo;
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UINT32 BufferSize;
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Data = fdt_getprop (Fdt, HostPciNode, "interrupt-map", &DataSize);
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if ((Data == NULL) || (DataSize <= 0)) {
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@ -455,9 +455,9 @@ ParseIrqMap (
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} // for
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PciInfo->Mapping[PciMappingTableInterrupt].ObjectId =
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CREATE_CM_ARM_OBJECT_ID (EArmObjPciInterruptMapInfo);
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CREATE_CM_ARCH_COMMON_OBJECT_ID (EArchCommonObjPciInterruptMapInfo);
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PciInfo->Mapping[PciMappingTableInterrupt].Size =
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sizeof (CM_ARM_PCI_INTERRUPT_MAP_INFO) * IrqMapCount;
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sizeof (CM_ARCH_COMMON_PCI_INTERRUPT_MAP_INFO) * IrqMapCount;
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PciInfo->Mapping[PciMappingTableInterrupt].Data = PciInterruptMapInfo;
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PciInfo->Mapping[PciMappingTableInterrupt].Count = IrqMapCount;
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@ -581,7 +581,7 @@ PciNodeParser (
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CmObj of the following types are concerned:
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- EArchCommonObjPciConfigSpaceInfo
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- EArchCommonObjPciAddressMapInfo
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- EArmObjPciInterruptMapInfo
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- EArchCommonObjPciInterruptMapInfo
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@param [in] FdtParserHandle A handle to the parser instance.
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@param [in] PciTableInfo PCI_PARSER_TABLE structure containing the
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@ -701,12 +701,12 @@ FreeParserTable (
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UINT64 AddressSize; // {Populated}
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} CM_ARCH_COMMON_PCI_ADDRESS_MAP_INFO;
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typedef struct CmArmPciInterruptMapInfo {
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typedef struct CmArchCommonPciInterruptMapInfo {
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UINT8 PciBus; // {Populated}
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UINT8 PciDevice; // {Populated}
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UINT8 PciInterrupt; // {Populated}
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CM_ARCH_COMMON_GENERIC_INTERRUPT IntcInterrupt; // {Populated}
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} CM_ARM_PCI_INTERRUPT_MAP_INFO;
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} CM_ARCH_COMMON_PCI_INTERRUPT_MAP_INFO;
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A parser parses a Device Tree to populate a specific CmObj type. None,
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one or many CmObj can be created by the parser.
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@ -109,12 +109,12 @@ typedef struct PciParserTable {
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UINT64 AddressSize; // {Populated}
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} CM_ARCH_COMMON_PCI_ADDRESS_MAP_INFO;
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typedef struct CmArmPciInterruptMapInfo {
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typedef struct CmArchCommonPciInterruptMapInfo {
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UINT8 PciBus; // {Populated}
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UINT8 PciDevice; // {Populated}
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UINT8 PciInterrupt; // {Populated}
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CM_ARCH_COMMON_GENERIC_INTERRUPT IntcInterrupt; // {Populated}
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} CM_ARM_PCI_INTERRUPT_MAP_INFO;
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} CM_ARCH_COMMON_PCI_INTERRUPT_MAP_INFO;
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A parser parses a Device Tree to populate a specific CmObj type. None,
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one or many CmObj can be created by the parser.
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@ -468,18 +468,17 @@ The CM_OBJECT_ID type is used to identify the Configuration Manager
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| 25 | Generic Initiator Affinity Info | Move to Arch Common NS |
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| 26 | CMN 600 Info | |
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| 27 | Low Power Idle State Info | Move to Arch Common NS |
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| 28 | PCI Interrupt Map Info | Move to Arch Common NS |
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| 29 | Reserved Memory Range Node | |
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| 30 | Memory Range Descriptor | |
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| 31 | Continuous Performance Control Info | Move to Arch Common NS |
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| 32 | Pcc Subspace Type 0 Info | Move to Arch Common NS |
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| 33 | Pcc Subspace Type 1 Info | Move to Arch Common NS |
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| 34 | Pcc Subspace Type 2 Info | Move to Arch Common NS |
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| 35 | Pcc Subspace Type 3 Info | Move to Arch Common NS |
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| 36 | Pcc Subspace Type 4 Info | Move to Arch Common NS |
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| 37 | Pcc Subspace Type 5 Info | Move to Arch Common NS |
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| 38 | Embedded Trace Extension/Module Info | |
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| 39 | P-State Dependency (PSD) Info | Move to Arch Common NS |
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| 28 | Reserved Memory Range Node | |
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| 29 | Memory Range Descriptor | |
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| 30 | Continuous Performance Control Info | Move to Arch Common NS |
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| 31 | Pcc Subspace Type 0 Info | Move to Arch Common NS |
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| 32 | Pcc Subspace Type 1 Info | Move to Arch Common NS |
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| 33 | Pcc Subspace Type 2 Info | Move to Arch Common NS |
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| 34 | Pcc Subspace Type 3 Info | Move to Arch Common NS |
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| 35 | Pcc Subspace Type 4 Info | Move to Arch Common NS |
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| 36 | Pcc Subspace Type 5 Info | Move to Arch Common NS |
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| 37 | Embedded Trace Extension/Module Info | |
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| 38 | P-State Dependency (PSD) Info | Move to Arch Common NS |
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| `*` | All other values are reserved. | |
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#### Object ID's in the Arch Common Namespace:
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@ -496,4 +495,5 @@ The CM_OBJECT_ID type is used to identify the Configuration Manager
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| 7 | CM Object Reference | |
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| 8 | PCI Configuration Space Info | |
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| 9 | PCI Address Map Info | |
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| 10 | PCI Interrupt Map Info | |
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| `*` | All other values are reserved. | |
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