mirror of https://github.com/acidanthera/audk.git
ArmPkg/ArmCpuLib: Removed unused files
Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13250 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
parent
b1d41be7c9
commit
124dfbf6da
|
|
@ -1,67 +0,0 @@
|
|||
//
|
||||
// Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//
|
||||
|
||||
#include <Library/ArmCpuLib.h>
|
||||
|
||||
.text
|
||||
.align 3
|
||||
|
||||
GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
|
||||
GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
|
||||
|
||||
// VOID
|
||||
// ArmCpuSynchronizeWait (
|
||||
// IN ARM_CPU_SYNCHRONIZE_EVENT Event
|
||||
// );
|
||||
ASM_PFX(ArmCpuSynchronizeWait):
|
||||
cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
|
||||
// The SCU enabled is the event to tell us the Init Boot Memory is initialized
|
||||
bx lr
|
||||
b ASM_PFX(CArmCpuSynchronizeWait)
|
||||
|
||||
|
||||
#if 0
|
||||
GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
|
||||
GCC_ASM_EXPORT(ArmGetScuBaseAddress)
|
||||
GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
|
||||
|
||||
// VOID
|
||||
// ArmCpuSynchronizeWait (
|
||||
// IN ARM_CPU_SYNCHRONIZE_EVENT Event
|
||||
// );
|
||||
ASM_PFX(ArmCpuSynchronizeWait):
|
||||
cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
|
||||
// The SCU enabled is the event to tell us the Init Boot Memory is initialized
|
||||
beq ArmWaitScuEnabled
|
||||
b ASM_PFX(CArmCpuSynchronizeWait)
|
||||
|
||||
// IN None
|
||||
// OUT r0 = SCU Base Address
|
||||
ASM_PFX(ArmGetScuBaseAddress):
|
||||
// Read Configuration Base Address Register. ArmCBar cannot be called to get
|
||||
// the Configuration BAR as a stack is not necessary setup. The SCU is at the
|
||||
// offset 0x0000 from the Private Memory Region.
|
||||
mrc p15, 4, r0, c15, c0, 0
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmWaitScuEnabled):
|
||||
// Read Configuration Base Address Register. ArmCBar cannot be called to get
|
||||
// the Configuration BAR as a stack is not necessary setup. The SCU is at the
|
||||
// offset 0x0000 from the Private Memory Region.
|
||||
mrc p15, 4, r0, c15, c0, 0
|
||||
add r0, r0, #A9_SCU_CONTROL_OFFSET
|
||||
ldr r0, [r0]
|
||||
cmp r0, #1
|
||||
bne ArmWaitScuEnabled
|
||||
bx lr
|
||||
#endif
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
//
|
||||
// Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//
|
||||
|
||||
#include <Library/ArmCpuLib.h>
|
||||
#include <Chipset/ArmCortexA9.h>
|
||||
|
||||
EXPORT ArmCpuSynchronizeWait
|
||||
EXPORT ArmGetScuBaseAddress
|
||||
IMPORT CArmCpuSynchronizeWait
|
||||
|
||||
PRESERVE8
|
||||
AREA ArmCortexA9Helper, CODE, READONLY
|
||||
|
||||
// VOID
|
||||
// ArmCpuSynchronizeWait (
|
||||
// IN ARM_CPU_SYNCHRONIZE_EVENT Event
|
||||
// );
|
||||
ArmCpuSynchronizeWait
|
||||
cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
|
||||
// The SCU enabled is the event to tell us the Init Boot Memory is initialized
|
||||
beq ArmWaitScuEnabled
|
||||
b CArmCpuSynchronizeWait
|
||||
|
||||
// IN None
|
||||
// OUT r0 = SCU Base Address
|
||||
ArmGetScuBaseAddress
|
||||
// Read Configuration Base Address Register. ArmCBar cannot be called to get
|
||||
// the Configuration BAR as a stack is not necessary setup. The SCU is at the
|
||||
// offset 0x0000 from the Private Memory Region.
|
||||
mrc p15, 4, r0, c15, c0, 0
|
||||
bx lr
|
||||
|
||||
ArmWaitScuEnabled
|
||||
// Read Configuration Base Address Register. ArmCBar cannot be called to get
|
||||
// the Configuration BAR as a stack is not necessary setup. The SCU is at the
|
||||
// offset 0x0000 from the Private Memory Region.
|
||||
mrc p15, 4, r0, c15, c0, 0
|
||||
add r0, r0, #A9_SCU_CONTROL_OFFSET
|
||||
ldr r0, [r0]
|
||||
cmp r0, #1
|
||||
bne ArmWaitScuEnabled
|
||||
bx lr
|
||||
|
||||
END
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
//
|
||||
// Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//
|
||||
|
||||
#include <AsmMacroIoLib.h>
|
||||
#include <Library/ArmCpuLib.h>
|
||||
#include <Library/ArmGicLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Chipset/ArmV7.h>
|
||||
|
||||
.text
|
||||
.align 3
|
||||
|
||||
GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
|
||||
GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
|
||||
// Dirty hack to get the Fixed value of GicDistributorBase
|
||||
GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdGicDistributorBase)
|
||||
|
||||
|
||||
// VOID
|
||||
// ArmCpuSynchronizeWait (
|
||||
// IN ARM_CPU_SYNCHRONIZE_EVENT Event
|
||||
// );
|
||||
ASM_PFX(ArmCpuSynchronizeWait):
|
||||
cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
|
||||
// The SCU enabled is the event to tell us the Init Boot Memory is initialized
|
||||
beq ArmWaitGicDistributorEnabled
|
||||
push {r1,lr}
|
||||
LoadConstantToReg (ASM_PFX(CArmCpuSynchronizeWait), r1)
|
||||
blx r1
|
||||
pop {r1,lr}
|
||||
bx lr
|
||||
|
||||
// IN None
|
||||
ArmWaitGicDistributorEnabled:
|
||||
LoadConstantToReg (ASM_PFX(_gPcd_FixedAtBuild_PcdGicDistributorBase), r0)
|
||||
ldr r0, [r0]
|
||||
_WaitGicDistributor:
|
||||
ldr r1, [r0, #ARM_GIC_ICDDCR]
|
||||
cmp r1, #1
|
||||
bne _WaitGicDistributor
|
||||
bx lr
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
//
|
||||
// Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//
|
||||
|
||||
#include <AsmMacroIoLib.h>
|
||||
#include <Library/ArmCpuLib.h>
|
||||
#include <Library/ArmGicLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Chipset/ArmV7.h>
|
||||
|
||||
INCLUDE AsmMacroIoLib.inc
|
||||
|
||||
EXPORT ArmCpuSynchronizeWait
|
||||
IMPORT CArmCpuSynchronizeWait
|
||||
// Dirty hack to get the Fixed value of GicDistributorBase
|
||||
IMPORT _gPcd_FixedAtBuild_PcdGicDistributorBase
|
||||
|
||||
PRESERVE8
|
||||
AREA ArmCortexA15Helper, CODE, READONLY
|
||||
|
||||
// VOID
|
||||
// ArmCpuSynchronizeWait (
|
||||
// IN ARM_CPU_SYNCHRONIZE_EVENT Event
|
||||
// );
|
||||
ArmCpuSynchronizeWait
|
||||
cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
|
||||
// The SCU enabled is the event to tell us the Init Boot Memory is initialized
|
||||
beq ArmWaitGicDistributorEnabled
|
||||
// Case when the stack has been set up
|
||||
push {r1,lr}
|
||||
LoadConstantToReg (CArmCpuSynchronizeWait, r1)
|
||||
blx r1
|
||||
pop {r1,lr}
|
||||
bx lr
|
||||
|
||||
|
||||
// IN None
|
||||
ArmWaitGicDistributorEnabled
|
||||
LoadConstantToReg (_gPcd_FixedAtBuild_PcdGicDistributorBase, r0)
|
||||
ldr r0, [r0]
|
||||
_WaitGicDistributor
|
||||
ldr r1, [r0, #ARM_GIC_ICDDCR]
|
||||
cmp r1, #1
|
||||
bne _WaitGicDistributor
|
||||
bx lr
|
||||
|
||||
END
|
||||
Loading…
Reference in New Issue