mirror of https://github.com/acidanthera/audk.git
ArmPkg/ArmCpuLib: Removed unused files
Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13250 6f19259b-4bc3-4df7-8a09-765794883524
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oliviermartin
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <Library/ArmCpuLib.h>
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.text
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.align 3
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GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
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GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
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// VOID
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// ArmCpuSynchronizeWait (
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// IN ARM_CPU_SYNCHRONIZE_EVENT Event
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// );
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ASM_PFX(ArmCpuSynchronizeWait):
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cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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// The SCU enabled is the event to tell us the Init Boot Memory is initialized
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bx lr
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b ASM_PFX(CArmCpuSynchronizeWait)
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#if 0
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GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
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GCC_ASM_EXPORT(ArmGetScuBaseAddress)
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GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
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// VOID
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// ArmCpuSynchronizeWait (
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// IN ARM_CPU_SYNCHRONIZE_EVENT Event
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// );
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ASM_PFX(ArmCpuSynchronizeWait):
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cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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// The SCU enabled is the event to tell us the Init Boot Memory is initialized
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beq ArmWaitScuEnabled
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b ASM_PFX(CArmCpuSynchronizeWait)
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// IN None
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// OUT r0 = SCU Base Address
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ASM_PFX(ArmGetScuBaseAddress):
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// Read Configuration Base Address Register. ArmCBar cannot be called to get
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// the Configuration BAR as a stack is not necessary setup. The SCU is at the
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// offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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bx lr
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ASM_PFX(ArmWaitScuEnabled):
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// Read Configuration Base Address Register. ArmCBar cannot be called to get
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// the Configuration BAR as a stack is not necessary setup. The SCU is at the
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// offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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add r0, r0, #A9_SCU_CONTROL_OFFSET
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ldr r0, [r0]
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cmp r0, #1
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bne ArmWaitScuEnabled
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bx lr
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#endif
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <Library/ArmCpuLib.h>
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#include <Chipset/ArmCortexA9.h>
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EXPORT ArmCpuSynchronizeWait
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EXPORT ArmGetScuBaseAddress
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IMPORT CArmCpuSynchronizeWait
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PRESERVE8
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AREA ArmCortexA9Helper, CODE, READONLY
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// VOID
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// ArmCpuSynchronizeWait (
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// IN ARM_CPU_SYNCHRONIZE_EVENT Event
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// );
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ArmCpuSynchronizeWait
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cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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// The SCU enabled is the event to tell us the Init Boot Memory is initialized
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beq ArmWaitScuEnabled
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b CArmCpuSynchronizeWait
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// IN None
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// OUT r0 = SCU Base Address
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ArmGetScuBaseAddress
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// Read Configuration Base Address Register. ArmCBar cannot be called to get
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// the Configuration BAR as a stack is not necessary setup. The SCU is at the
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// offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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bx lr
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ArmWaitScuEnabled
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// Read Configuration Base Address Register. ArmCBar cannot be called to get
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// the Configuration BAR as a stack is not necessary setup. The SCU is at the
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// offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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add r0, r0, #A9_SCU_CONTROL_OFFSET
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ldr r0, [r0]
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cmp r0, #1
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bne ArmWaitScuEnabled
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bx lr
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END
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <AsmMacroIoLib.h>
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#include <Library/ArmCpuLib.h>
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#include <Library/ArmGicLib.h>
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#include <Library/PcdLib.h>
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#include <Chipset/ArmV7.h>
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.text
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.align 3
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GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
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GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
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// Dirty hack to get the Fixed value of GicDistributorBase
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GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdGicDistributorBase)
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// VOID
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// ArmCpuSynchronizeWait (
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// IN ARM_CPU_SYNCHRONIZE_EVENT Event
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// );
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ASM_PFX(ArmCpuSynchronizeWait):
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cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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// The SCU enabled is the event to tell us the Init Boot Memory is initialized
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beq ArmWaitGicDistributorEnabled
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push {r1,lr}
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LoadConstantToReg (ASM_PFX(CArmCpuSynchronizeWait), r1)
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blx r1
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pop {r1,lr}
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bx lr
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// IN None
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ArmWaitGicDistributorEnabled:
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LoadConstantToReg (ASM_PFX(_gPcd_FixedAtBuild_PcdGicDistributorBase), r0)
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ldr r0, [r0]
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_WaitGicDistributor:
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ldr r1, [r0, #ARM_GIC_ICDDCR]
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cmp r1, #1
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bne _WaitGicDistributor
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bx lr
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@ -1,56 +0,0 @@
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <AsmMacroIoLib.h>
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#include <Library/ArmCpuLib.h>
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#include <Library/ArmGicLib.h>
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#include <Library/PcdLib.h>
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#include <Chipset/ArmV7.h>
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INCLUDE AsmMacroIoLib.inc
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EXPORT ArmCpuSynchronizeWait
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IMPORT CArmCpuSynchronizeWait
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// Dirty hack to get the Fixed value of GicDistributorBase
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IMPORT _gPcd_FixedAtBuild_PcdGicDistributorBase
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PRESERVE8
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AREA ArmCortexA15Helper, CODE, READONLY
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// VOID
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// ArmCpuSynchronizeWait (
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// IN ARM_CPU_SYNCHRONIZE_EVENT Event
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// );
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ArmCpuSynchronizeWait
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cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
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// The SCU enabled is the event to tell us the Init Boot Memory is initialized
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beq ArmWaitGicDistributorEnabled
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// Case when the stack has been set up
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push {r1,lr}
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LoadConstantToReg (CArmCpuSynchronizeWait, r1)
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blx r1
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pop {r1,lr}
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bx lr
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// IN None
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ArmWaitGicDistributorEnabled
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LoadConstantToReg (_gPcd_FixedAtBuild_PcdGicDistributorBase, r0)
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ldr r0, [r0]
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_WaitGicDistributor
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ldr r1, [r0, #ARM_GIC_ICDDCR]
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cmp r1, #1
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bne _WaitGicDistributor
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bx lr
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END
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