mirror of https://github.com/acidanthera/audk.git
DynamicTablesPkg: FdtHwInfoParserLib: Parse Pmu info
Parse the Pmu interrupts if a pmu compatible node is present, and populate the MADT GicC structure accordingly. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
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@ -1,13 +1,14 @@
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/** @file
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Arm Gic cpu parser.
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Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
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Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Reference(s):
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- linux/Documentation/devicetree/bindings/arm/cpus.yaml
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- linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
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- linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
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- linux/Documentation/devicetree/bindings/arm/pmu.yaml
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**/
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#include "FdtHwInfoParser.h"
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@ -34,6 +35,21 @@ STATIC CONST COMPATIBILITY_INFO CpuCompatibleInfo = {
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CpuCompatibleStr
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};
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/** Pmu compatible strings.
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Any other "compatible" value is not supported by this module.
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*/
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STATIC CONST COMPATIBILITY_STR PmuCompatibleStr[] = {
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{ "arm,armv8-pmuv3" }
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};
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/** COMPATIBILITY_INFO structure for the PmuCompatibleStr.
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*/
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CONST COMPATIBILITY_INFO PmuCompatibleInfo = {
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ARRAY_SIZE (PmuCompatibleStr),
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PmuCompatibleStr
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};
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/** Parse a "cpu" node.
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@param [in] Fdt Pointer to a Flattened Device Tree (Fdt).
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@ -639,6 +655,111 @@ GicCv3IntcNodeParser (
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return EFI_SUCCESS;
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}
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/** Parse a Pmu compatible node, extracting Pmu information.
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This function modifies a CM_OBJ_DESCRIPTOR object.
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The following CM_ARM_GICC_INFO fields are patched:
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- PerformanceInterruptGsiv;
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@param [in] Fdt Pointer to a Flattened Device Tree (Fdt).
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@param [in] GicIntcNode Offset of a Gic compatible
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interrupt-controller node.
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@param [in, out] GicCCmObjDesc The CM_ARM_GICC_INFO to patch.
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@retval EFI_SUCCESS The function completed successfully.
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@retval EFI_ABORTED An error occurred.
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@retval EFI_INVALID_PARAMETER Invalid parameter.
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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GicCPmuNodeParser (
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IN CONST VOID *Fdt,
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IN INT32 GicIntcNode,
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IN OUT CM_OBJ_DESCRIPTOR *GicCCmObjDesc
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)
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{
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EFI_STATUS Status;
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INT32 IntCells;
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INT32 PmuNode;
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UINT32 PmuNodeCount;
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UINT32 PmuIrq;
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UINT32 Index;
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CM_ARM_GICC_INFO *GicCInfo;
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CONST UINT8 *Data;
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INT32 DataSize;
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if (GicCCmObjDesc == NULL) {
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ASSERT (GicCCmObjDesc != NULL);
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return EFI_INVALID_PARAMETER;
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}
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GicCInfo = (CM_ARM_GICC_INFO *)GicCCmObjDesc->Data;
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PmuNode = 0;
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// Count the number of pmu nodes.
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Status = FdtCountCompatNodeInBranch (
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Fdt,
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0,
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&PmuCompatibleInfo,
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&PmuNodeCount
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);
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if (EFI_ERROR (Status)) {
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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if (PmuNodeCount == 0) {
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return EFI_NOT_FOUND;
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}
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Status = FdtGetNextCompatNodeInBranch (
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Fdt,
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0,
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&PmuCompatibleInfo,
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&PmuNode
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);
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if (EFI_ERROR (Status)) {
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ASSERT_EFI_ERROR (Status);
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if (Status == EFI_NOT_FOUND) {
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// Should have found the node.
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Status = EFI_ABORTED;
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}
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}
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// Get the number of cells used to encode an interrupt.
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Status = FdtGetInterruptCellsInfo (Fdt, GicIntcNode, &IntCells);
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if (EFI_ERROR (Status)) {
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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Data = fdt_getprop (Fdt, PmuNode, "interrupts", &DataSize);
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if ((Data == NULL) || (DataSize != (IntCells * sizeof (UINT32)))) {
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// If error or not 1 interrupt.
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ASSERT (Data != NULL);
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ASSERT (DataSize == (IntCells * sizeof (UINT32)));
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return EFI_ABORTED;
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}
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PmuIrq = FdtGetInterruptId ((CONST UINT32 *)Data);
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// Only supports PPI 23 for now.
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// According to BSA 1.0 s3.6 PPI assignments, PMU IRQ ID is 23. A non BSA
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// compliant system may assign a different IRQ for the PMU, however this
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// is not implemented for now.
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if (PmuIrq != BSA_PMU_IRQ) {
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ASSERT (PmuIrq == BSA_PMU_IRQ);
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return EFI_ABORTED;
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}
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for (Index = 0; Index < GicCCmObjDesc->Count; Index++) {
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GicCInfo[Index].PerformanceInterruptGsiv = PmuIrq;
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}
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return EFI_SUCCESS;
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}
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/** CM_ARM_GICC_INFO parser function.
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This parser expects FdtBranch to be the "\cpus" node node.
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@ -649,7 +770,7 @@ GicCv3IntcNodeParser (
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UINT32 AcpiProcessorUid; // {Populated}
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UINT32 Flags; // {Populated}
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UINT32 ParkingProtocolVersion; // {default = 0}
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UINT32 PerformanceInterruptGsiv; // {default = 0}
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UINT32 PerformanceInterruptGsiv; // {Populated}
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UINT64 ParkedAddress; // {default = 0}
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UINT64 PhysicalBaseAddress; // {Populated}
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UINT64 GICV; // {Populated}
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@ -764,6 +885,13 @@ ArmGicCInfoParser (
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goto exit_handler;
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}
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// Parse the Pmu Interrupt.
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Status = GicCPmuNodeParser (Fdt, IntcNode, NewCmObjDesc);
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if (EFI_ERROR (Status) && (Status != EFI_NOT_FOUND)) {
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ASSERT_EFI_ERROR (Status);
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goto exit_handler;
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}
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// Add all the CmObjs to the Configuration Manager.
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Status = AddMultipleCmObj (FdtParserHandle, NewCmObjDesc, 0, NULL);
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if (EFI_ERROR (Status)) {
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@ -1,7 +1,7 @@
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/** @file
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Arm Gic cpu parser.
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Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
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Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Reference(s):
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@ -12,6 +12,10 @@
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#ifndef ARM_GICC_PARSER_H_
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#define ARM_GICC_PARSER_H_
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/* According to BSA 1.0 s3.6 PPI assignments, PMU IRQ ID is 23.
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*/
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#define BSA_PMU_IRQ 23
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/** CM_ARM_GICC_INFO parser function.
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This parser expects FdtBranch to be the "\cpus" node node.
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UINT32 AcpiProcessorUid; // {Populated}
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UINT32 Flags; // {Populated}
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UINT32 ParkingProtocolVersion; // {default = 0}
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UINT32 PerformanceInterruptGsiv; // {default = 0}
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UINT32 PerformanceInterruptGsiv; // {Populated}
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UINT64 ParkedAddress; // {default = 0}
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UINT64 PhysicalBaseAddress; // {Populated}
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UINT64 GICV; // {Populated}
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