mirror of https://github.com/acidanthera/audk.git
MdeModulePkg/UfsPassThruDxe: fix the bit in UFS_HC_UTRLDBR_OFFSET reg
When UPIU packet is sent, (BIT0 << Slot) should be set according to context. But BIT0 is used without Slot when UfsWaitMemSet () is invoked. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Feng Tian <feng.tian@intel.com>
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@ -954,7 +954,7 @@ UfsRwDeviceDesc (
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//
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// Wait for the completion of the transfer request.
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//
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Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0, 0, Packet.Timeout);
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Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0 << Slot, 0, Packet.Timeout);
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if (EFI_ERROR (Status)) {
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goto Exit;
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}
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@ -1077,7 +1077,7 @@ UfsRwAttributes (
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//
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// Wait for the completion of the transfer request.
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//
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Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0, 0, Packet.Timeout);
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Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0 << Slot, 0, Packet.Timeout);
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if (EFI_ERROR (Status)) {
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goto Exit;
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}
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@ -1201,7 +1201,7 @@ UfsRwFlags (
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//
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// Wait for the completion of the transfer request.
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//
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Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0, 0, Packet.Timeout);
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Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0 << Slot, 0, Packet.Timeout);
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if (EFI_ERROR (Status)) {
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goto Exit;
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}
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@ -1368,7 +1368,7 @@ UfsExecNopCmds (
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//
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// Wait for the completion of the transfer request.
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//
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Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0, 0, UFS_TIMEOUT);
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Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0 << Slot, 0, UFS_TIMEOUT);
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if (EFI_ERROR (Status)) {
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goto Exit;
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}
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@ -1534,7 +1534,7 @@ UfsExecScsiCmds (
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//
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// Wait for the completion of the transfer request.
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//
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Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0, 0, Packet->Timeout);
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Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0 << TransReq->Slot, 0, Packet->Timeout);
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if (EFI_ERROR (Status)) {
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goto Exit;
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}
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