mirror of https://github.com/acidanthera/audk.git
ArmPkg: remove unused ArmGicSecLib library implementation
This module is not used anywhere under edk2 or edk2-platforms, so let's remove it. This removes the only dependency on ArmPlatformLib from ArmPkg. While at it, remove a mention of ArmPlatformPkg from a comment in the .dec file as well. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Ard Biesheuvel
parent
4cebe0453f
commit
142fa386eb
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@ -224,8 +224,8 @@
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[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
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[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
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# System Memory (DRAM): These PCDs define the region of in-built system memory
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# System Memory (DRAM): These PCDs define the region of in-built system memory
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# Some platforms can get DRAM extensions, these additional regions will be declared
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# Some platforms can get DRAM extensions, these additional regions may be
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# to UEFI by ArmPlatformLib
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# declared to UEFI using separate resource descriptor HOBs
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gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
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gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
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gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
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gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
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@ -121,7 +121,6 @@
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ArmPkg/Drivers/CpuPei/CpuPei.inf
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ArmPkg/Drivers/CpuPei/CpuPei.inf
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ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
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ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
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ArmPkg/Drivers/ArmGic/ArmGicLib.inf
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ArmPkg/Drivers/ArmGic/ArmGicLib.inf
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ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
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ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
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ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
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ArmPkg/Drivers/TimerDxe/TimerDxe.inf
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ArmPkg/Drivers/TimerDxe/TimerDxe.inf
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@ -1,52 +0,0 @@
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#/* @file
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# Copyright (c) 2011-2015, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#*/
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = ArmGicSecLib
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FILE_GUID = 85f3cf80-b5f4-11df-9855-0002a5d5c51b
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MODULE_TYPE = SEC
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VERSION_STRING = 1.0
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LIBRARY_CLASS = ArmGicLib
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[Sources]
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ArmGicLib.c
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ArmGicSecLib.c
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GicV2/ArmGicV2Lib.c
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GicV2/ArmGicV2SecLib.c
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[Sources.ARM]
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GicV3/Arm/ArmGicV3.S | GCC
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GicV3/Arm/ArmGicV3.asm | RVCT
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[Sources.AARCH64]
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GicV3/AArch64/ArmGicV3.S
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[Packages]
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ArmPkg/ArmPkg.dec
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ArmPlatformPkg/ArmPlatformPkg.dec
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MdePkg/MdePkg.dec
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MdeModulePkg/MdeModulePkg.dec
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[LibraryClasses]
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ArmLib
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DebugLib
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IoLib
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ArmGicArchLib
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[Pcd]
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gArmPlatformTokenSpaceGuid.PcdCoreCount
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[FeaturePcd]
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gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
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@ -1,100 +0,0 @@
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/** @file
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*
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* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/ArmGicLib.h>
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/*
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* This function configures the all interrupts to be Non-secure.
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*
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*/
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VOID
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EFIAPI
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ArmGicV2SetupNonSecure (
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IN UINTN MpId,
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IN INTN GicDistributorBase,
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IN INTN GicInterruptInterfaceBase
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)
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{
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UINTN InterruptId;
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UINTN CachedPriorityMask;
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UINTN Index;
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UINTN MaxInterrupts;
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CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
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// Set priority Mask so that no interrupts get through to CPU
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
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InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
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MaxInterrupts = ArmGicGetMaxNumInterrupts (GicDistributorBase);
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// Only try to clear valid interrupts. Ignore spurious interrupts.
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while ((InterruptId & 0x3FF) < MaxInterrupts) {
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// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
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ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId);
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// Next
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InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
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}
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// Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
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if (ArmPlatformIsPrimaryCore (MpId)) {
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// Ensure all GIC interrupts are Non-Secure
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for (Index = 0; Index < (MaxInterrupts / 32); Index++) {
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
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}
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} else {
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// The secondary cores only set the Non Secure bit to their banked PPIs
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);
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}
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// Ensure all interrupts can get through the priority mask
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
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}
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VOID
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EFIAPI
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ArmGicV2EnableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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)
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{
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// Set Priority Mask to allow interrupts
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
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// Enable CPU interface in Secure world
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// Enable CPU interface in Non-secure World
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// Signal Secure Interrupts to CPU using FIQ line *
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
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ARM_GIC_ICCICR_ENABLE_SECURE |
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ARM_GIC_ICCICR_ENABLE_NS |
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ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
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}
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VOID
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EFIAPI
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ArmGicV2DisableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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)
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{
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UINT32 ControlValue;
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// Disable CPU interface in Secure world and Non-secure World
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ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));
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}
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