From 14fa71247c49f79dd8b545265f110eb9f47f899f Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Thu, 6 Apr 2017 12:59:38 +0100 Subject: [PATCH] ArmPlatformPkg/HdLcdArmVExpressLib: use write-combine mapping for VRAM Replace the uncached memory mapping of the framebuffer with a write- combining one. This improves performance, and avoids issues with unaligned accesses and DC ZVA instructions performed by the accelerated memcpy/memset routines. Instead of manipulating the memory attributes directly, use the SetMemorySpaceAttributes() DXE services, which validates the attributes against the capabilities of the region before making the actual change. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Jeremy Linton Tested-by: Ryan Harkin Reviewed-by: Leif Lindholm --- .../Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c | 12 ++++-------- .../HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf | 3 ++- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c index 67b2f14bee..b1106ee19b 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c @@ -18,11 +18,11 @@ #include #include #include +#include #include #include #include -#include #include #include @@ -119,7 +119,6 @@ LcdPlatformGetVram ( ) { EFI_STATUS Status; - EFI_CPU_ARCH_PROTOCOL *Cpu; EFI_ALLOCATE_TYPE AllocationType; // Set the vram size @@ -138,12 +137,9 @@ LcdPlatformGetVram ( return Status; } - // Ensure the Cpu architectural protocol is already installed - Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu); - ASSERT_EFI_ERROR(Status); - - // Mark the VRAM as un-cacheable. The VRAM is inside the DRAM, which is cacheable. - Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC); + // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which is cacheable. + Status = gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, + EFI_MEMORY_WC); ASSERT_EFI_ERROR(Status); if (EFI_ERROR(Status)) { gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf index 7807247379..dff17e86fd 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf @@ -32,8 +32,9 @@ HdLcdArmVExpress.c ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec [LibraryClasses] - BaseLib ArmPlatformSysConfigLib + BaseLib + DxeServicesTableLib [Protocols] gEfiEdidDiscoveredProtocolGuid # Produced