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UefiCpuPkg/CpuExceptionHandlerLib: Setup single step in #PF handler 

Once the #PF handler has set the page to be 'present', there should
be a way to reset it to 'not-present'. 'TF' bit in EFLAGS can be used
for this purpose. 'TF' bit will be set in interrupted function context
so that it can be triggered once the cpu control returns back to the
instruction causing #PF and re-execute it.

This is an necessary step to implement non-stop mode for Heap Guard
and NULL Pointer Detection feature.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Jian J Wang 2018-08-09 16:17:19 +08:00
parent 8f2613628a
commit 16b918bbaf
3 changed files with 12 additions and 3 deletions
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7
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm
View File

@ -383,6 +383,13 @@ ErrorCodeAndVectorOnStack:
pop dword [ebp - 4] pop dword [ebp - 4]
mov esp, ebp mov esp, ebp
pop ebp pop ebp
; Enable TF bit after page fault handler runs
cmp dword [esp], 14 ; #PF?
jne .5
bts dword [esp + 16], 8 ; EFLAGS
.5:
add esp, 8 add esp, 8
cmp dword [esp - 16], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler cmp dword [esp - 16], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
jz DoReturn jz DoReturn

4
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
View File

@ -355,10 +355,8 @@ o16 mov [ecx + IA32_TSS._SS], ax
movzx ebx, word [ecx + IA32_TSS._CS] movzx ebx, word [ecx + IA32_TSS._CS]
mov [eax - 0x8], ebx ; create CS in old stack mov [eax - 0x8], ebx ; create CS in old stack
mov ebx, dword [ecx + IA32_TSS.EFLAGS] mov ebx, dword [ecx + IA32_TSS.EFLAGS]
bts ebx, 8 bts ebx, 8 ; Set TF
mov [eax - 0x4], ebx ; create eflags in old stack mov [eax - 0x4], ebx ; create eflags in old stack
mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old TSS
mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
sub eax, 0xc ; minus 12 byte sub eax, 0xc ; minus 12 byte
mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer

4
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
View File

@ -336,6 +336,10 @@ HasErrorCode:
pop r15 pop r15
mov rsp, rbp mov rsp, rbp
cmp qword [rbp + 8], 14 ; #PF?
jne .1
bts qword [rsp + 40], 8 ; RFLAGS.TF
.1:
pop rbp pop rbp
add rsp, 16 add rsp, 16
cmp qword [rsp - 32], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler cmp qword [rsp - 32], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler